From nobody Sun Feb 8 22:17:44 2026 Received: from mout-p-103.mailbox.org (mout-p-103.mailbox.org [80.241.56.161]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C4381DED4B; Sun, 20 Apr 2025 17:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.161 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170763; cv=none; b=p93i8/G6XkxBjeBDBr4y6O5JiPwfrNK+Fm9YwfN7BfUw1zPcrADi9Y9Cvtw+ONnpPXIESf5n3IcHVqhbvothNWSoit/68dI40f1dJGKwsGGzeqEjcFf+LJfxwUq78u1r5gtVrdf0QT7GZTZ95vgRJpQDM5iS84bMyBPhzlrxETo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170763; c=relaxed/simple; bh=pgVts3zH8/3m01mUpr268z1ZNkTJdEHKJD4wiVVaTgU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dBuR8VcW3Tm0Xs+/UQBZVuCyip6BOIPJ1huiMnt5KURUGgYG2EUvrJFkEe1uJlT6gy8UqFzoVCidSODRcXgFOzbNhp8mVYg17ZC8d51QYdCcEEk6s7qZlWHLYmFRtDEVN9gCFdSjogwW5NeVzM1RcW1H+AnELz4wcxu56iRhz44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=WP8Ty9zg; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=BZcbMBrg; arc=none smtp.client-ip=80.241.56.161 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="WP8Ty9zg"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="BZcbMBrg" Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:b231:465::102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 4ZgbN55QxGz9t72; Sun, 20 Apr 2025 19:39:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KLSTm2eAkY0GGbHRw8VQP7KYnuUYCyjh+76myopty7g=; b=WP8Ty9zgDEPJPjjgJfUI6a9Zo0jSm+sC5xSJQynbtc+5h83NOWaZO+uRP+FNAKDWAS3HqC WviBXRMzHyoB4woL3Kd0F7TWdkirA4L6uZIQsC9fb7jaJdcf8dBvCQPuDzl3vnnxmmiXut 1T4i3iAOFF6LRHC3EYDdjZxMw5Oa2O1hwvzMUH8cf6n9/nVvbmaIcZ6dO992ZMhIjK+CZL Mcnuv35T+4xq/fmAxyFqMrpg14uar5B+v1mThMpGSYg7L7VsXZ4DY+NBNUEuGglrC4+quX w4YDAgPqG4rcaOmGUpOOvp/K5AGcvdKBsTsBRSxVyXJsCf4vbdo+fwVP6rPckg== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170755; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KLSTm2eAkY0GGbHRw8VQP7KYnuUYCyjh+76myopty7g=; b=BZcbMBrgar3ZHd+5I5TjGbywYr1hEUGLl0v4BvCPlzpy13A2iJbARKTWi59RN64MBvFpav eq6FF7U2EUU/memo2SD2v0L+OZ9Q22RJo4/HsVEYs8His9Eo/u/tUzmv0QzxRCDfeOJ2/V aDL9WgTrXmqzqJT+0P1U0tddzu7hUlrd6kGiAWp6uOCLRcHhOJ9ZohAayjZ/TaIfchC3Vk kJoUiT9ZqH8fopfB/c1Til/M4rUYzWv3vLrSOpQLZ8ociXtKC/En5NMly0AWNoiL0LoKI1 6O4SDEvzk2RZ9TkybhhKrLErBKk9QEIkq89nXjiJKdVDXgL/ZnrphC4ZaZb4Ng== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Krzysztof Kozlowski , Geert Uytterhoeven , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add Retronix Technology Inc. Date: Sun, 20 Apr 2025 19:36:27 +0200 Message-ID: <20250420173829.200553-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> References: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 3dcd1b8fa1fd642b3a1 X-MBO-RS-META: y4gyayeuk88anxeym8ykb3wbk9orzzkc X-Rspamd-Queue-Id: 4ZgbN55QxGz9t72 Add vendor prefix for Retronix Technology Inc. https://www.retronix.com.tw/en/about.html Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Tested-by: Niklas S=C3=B6derlund Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: "Rafa=C5=82 Mi=C5=82ecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add AB from Krzysztof - Add RB from Geert - Add TB from Niklas V3: No change --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index c2753656ae8be..836b446132686 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1264,6 +1264,8 @@ patternProperties: description: Renesas Electronics Corporation "^rervision,.*": description: Shenzhen Rervision Technology Co., Ltd. + "^retronix,.*": + description: Retronix Technology Inc. "^revotics,.*": description: Revolution Robotics, Inc. (Revotics) "^rex,.*": --=20 2.47.2 From nobody Sun Feb 8 22:17:44 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 744AF1E991A; Sun, 20 Apr 2025 17:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170770; cv=none; b=i6AiqJs+Yx0l5/zN7zJpTbMCSJyf5SFSeloibEsDGRYQyYg+2nhjgp1Si/EKcQlbnZ0yS0tmBedNJ8D2NhgcI2sx5jYju59VEiDJqzatb4PeMorZr8dM1FPTrMOkf9Y+CkG8Xcgx2I5jB/jUVaZ73jdsQQwvogkS6vTaxag9mnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170770; c=relaxed/simple; bh=TW9Jtl60AgYvjUyXlVJa7j16Ky2ZLcA0QFeNX/9VaVQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bDkDwnCoiTubW0d5oaoP1Jgix32Gf+exn9rsZ7IRMI/S9FvPo7drXfMa8K55Gcak5kPIig+4JBjRGhIR1uTCR/8t0P9sXyOe3sjQ8gmxzOO661xukoRLFMKpujEGC+ypQfWc032/XQanQgMyRGE9o+FmqhbpbivGwDgoGAZu3TQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=THhdTyyK; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=DGfWaqCR; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="THhdTyyK"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="DGfWaqCR" Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:b231:465::102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4ZgbN84NRdz9tXv; Sun, 20 Apr 2025 19:39:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170760; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ycNAhVHWprcmlx0NXKu/950Cj9ZtnGPvQSTzBEdE08o=; b=THhdTyyK3/5qfdfEg/XowqSZGbKcRCdTnSZXIfUIbHIRkWOiLD7TnI3OuyV4rTab8vnhT3 H97/R08gjpeJ2fR6383yoLhmk7ze7WbpK2wMFW4tWUbY1sUv6MfuFQjcrRAioamvzPS1Gg VcloEL9g6FORTQtkSzhZLUeUNtRtv5/mRlLASm6mhySDwr4bSfj/CyGqye3jktKodCf/PF 7LPOmfBJTgYQHndZSZs8uauCseaS13lIx2RnB1ec/uLykUUleIQxFR+bc/M5HuqV/T0v+c 5Wwt4MWO2+E1rQ/HrRjMZQGPsGlkeHY5PZhFMFuuS1vI6nchT4q4hjpbxvBt6Q== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170758; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ycNAhVHWprcmlx0NXKu/950Cj9ZtnGPvQSTzBEdE08o=; b=DGfWaqCRZZ5cgG2HzD2XJp47rEMoF8J52aYSGQKhX6DLS+NCgZrlPwAhZ3JZmDyw0ndvbr PiLaQpji5y+DF29exHvDOKYQOdvbvU80pnRoT/OpvBL71X9v17b8j+YF8Bul+d+G06XRno 8xMvxi08lffMJhMjShdWLLTlucWNSGWfOoM4xkAzcMzxkMofg0xGkHwYJ25TyjM7srN9hu 9rcv03htdjGMIWQ4Z6wuhjbd0bAjupNxbdrUS1d3h2d3XuOTF8UHj0LqdpHvu0nOSTJlFp tviTaw8uP2ciK/AXm4t2BpKeV6VmBXNaML1cZRIaIhGYJg9F6k69o0Wl3fKQjQ== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Krzysztof Kozlowski , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 2/3] dt-bindings: soc: renesas: Document Retronix R-Car V4H Sparrow Hawk board support Date: Sun, 20 Apr 2025 19:36:28 +0200 Message-ID: <20250420173829.200553-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> References: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: ffqcsgydgpipf78ye5gg7qhhp65tap84 X-MBO-RS-ID: 1ce5a253f8c40f34f9f X-Rspamd-Queue-Id: 4ZgbN84NRdz9tXv Document Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H E= S3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit etherne= t, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD port= s, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe S= SD, debug UART and JTAG. Acked-by: Krzysztof Kozlowski Tested-by: Niklas S=C3=B6derlund Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: "Rafa=C5=82 Mi=C5=82ecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add AB from Krzysztof - Add TB from Niklas - Rename {Renesas,Retronix} R-Car V4H Sparrow Hawk in commit message and update R-Car V4H ES3.0 to Renesas R-Car V4H ES3.0 V3: No change --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index 0389355b9ecad..3acfb835dd375 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -375,6 +375,13 @@ properties: - renesas,r8a779g3 # ES3.x - const: renesas,r8a779g0 =20 + - description: R-Car V4H (R8A779G3) + items: + - enum: + - retronix,sparrow-hawk # Sparrow Hawk board + - const: renesas,r8a779g3 # ES3.x + - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) items: - enum: --=20 2.47.2 From nobody Sun Feb 8 22:17:44 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99C1F20C028; Sun, 20 Apr 2025 17:39:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170774; cv=none; b=qb2qpAZjGn+BUseLfgmfj/NEOO0XNEit8TfxpPaqzY/OXGFSa4fAi+yVbbNIGhQLvhKX7sX9TP3U0Y6vTaJxoH8GPZ+TEugfO4sY3Qq/hpA9aWulKnaWn8iF/1YylNegS5RmO1X44rpcQFFCzaJUWeWZXLXVd4RSauIMWSpNs2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745170774; c=relaxed/simple; bh=pa9bJmv0EdHRdLTQXPjyXBU2ifElr8CakzPvv7Ftibc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X+kN5oXVW3OgzGJcrk3zedXMsnGJBMkG2q3aRzM929W7dXw9SQB6aLGK/K68OqM9wpQMBBt7I35wb3+S3ymJ8HLUxbnzc6CzCwjRh3iZCeq2lK+hvadoX2GCmxBiOHnKdN7JEVV+gaJlxZp0JcF54993RqcbPACJN37lKOLmPkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=AMAE1F+K; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=bJctHwMF; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="AMAE1F+K"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="bJctHwMF" Received: from smtp102.mailbox.org (smtp102.mailbox.org [10.196.197.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4ZgbND0VMrz9sbY; Sun, 20 Apr 2025 19:39:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170764; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tzPZpUyAlFgnc6sj7xHgOV0PsH4Ph49bIzG0GCTxjb4=; b=AMAE1F+KMufRWTXPpmGp3SXD6ze5aDEsdcbJWcVRbEjSCyUTSYksqWnhYeZkzY2Q6NN2pv m8vRDmtfxkshPi+eprRt+aFewm6d7JP12QdLKWWoNpwpgLHU4EeKZ6YIQRSK5AyXByg+oy YEs3kLNEzeyc5FAHSbWJDnSCn/gaFsTKHr5OBzDu+DU4vmVXL4qsDgW98gcMGoUdQ1AuH2 q1wwHaru1zCxhI2TE2K0OmMMEUlWNAb+MUNvf5jfDfVVycO3oddCZ3ztLt4UJJnx73IlMV 6EwlESs4CXNFjPIjCYvIcMRpEydKyhkFtoDuVQ9KzV8zeAao3pwTRI1mQazREQ== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1745170762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tzPZpUyAlFgnc6sj7xHgOV0PsH4Ph49bIzG0GCTxjb4=; b=bJctHwMFb/znXNfaC5b5FffzK1HHsQ53/raQcZIGr1h99+FX+TQMdmKhueLl19jdkB5VPc J9dqKKzXSEQatJhxz2RFyqCRVS0s7AYCzOhl5aHjXaYuZmc2Yiu8zKz5WNcuX5305sVvyP 5lLBtiWGZMOCMFtu/yC4QCA6q/22kKyi+BSVRxsV9/q0ax1P1YoMxD5Y6+UoPej8U7LaQD g8yq4L0DBKBoo12koNmnSW1q6rGVExxyHiezzQzR4mimZNhnmJ0mpwOrjnplArTMOpG3/N SHBLgYLwHYF/in76LSg+oBkKm7M4n3d0LKrRKOolF7thQEj2RNSDKSaWTrFj3w== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Kuninori Morimoto , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support Date: Sun, 20 Apr 2025 19:36:29 +0200 Message-ID: <20250420173829.200553-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> References: <20250420173829.200553-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: e15mmaq7tqdfmqcf9qf7uwohqyo9xqbs X-MBO-RS-ID: 2b801e25da5dbab06a7 Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit etherne= t, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD port= s, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe S= SD, debug UART and JTAG. Tested-by: Kuninori Morimoto Tested-by: Niklas S=C3=B6derlund Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: "Rafa=C5=82 Mi=C5=82ecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add TB from Morimoto-san - Enable pwm-fan and set PWM to full by default, to achieve maximum cooling effect unless configured otherwise. The blower fan is user supplied device, hence this default. - Add arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso to demonstrate user supplied blower fan configuration. - Add TB from Niklas - Rename pins{_,-}mdio, pins{_,-}mii, scif{_,-}clk, sd{_,-}uhs - Add serial1 =3D &hscif1; and serial2 =3D &hscif3 - Rename {Renesas,Retronix} R-Car V4H Sparrow Hawk in commit message and update R-Car V4H ES3.0 to Renesas R-Car V4H ES3.0 V3: - Remove Renesas 9FGV0441 PCIe clock generator node from I2C bus, remove clk-x8 clock node used by the PCIe clock generator, use pcie0_clkref and pcie1_clkref to describe 100 MHz clock supplied to both the PCIe controller and bus for now. The 9FGV0441 can and does operate autonomously without any configuration. The 9FGV0441 description will be added in a separate follow up patch, once it is clear how to describe separate controller and bus clock in DT. --- arch/arm64/boot/dts/renesas/Makefile | 4 + .../r8a779g3-sparrow-hawk-fan-pwm.dtso | 43 ++ .../dts/renesas/r8a779g3-sparrow-hawk.dts | 666 ++++++++++++++++++ 3 files changed, 713 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-p= wm.dtso create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index d8a8d7ca4c58a..b24dddee3827c 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -94,6 +94,10 @@ dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g2-white-hawk-sin= gle.dtb r8a779g2-white-hawk-single-ard-audio-da7212-dtbs :=3D r8a779g2-white-hawk-= single.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g2-white-hawk-single-ard-audio-da72= 12.dtb =20 +dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g3-sparrow-hawk.dtb +r8a779g3-sparrow-hawk-fan-pwm-dtbs :=3D r8a779g3-sparrow-hawk.dtb r8a779g3= -sparrow-hawk-fan-pwm.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g3-sparrow-hawk-fan-pwm.dtb + dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g3-white-hawk-single.dtb r8a779g3-white-hawk-single-ard-audio-da7212-dtbs :=3D r8a779g3-white-hawk-= single.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g3-white-hawk-single-ard-audio-da72= 12.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso= b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso new file mode 100644 index 0000000000000..50d53c8d76c5b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the PWM controlled blower fan in connector J3:F= AN + * on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + * + * Example usage: + * + * # Localize hwmon sysfs directory that matches the PWM fan, + * # enable the PWM fan, and configure the fan speed manually. + * r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name + * /sys/class/hwmon/hwmon0/name:sensor1_thermal + * /sys/class/hwmon/hwmon1/name:sensor2_thermal + * /sys/class/hwmon/hwmon2/name:sensor3_thermal + * /sys/class/hwmon/hwmon3/name:sensor4_thermal + * /sys/class/hwmon/hwmon4/name:pwmfan + * ^ ^^^^^^ + * + * # Select mode 2 , enable fan PWM and regulator and keep them enabled. + * # For details, see Linux Documentation/hwmon/pwm-fan.rst + * r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable + * + * # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full = speed . + * # Fan speed 101 is about 2/5 of the PWM fan speed: + * r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1 + */ + +/dts-v1/; +/plugin/; + +/* + * Override default PWM fan settings. For a list of available properties, + * see schema Documentation/devicetree/bindings/hwmon/pwm-fan.yaml . + */ +&fan { + /* Available cooling levels */ + cooling-levels =3D <0 50 100 150 200 255>; + /* Four pulses of tacho signal per one revolution */ + pulses-per-revolution =3D <4>; + /* PWM period: 100us ~=3D 10 kHz */ + pwms =3D <&pwm0 0 100000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/a= rm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts new file mode 100644 index 0000000000000..b109095a0d872 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +/dts-v1/; +#include + +#include "r8a779g3.dtsi" + +/ { + model =3D "Retronix Sparrow Hawk board based on r8a779g3"; + compatible =3D "retronix,sparrow-hawk", "renesas,r8a779g3", + "renesas,r8a779g0"; + + aliases { + ethernet0 =3D &avb0; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + serial0 =3D &hscif0; + serial1 =3D &hscif1; + serial2 =3D &hscif3; + spi0 =3D &rpc; + }; + + chosen { + bootargs =3D "ignore_loglevel rw root=3D/dev/nfs ip=3Don"; + stdout-path =3D "serial0:921600n8"; + }; + + /* Page 31 / FAN */ + fan: pwm-fan { + pinctrl-0 =3D <&irq4_pins>; + pinctrl-names =3D "default"; + compatible =3D "pwm-fan"; + #cooling-cells =3D <2>; + interrupts-extended =3D <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; + /* + * The fan model connected to this device can be selected + * by user. Set "cooling-levels" DT property to single 255 + * entry to force the fan PWM into constant HIGH, which + * forces the fan to spin at maximum RPM, thus providing + * maximum cooling to this device and protection against + * misconfigured PWM duty cycle to the fan. + * + * User has to configure "pwms" and "pulses-per-revolution" + * DT properties according to fan datasheet first, and then + * extend "cooling-levels =3D <0 m n ... 255>" property to + * achieve proper fan control compatible with fan model + * installed by user. + */ + cooling-levels =3D <255>; + pulses-per-revolution =3D <2>; + pwms =3D <&pwm0 0 50000>; + }; + + /* + * Page 15 / LPDDR5 + * + * This configuration listed below is for the 8 GiB board variant + * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. + * + * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on + * the board is automatically handled by the bootloader, which + * adjusts the correct DRAM size into the memory nodes below. + */ + memory@48000000 { + device_type =3D "memory"; + /* first 128MB is reserved for secure area. */ + reg =3D <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type =3D "memory"; + reg =3D <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type =3D "memory"; + reg =3D <0x6 0x00000000 0x1 0x00000000>; + }; + + /* Page 27 / DSI to Display */ + mini-dp-con { + compatible =3D "dp-connector"; + label =3D "CN6"; + type =3D "full-size"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint =3D <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.2V"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Page 27 / DSI to Display */ + sn65dsi86_refclk: clk-x9 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <38400000>; + }; + + /* Page 17 uSD-Slot */ + vcc_sdhi: regulator-vcc-sdhi { + compatible =3D "regulator-gpio"; + regulator-name =3D "SDHI VccQ"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio8 13 GPIO_ACTIVE_HIGH>; + gpios-states =3D <1>; + states =3D <3300000 0>, <1800000 1>; + }; +}; + +/* Page 22 / Ether_AVB0 */ +&avb0 { + pinctrl-0 =3D <&avb0_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&avb0_phy>; + tx-internal-delay-ps =3D <2000>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ + compatible =3D "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps =3D <1500>; + reg =3D <0>; + /* AVB0_PHY_INT_V */ + interrupts-extended =3D <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + /* GP7_10/AVB0_RESETN_V */ + reset-gpios =3D <&gpio7 10 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <300>; + }; + }; +}; + +/* Page 28 / CANFD_IF */ +&can_clk { + clock-frequency =3D <40000000>; +}; + +/* Page 28 / CANFD_IF */ +&canfd { + pinctrl-0 =3D <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + channel3 { + status =3D "okay"; + }; + + channel4 { + status =3D "okay"; + }; +}; + +/* Page 27 / DSI to Display */ +&dsi1 { + status =3D "okay"; + + ports { + port@1 { + dsi1_out: endpoint { + remote-endpoint =3D <&sn65dsi86_in>; + data-lanes =3D <1 2 3 4>; + }; + }; + }; +}; + +/* Page 27 / DSI to Display */ +&du { + status =3D "okay"; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extal_clk { /* X3 */ + clock-frequency =3D <16666666>; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extalr_clk { /* X2 */ + clock-frequency =3D <32768>; +}; + +/* Page 26 / 2230 Key M M.2 */ +&gpio4 { + /* 9FGV0441 nOE inputs 0 and 1 */ + pcie-m2-oe-hog { + gpio-hog; + gpios =3D <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "PCIe-CLK-nOE-M2"; + }; + + /* 9FGV0441 nOE inputs 2 and 3 */ + pcie-usb-oe-hog { + gpio-hog; + gpios =3D <22 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "PCIe-CLK-nOE-USB"; + }; +}; + +/* Page 23 / DEBUG */ +&hscif0 { /* FTDI ADBUS[3:0] */ + pinctrl-0 =3D <&hscif0_pins>; + pinctrl-names =3D "default"; + uart-has-rtscts; + bootph-all; + + status =3D "okay"; +}; + +/* Page 23 / DEBUG */ +&hscif1 { /* FTDI BDBUS[3:0] */ + pinctrl-0 =3D <&hscif1_pins>; + pinctrl-names =3D "default"; + uart-has-rtscts; + + status =3D "okay"; +}; + +/* Page 24 / UART */ +&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ + pinctrl-0 =3D <&hscif3_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +/* Page 24 / I2C SWITCH */ +&i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + clock-frequency =3D <400000>; + status =3D "okay"; + + mux@71 { + compatible =3D "nxp,pca9544"; /* TCA9544 */ + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + vdd-supply =3D <®_3p3v>; + + i2c0_mux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Page 27 / DSI to Display */ + bridge@2c { + pinctrl-0 =3D <&irq0_pins>; + pinctrl-names =3D "default"; + + compatible =3D "ti,sn65dsi86"; + reg =3D <0x2c>; + + clocks =3D <&sn65dsi86_refclk>; + clock-names =3D "refclk"; + + interrupts-extended =3D <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios =3D <&gpio2 1 GPIO_ACTIVE_HIGH>; + + vccio-supply =3D <®_1p8v>; + vpll-supply =3D <®_1p8v>; + vcca-supply =3D <®_1p2v>; + vcc-supply =3D <®_1p2v>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + sn65dsi86_in: endpoint { + remote-endpoint =3D <&dsi1_out>; + }; + }; + + port@1 { + reg =3D <1>; + sn65dsi86_out: endpoint { + remote-endpoint =3D <&mini_dp_con_in>; + }; + }; + }; + }; + }; + + i2c0_mux1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN0 */ +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN1 */ +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; +}; + +/* Page 31 / IO_CN */ +&i2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; +}; + +/* Page 31 / IO_CN */ +&i2c4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c4_pins>; + pinctrl-names =3D "default"; +}; + +/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ +&i2c5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c5_pins>; + pinctrl-names =3D "default"; +}; + +/* Page 17 uSD-Slot */ +&mmc0 { + pinctrl-0 =3D <&sd_pins>; + pinctrl-1 =3D <&sd_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + bus-width =3D <4>; + cd-gpios =3D <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vcc_sdhi>; + status =3D "okay"; +}; + +/* Page 26 / 2230 Key M M.2 */ +&pcie0_clkref { + clock-frequency =3D <100000000>; +}; + +&pciec0 { + reset-gpios =3D <&gpio2 2 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +/* Page 25 / PCIe to USB */ +&pcie1_clkref { + clock-frequency =3D <100000000>; +}; + +&pciec1 { + /* uPD720201 is PCIe Gen2 x1 device */ + num-lanes =3D <1>; + reset-gpios =3D <&gpio2 0 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pfc { + pinctrl-0 =3D <&scif_clk_pins>; + pinctrl-names =3D "default"; + + /* Page 22 / Ether_AVB0 */ + avb0_pins: avb0 { + mux { + groups =3D "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function =3D "avb0"; + }; + + pins-mdio { + groups =3D "avb0_mdio"; + drive-strength =3D <21>; + }; + + pins-mii { + groups =3D "avb0_rgmii"; + drive-strength =3D <21>; + }; + + }; + + /* Page 28 / CANFD_IF */ + can_clk_pins: can-clk { + groups =3D "can_clk"; + function =3D "can_clk"; + }; + + /* Page 28 / CANFD_IF */ + canfd3_pins: canfd3 { + groups =3D "canfd3_data"; + function =3D "canfd3"; + }; + + /* Page 28 / CANFD_IF */ + canfd4_pins: canfd4 { + groups =3D "canfd4_data"; + function =3D "canfd4"; + }; + + /* Page 23 / DEBUG */ + hscif0_pins: hscif0 { + groups =3D "hscif0_data", "hscif0_ctrl"; + function =3D "hscif0"; + }; + + /* Page 23 / DEBUG */ + hscif1_pins: hscif1 { + groups =3D "hscif1_data_a", "hscif1_ctrl_a"; + function =3D "hscif1"; + }; + + /* Page 24 / UART */ + hscif3_pins: hscif3 { + groups =3D "hscif3_data_a"; + function =3D "hscif3"; + }; + + /* Page 24 / I2C SWITCH */ + i2c0_pins: i2c0 { + groups =3D "i2c0"; + function =3D "i2c0"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN0 */ + i2c1_pins: i2c1 { + groups =3D "i2c1"; + function =3D "i2c1"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN1 */ + i2c2_pins: i2c2 { + groups =3D "i2c2"; + function =3D "i2c2"; + }; + + /* Page 31 / IO_CN */ + i2c3_pins: i2c3 { + groups =3D "i2c3"; + function =3D "i2c3"; + }; + + /* Page 31 / IO_CN */ + i2c4_pins: i2c4 { + groups =3D "i2c4"; + function =3D "i2c4"; + }; + + /* Page 18 / POWER_CORE */ + i2c5_pins: i2c5 { + groups =3D "i2c5"; + function =3D "i2c5"; + }; + + /* Page 27 / DSI to Display */ + irq0_pins: irq0 { + groups =3D "intc_ex_irq0_a"; + function =3D "intc_ex"; + }; + + /* Page 31 / FAN */ + irq4_pins: irq4 { + groups =3D "intc_ex_irq4_b"; + function =3D "intc_ex"; + }; + + /* Page 31 / FAN */ + pwm0_pins: pwm0 { + groups =3D "pwm0"; + function =3D "pwm0"; + }; + + /* Page 31 / CN7 pin 12 */ + pwm1_pins: pwm1 { + groups =3D "pwm1_b"; + function =3D "pwm1"; + }; + + /* Page 31 / CN7 pin 32 */ + pwm6_pins: pwm6 { + groups =3D "pwm6"; + function =3D "pwm6"; + }; + + /* Page 31 / CN7 pin 33 */ + pwm7_pins: pwm7 { + groups =3D "pwm7"; + function =3D "pwm7"; + }; + + /* Page 16 / QSPI_FLASH */ + qspi0_pins: qspi0 { + groups =3D "qspi0_ctrl", "qspi0_data4"; + function =3D "qspi0"; + bootph-all; + }; + + /* Page 6 / SCIF_CLK_SOC_V */ + scif_clk_pins: scif-clk { + groups =3D "scif_clk"; + function =3D "scif_clk"; + }; + + /* Page 17 uSD-Slot */ + sd_pins: sd { + groups =3D "mmc_data4", "mmc_ctrl"; + function =3D "mmc"; + power-source =3D <3300>; + }; + + /* Page 17 uSD-Slot */ + sd_uhs_pins: sd-uhs { + groups =3D "mmc_data4", "mmc_ctrl"; + function =3D "mmc"; + power-source =3D <1800>; + }; +}; + +/* Page 31 / FAN */ +&pwm0 { + pinctrl-0 =3D <&pwm0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Page 31 / CN7 pin 12 */ +&pwm1 { + pinctrl-0 =3D <&pwm1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Page 31 / CN7 pin 32 */ +&pwm6 { + pinctrl-0 =3D <&pwm6_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Page 31 / CN7 pin 33 */ +&pwm7 { + pinctrl-0 =3D <&pwm7_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Page 16 / QSPI_FLASH */ +&rpc { + pinctrl-0 =3D <&qspi0_pins>; + pinctrl-names =3D "default"; + bootph-all; + + status =3D "okay"; + + flash@0 { + compatible =3D "spansion,s25fs512s", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + bootph-all; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + boot@0 { + reg =3D <0x0 0x1000000>; + read-only; + }; + + user@1000000 { + reg =3D <0x1000000 0x2f80000>; + }; + + env1@3f80000 { + reg =3D <0x3f80000 0x40000>; + }; + + env2@3fc0000 { + reg =3D <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec =3D <60>; + status =3D "okay"; +}; + +/* Page 6 / SCIF_CLK_SOC_V */ +&scif_clk { /* X12 */ + clock-frequency =3D <24000000>; +}; --=20 2.47.2