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Sun, 20 Apr 2025 00:04:39 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v2 1/6] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support Date: Sun, 20 Apr 2025 15:02:46 +0800 Message-ID: <20250420070251.378950-2-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250420070251.378950-1-guodong@riscstar.com> References: <20250420070251.378950-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC reuses the Marvell PXA910-compatible PWM controller with one notable difference: the addition of a resets property. To make the device tree pass schema validation (make dtbs_check W=3D3), this patch updates the binding to accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm. Support for the optional resets property is also added, as it is required by the K1 integration but was not present in the original Marvell bindings. Since the PWM reset line may be deasserted during the early bootloader stage, making the resets property optional avoids potential double-deassertion, which could otherwise cause flickering on displays that use PWM for backlight control. Signed-off-by: Guodong Xu Reviewed-by: Rob Herring (Arm) --- v2: Accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm .../bindings/pwm/marvell,pxa-pwm.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/D= ocumentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 9ee1946dc2e1..0d97333c7fee 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -14,11 +14,15 @@ allOf: =20 properties: compatible: - enum: - - marvell,pxa250-pwm - - marvell,pxa270-pwm - - marvell,pxa168-pwm - - marvell,pxa910-pwm + oneOf: + - enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: + - const: spacemit,k1-pwm + - const: marvell,pxa910-pwm =20 reg: # Length should be 0x10 @@ -31,6 +35,9 @@ properties: clocks: maxItems: 1 =20 + resets: + maxItems: 1 + required: - compatible - reg --=20 2.43.0 From nobody Sun Feb 8 19:56:59 2026 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9388635947 for ; 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Sun, 20 Apr 2025 00:05:01 -0700 (PDT) Received: from localhost.localdomain ([2a11:3:200::40b3]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b0db12743afsm3742626a12.16.2025.04.20.00.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Apr 2025 00:05:01 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v2 2/6] pwm: pxa: add optional reset control Date: Sun, 20 Apr 2025 15:02:47 +0800 Message-ID: <20250420070251.378950-3-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250420070251.378950-1-guodong@riscstar.com> References: <20250420070251.378950-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support optional reset control for the PWM PXA driver. During the probe, it acquires the reset controller using devm_reset_control_get_optional_exclusive_deasserted() to get and deassert the reset controller to enable the PWM channel. Signed-off-by: Guodong Xu --- v2: No change drivers/pwm/pwm-pxa.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 430bd6a709e9..dd9c6af0f672 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #include =20 @@ -49,10 +50,10 @@ MODULE_DEVICE_TABLE(platform, pwm_id_table); #define PWMDCR_FD (1 << 10) =20 struct pxa_pwm_chip { - struct device *dev; - - struct clk *clk; - void __iomem *mmio_base; + struct device *dev; + struct clk *clk; + void __iomem *mmio_base; + struct reset_control *reset; }; =20 static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip) @@ -179,6 +180,11 @@ static int pwm_probe(struct platform_device *pdev) if (IS_ERR(pc->clk)) return PTR_ERR(pc->clk); =20 + pc->reset =3D devm_reset_control_get_optional_exclusive_deasserted( + &pdev->dev, NULL); + if (IS_ERR(pc->reset)) + return PTR_ERR(pc->reset); + chip->ops =3D &pxa_pwm_ops; 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Sun, 20 Apr 2025 00:05:19 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v2 3/6] riscv: dts: spacemit: add PWM support for K1 SoC Date: Sun, 20 Apr 2025 15:02:48 +0800 Message-ID: <20250420070251.378950-4-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250420070251.378950-1-guodong@riscstar.com> References: <20250420070251.378950-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC features a PWM controller with 20 independent channels. Add the corresponding 20 PWM nodes to the device tree. Signed-off-by: Guodong Xu --- v2: Changed compatible string with the fallback marvell,pxa910-pwm arch/riscv/boot/dts/spacemit/k1.dtsi | 180 +++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index c0cc4b99c935..e7dba623e877 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -556,5 +556,185 @@ sec_uart1: serial@f0612000 { reg-io-width =3D <4>; status =3D "reserved"; /* for TEE usage */ }; + + pwm0: pwm@d401a000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a000 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM0>; + resets =3D <&syscon_apbc RESET_PWM0>; + status =3D "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a400 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM1>; + resets =3D <&syscon_apbc RESET_PWM1>; + status =3D "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a800 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM2>; + resets =3D <&syscon_apbc RESET_PWM2>; + status =3D "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401ac00 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM3>; + resets =3D <&syscon_apbc RESET_PWM3>; + status =3D "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b000 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM4>; + resets =3D <&syscon_apbc RESET_PWM4>; + status =3D "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b400 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM5>; + resets =3D <&syscon_apbc RESET_PWM5>; + status =3D "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b800 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM6>; + resets =3D <&syscon_apbc RESET_PWM6>; + status =3D "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401bc00 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM7>; + resets =3D <&syscon_apbc RESET_PWM7>; + status =3D "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020000 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM8>; + resets =3D <&syscon_apbc RESET_PWM8>; + status =3D "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020400 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM9>; + resets =3D <&syscon_apbc RESET_PWM9>; + status =3D "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020800 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM10>; + resets =3D <&syscon_apbc RESET_PWM10>; + status =3D "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020c00 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM11>; + resets =3D <&syscon_apbc RESET_PWM11>; + status =3D "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021000 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM12>; + resets =3D <&syscon_apbc RESET_PWM12>; + status =3D "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021400 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM13>; + resets =3D <&syscon_apbc RESET_PWM13>; + status =3D "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021800 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM14>; + resets =3D <&syscon_apbc RESET_PWM14>; + status =3D "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021c00 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM15>; + resets =3D <&syscon_apbc RESET_PWM15>; + status =3D "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022000 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM16>; + resets =3D <&syscon_apbc RESET_PWM16>; + status =3D "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022400 0x0 0x10>; + #pwm-cells =3D <1>; + clocks =3D <&syscon_apbc CLK_PWM17>; + resets =3D <&syscon_apbc RESET_PWM17>; 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charset="utf-8" This patch adds the option 1 (hence the name pwm14_1) pinctrl configuration for PWM14 on the SpacemiT K1 SoC. PWM14 option 1 is used for PWM-based backlight control on MIPI displays. This configuration is present on all existing K1 development boards, such as the Banana Pi BPI-F3 and the Milk-V Jupiter. For reference, a more complete list of PWM0-PWM19 pinctrl configurations including all options can be found in [1]. Note: Since the corresponding functionality for other pins is not yet in use or ready for upstreaming, this patch includes only the pwm14_1 setting. [1] https://lore.kernel.org/all/20250411131423.3802611-7-guodong@riscstar.c= om/ Signed-off-by: Guodong Xu --- v2: Discard pwm0-pwm19 pinctrl configurations, and adds only pwm14_1_cfg arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index 283663647a86..195eb8874f3c 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -20,4 +20,11 @@ uart0-2-pins { drive-strength =3D <32>; }; }; + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux =3D ; + bias-pull-up =3D <0>; + drive-strength =3D <32>; + }; + }; }; --=20 2.43.0 From nobody Sun Feb 8 19:57:00 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78D6C1D63C7 for ; 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Sun, 20 Apr 2025 00:05:54 -0700 (PDT) Received: from localhost.localdomain ([2a11:3:200::40b3]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b0db12743afsm3742626a12.16.2025.04.20.00.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Apr 2025 00:05:54 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v2 5/6] pwm: Kconfig: add depends on ARCH_SPACEMIT to PWM_PXA Date: Sun, 20 Apr 2025 15:02:50 +0800 Message-ID: <20250420070251.378950-6-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250420070251.378950-1-guodong@riscstar.com> References: <20250420070251.378950-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC uses PWM_PXA driver. Update the Kconfig file for the PWM_PXA driver to allow the SpacemiT K1 SoC to use it. Signed-off-by: Guodong Xu --- v2: No change drivers/pwm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4731d5b90d7e..6731669e724e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -493,7 +493,7 @@ config PWM_PCA9685 =20 config PWM_PXA tristate "PXA PWM support" - depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST + depends on ARCH_PXA || ARCH_MMP || ARCH_SPACEMIT || COMPILE_TEST depends on HAS_IOMEM help Generic PWM framework driver for PXA. --=20 2.43.0 From nobody Sun Feb 8 19:57:00 2026 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 084401DF256 for ; Sun, 20 Apr 2025 07:06:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Sun, 20 Apr 2025 00:06:11 -0700 (PDT) Received: from localhost.localdomain ([2a11:3:200::40b3]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b0db12743afsm3742626a12.16.2025.04.20.00.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Apr 2025 00:06:10 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v2 6/6] riscv: defconfig: Enable PWM support for SpacemiT K1 SoC Date: Sun, 20 Apr 2025 15:02:51 +0800 Message-ID: <20250420070251.378950-7-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250420070251.378950-1-guodong@riscstar.com> References: <20250420070251.378950-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CONFIG_PWM and CONFIG_PWM_PXA in the defconfig to support the PWM controller used on the SpacemiT K1 SoC. Signed-off-by: Guodong Xu --- v2: Changed PWM_PXA from built-in to a loadable module (=3Dm) arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 4888529df1d8..8a8b77a0ac5a 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -259,6 +259,8 @@ CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy CONFIG_PM_DEVFREQ=3Dy CONFIG_IIO=3Dy +CONFIG_PWM=3Dy +CONFIG_PWM_PXA=3Dm CONFIG_THEAD_C900_ACLINT_SSWI=3Dy CONFIG_PHY_SUN4I_USB=3Dm CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=3Dm --=20 2.43.0