From nobody Tue Feb 10 08:30:00 2026 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17AF9199947 for ; Sun, 20 Apr 2025 19:00:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745175653; cv=none; b=hkjRaX6hbIGjJf6SVm7pqpcV43Xlz48dfK91U5ZsSVNIhXc6/7S/3vHagNbZT45vsWRB7XPispoABhJRiv/SaGRhN49wKoZ2rzdfAAFdY5MH5tHfLDx7ukuK0jsSY6LhWpLoCDjgK45vokbp1WVcxWBRgPQOHpy8UCNnxNzHV/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745175653; c=relaxed/simple; bh=ZzqEnrc2GwGD0LJJxzv/EFLw7i0OZpVSmt6FN5Jh0zE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n0vmShu623KPR1peS+8hIHVehCkKImLiSoK21og/hbGgjhj1yFkiytKFV0UE1CMP/YgY75ku1Afh65NGoy7XrEqOpFVPzsI3zWqjnqBW8ApY04mA46JbCwSVPRUj6nNu6rrpyHmxTcqRf+1WXncpnUTBUJgxkR2CQqlqwTO0TPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=LIR/K4Rk; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="LIR/K4Rk" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=LIR/K4RkD+zKs/VeUcFutsQxHIxd0wjdIHb6Q7CDJQi4rfE1g9MsoYS85D9m+ngOxrDStx7rhS1eA+cO84LDB0ohGNHqmKp62+uKHB8cJimZjbvUcm8EzYtIYyi5l94++GC2VOGz8YVSanleIaknZbiebGJ1Ad++g9kxmPEz+PN0eWPdy2c2D+UuDZv5un5ezLDigKIfpaUN3ZLFztawpmMZiJndXnnDFZ23GI7+zP72BR9PYg6HLNxwSRi7XC7c6ZkmUREzyIbFR3zn2kIvTICpiuy1BZBNrtth08allgcgBd96d3MNoi11rmMjlSOK0U6ka0KMPkPBisZpDXdbxA==; s=purelymail3; d=purelymail.com; v=1; bh=ZzqEnrc2GwGD0LJJxzv/EFLw7i0OZpVSmt6FN5Jh0zE=; h=Feedback-ID:Received:From:Date:Subject:To; Feedback-ID: 68247:10037:null:purelymail X-Pm-Original-To: linux-kernel@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id 1640089901; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Sun, 20 Apr 2025 19:00:43 +0000 (UTC) From: Igor Belwon Date: Sun, 20 Apr 2025 21:00:38 +0200 Subject: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos990-wdt compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250420-wdt-resends-april-v1-1-f58639673959@mentallysanemainliners.org> References: <20250420-wdt-resends-april-v1-0-f58639673959@mentallysanemainliners.org> In-Reply-To: <20250420-wdt-resends-april-v1-0-f58639673959@mentallysanemainliners.org> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745175638; l=2884; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=ZzqEnrc2GwGD0LJJxzv/EFLw7i0OZpVSmt6FN5Jh0zE=; b=l3whzqZEDIVwIoZNOtSEIAdPsHfbI3xwrAn2qclEOxST3fnd30CM+CTztr4C+eQvzowAGgHQD 3hFXaF1Y2PJCHH7G8jU5ZoQ5EZ1wNnwDKnfgF+kItJ/pr18r5FzdIBt X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= Add a dt-binding compatible for the Exynos990 Watchdog timer. This watchdog is compatible with the GS101/Exynos850 design, as such it requires the cluster-index and syscon-phandle properties to be present. It also contains a cl2 cluster, as such the cluster-index property has been expanded. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Igor Belwon Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 11 +++++++--= -- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/= Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index d175ae9683366d33b1f9d9d820501d1e7c5964bd..53fc64f5b56d33f910395d32b35= e0905b8b9aa53 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 + - samsung,exynos990-wdt # for Exynos990 - samsung,exynosautov9-wdt # for Exynosautov9 - samsung,exynosautov920-wdt # for Exynosautov920 - items: @@ -49,14 +50,14 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos= 850 - or Google gs101). + Index of CPU cluster on which watchdog is running (in case of Exynos= 850, + Exynos990 or Google gs101). =20 samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7, Exynos850 and gs101). + Exynos5420, Exynos7, Exynos850, Exynos990 and gs101). =20 required: - compatible @@ -77,6 +78,7 @@ allOf: - samsung,exynos5420-wdt - samsung,exynos7-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -89,6 +91,7 @@ allOf: enum: - google,gs101-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -102,7 +105,7 @@ allOf: - const: watchdog - const: watchdog_src samsung,cluster-index: - enum: [0, 1] + enum: [0, 1, 2] required: - samsung,cluster-index else: --=20 2.47.2 From nobody Tue Feb 10 08:30:00 2026 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3738321128D for ; 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(version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Sun, 20 Apr 2025 19:00:45 +0000 (UTC) From: Igor Belwon Date: Sun, 20 Apr 2025 21:00:39 +0200 Subject: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos990-wdt compatible data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250420-wdt-resends-april-v1-2-f58639673959@mentallysanemainliners.org> References: <20250420-wdt-resends-april-v1-0-f58639673959@mentallysanemainliners.org> In-Reply-To: <20250420-wdt-resends-april-v1-0-f58639673959@mentallysanemainliners.org> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745175638; l=3556; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=Fxg61Yte1UPz7xtMEapmFGrdMeVN/z75TtaNETL9lu4=; b=JS2lGNZDyaaVkljswDbu0dXHW1KjOUlEXMzWb1hi1S0JfSb0OvEezHI/eSl5ZSjQDddueAUxa mC7O1cSh3l1D1Da+z7cGPy79Iul+5yUJOh1EurlCLDM9Vu0H/B8bbrF X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= The Exynos990 has two watchdog clusters - cl0 and cl2. Add new driver data for these two clusters, making it possible to use the watchdog timer on this SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Igor Belwon Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index bdd81d8074b2496d68c2b0f086f477dc8652e452..40901bdac42613458f93c096543= 53190785ff072 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -82,6 +82,10 @@ #define GS_CLUSTER2_NONCPU_INT_EN 0x1644 #define GS_RST_STAT_REG_OFFSET 0x3B44 =20 +#define EXYNOS990_CLUSTER2_NONCPU_OUT 0x1620 +#define EXYNOS990_CLUSTER2_NONCPU_INT_EN 0x1644 +#define EXYNOS990_CLUSTER2_WDTRESET_BIT 23 + /** * DOC: Quirk flags for different Samsung watchdog IP-cores * @@ -259,6 +263,32 @@ static const struct s3c2410_wdt_variant drv_data_exyno= s850_cl1 =3D { QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, }; =20 +static const struct s3c2410_wdt_variant drv_data_exynos990_cl0 =3D { + .mask_reset_reg =3D GS_CLUSTER0_NONCPU_INT_EN, + .mask_bit =3D 2, + .mask_reset_inv =3D true, + .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit =3D EXYNOS850_CLUSTER0_WDTRESET_BIT, + .cnt_en_reg =3D EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT, + .cnt_en_bit =3D 7, + .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT, +}; + +static const struct s3c2410_wdt_variant drv_data_exynos990_cl2 =3D { + .mask_reset_reg =3D EXYNOS990_CLUSTER2_NONCPU_INT_EN, + .mask_bit =3D 2, + .mask_reset_inv =3D true, + .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit =3D EXYNOS990_CLUSTER2_WDTRESET_BIT, + .cnt_en_reg =3D EXYNOS990_CLUSTER2_NONCPU_OUT, + .cnt_en_bit =3D 7, + .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT, +}; + static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 =3D { .mask_reset_reg =3D EXYNOS850_CLUSTER0_NONCPU_INT_EN, .mask_bit =3D 2, @@ -350,6 +380,8 @@ static const struct of_device_id s3c2410_wdt_match[] = =3D { .data =3D &drv_data_exynos7 }, { .compatible =3D "samsung,exynos850-wdt", .data =3D &drv_data_exynos850_cl0 }, + { .compatible =3D "samsung,exynos990-wdt", + .data =3D &drv_data_exynos990_cl0 }, { .compatible =3D "samsung,exynosautov9-wdt", .data =3D &drv_data_exynosautov9_cl0 }, { .compatible =3D "samsung,exynosautov920-wdt", @@ -678,7 +710,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, = struct s3c2410_wdt *wdt) if (variant =3D=3D &drv_data_exynos850_cl0 || variant =3D=3D &drv_data_exynosautov9_cl0 || variant =3D=3D &drv_data_gs101_cl0 || - variant =3D=3D &drv_data_exynosautov920_cl0) { + variant =3D=3D &drv_data_exynosautov920_cl0 || + variant =3D=3D &drv_data_exynos990_cl0) { u32 index; int err; =20 @@ -700,6 +733,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev,= struct s3c2410_wdt *wdt) else if (variant =3D=3D &drv_data_exynosautov920_cl0) variant =3D &drv_data_exynosautov920_cl1; break; + case 2: + if (variant =3D=3D &drv_data_exynos990_cl0) + variant =3D &drv_data_exynos990_cl2; + break; default: return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); } --=20 2.47.2