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Sat, 19 Apr 2025 15:36:34 -0700 (PDT) From: Linus Walleij Date: Sun, 20 Apr 2025 00:36:17 +0200 Subject: [PATCH v6 30/31] ARM: entry: Block IRQs in early IRQ context Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250420-arm-generic-entry-v6-30-95f1fcdfeeb2@linaro.org> References: <20250420-arm-generic-entry-v6-0-95f1fcdfeeb2@linaro.org> In-Reply-To: <20250420-arm-generic-entry-v6-0-95f1fcdfeeb2@linaro.org> To: Dmitry Vyukov , Oleg Nesterov , Russell King , Kees Cook , Andy Lutomirski , Will Drewry , Frederic Weisbecker , "Paul E. McKenney" , Jinjie Ruan , Arnd Bergmann , Ard Biesheuvel , Al Viro Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij , Thomas Gleixner X-Mailer: b4 0.14.2 When dabt, pabt or und exceptions occur on ARM, ordinary interrupts (IRQs) can still happen. This isn't nice for the kernels context tracker, which expect (when using generic entry at least) that any nested IRQs happens between irqentry_enter() and irqentry_exit(), else it thinks something is fishy. This change blocks interrupts in the pabt, dabt, und and abt exception paths (all of them really) by unconditionally setting PSR_I_BIT in the early exception handler, until after context has been established with irqentry_enter() and before it is exited with irqentry_exit(). Inside the context-tracked exception handler we enable IRQs again, and once we leave it we disable them while exiting the exception. The local_irq_disable() in bad_mode() can be dropped since we are now disabling IRQs in the early assembly exception handler for all exceptions. This seems like not perfect: it seems an interrupt could still occur right before CPSR is set, or right after the userspace registers are restored in ret_from_exception. I would like to know if there is some way to set up these exceptions to inherently block IRQs when handled, until we explicitly allow them between irqentry_enter() and irqentry_exit() or if this is simply the best we can do on ARM for these exceptions to make the context tracker happy. Acked-by: Thomas Gleixner Acked-by: Paul E. McKenney Signed-off-by: Linus Walleij --- arch/arm/kernel/entry-armv.S | 6 +----- arch/arm/kernel/entry.c | 18 ++++++++++++++++++ arch/arm/kernel/traps.c | 1 - 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index ae2f952beea7611f0abc7bd299fc944335a21219..3dae35b0bb3f440ecaf157a4568= 7bf4690fb8f88 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -416,11 +416,6 @@ ENDPROC(__irq_usr) __und_usr: usr_entry uaccess=3D0 =20 - @ IRQs must be enabled before attempting to read the instruction from - @ user space since that could cause a page/translation fault if the - @ page table was modified by another CPU. - enable_irq - tst r5, #PSR_T_BIT @ Thumb mode? mov r1, #2 @ set insn size to 2 for Thumb bne 0f @ handle as Thumb undef exception @@ -847,6 +842,7 @@ vector_\name: @ mrs r0, cpsr eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) + orr r0, r0, #PSR_I_BIT msr spsr_cxsf, r0 =20 @ diff --git a/arch/arm/kernel/entry.c b/arch/arm/kernel/entry.c index 01e4339ccdb4951e04a89fb91ad7c6e1991e09af..3881670e0987ee40be6fff32f41= 2edcf4f3ec80a 100644 --- a/arch/arm/kernel/entry.c +++ b/arch/arm/kernel/entry.c @@ -17,8 +17,18 @@ noinstr asmlinkage void arm_und_handler(struct pt_regs *= regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 + /* + * IRQs must be enabled before attempting to read the instruction from + * user space since that could cause a page/translation fault if the + * page table was modified by another CPU. + */ + + local_irq_enable(); + do_undefinstr(regs); =20 + local_irq_disable(); + irqentry_exit(regs, state); } =20 @@ -27,8 +37,12 @@ noinstr asmlinkage void arm_dabt_handler(unsigned long a= ddr, unsigned int fsr, { irqentry_state_t state =3D irqentry_enter(regs); =20 + local_irq_enable(); + do_DataAbort(addr, fsr, regs); =20 + local_irq_disable(); + irqentry_exit(regs, state); } =20 @@ -37,8 +51,12 @@ noinstr asmlinkage void arm_pabt_handler(unsigned long a= ddr, unsigned int ifsr, { irqentry_state_t state =3D irqentry_enter(regs); =20 + local_irq_enable(); + do_PrefetchAbort(addr, ifsr, regs); =20 + local_irq_disable(); + irqentry_exit(regs, state); } =20 diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 934708b9eb6f4d615000c0d667d1c7cfcd0d2820..7d557339490e3e6056ad772690f= 340f127f51c51 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -508,7 +508,6 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reas= on) pr_crit("Bad mode in %s handler detected\n", handler[reason]); =20 die("Oops - bad mode", regs, 0); - local_irq_disable(); panic("bad mode"); } =20 --=20 2.49.0