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Sat, 19 Apr 2025 15:36:17 -0700 (PDT) From: Linus Walleij Date: Sun, 20 Apr 2025 00:36:03 +0200 Subject: [PATCH v6 16/31] ARM: entry: Drop argument to asm_irqentry macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250420-arm-generic-entry-v6-16-95f1fcdfeeb2@linaro.org> References: <20250420-arm-generic-entry-v6-0-95f1fcdfeeb2@linaro.org> In-Reply-To: <20250420-arm-generic-entry-v6-0-95f1fcdfeeb2@linaro.org> To: Dmitry Vyukov , Oleg Nesterov , Russell King , Kees Cook , Andy Lutomirski , Will Drewry , Frederic Weisbecker , "Paul E. McKenney" , Jinjie Ruan , Arnd Bergmann , Ard Biesheuvel , Al Viro Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij , Thomas Gleixner X-Mailer: b4 0.14.2 asm_irqentry_enter_from_user_mode and asm_irqentry_exit_to_user_mode have a "save" argument that will save and restore registers before the call to the C function. Now all invocations set this argument to 0 so drop the surplus code. Acked-by: Thomas Gleixner Acked-by: Paul E. McKenney Signed-off-by: Linus Walleij --- arch/arm/kernel/entry-armv.S | 8 ++++---- arch/arm/kernel/entry-common.S | 2 +- arch/arm/kernel/entry-header.S | 18 ++---------------- 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 6edf362ab1e1035dafebf6fb7c55db71462c1eae..460aa92c3c1f50de905550acf36= 3c58f509bfe0a 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -422,7 +422,7 @@ ENDPROC(__fiq_abt) .align 5 __dabt_usr: usr_entry uaccess=3D0 - asm_irqentry_enter_from_user_mode save =3D 0 + asm_irqentry_enter_from_user_mode kuser_cmpxchg_check mov r2, sp dabt_helper @@ -433,7 +433,7 @@ ENDPROC(__dabt_usr) .align 5 __irq_usr: usr_entry - asm_irqentry_enter_from_user_mode save =3D 0 + asm_irqentry_enter_from_user_mode kuser_cmpxchg_check irq_handler from_user=3D1 get_thread_info tsk @@ -447,7 +447,7 @@ ENDPROC(__irq_usr) .align 5 __und_usr: usr_entry uaccess=3D0 - asm_irqentry_enter_from_user_mode save =3D 0 + asm_irqentry_enter_from_user_mode =20 @ IRQs must be enabled before attempting to read the instruction from @ user space since that could cause a page/translation fault if the @@ -472,7 +472,7 @@ ENDPROC(__und_usr) .align 5 __pabt_usr: usr_entry - asm_irqentry_enter_from_user_mode save =3D 0 + asm_irqentry_enter_from_user_mode mov r2, sp @ regs pabt_helper UNWIND(.fnend ) diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 14b2495cae3c2f95b0dfecd849b4e16ec143dbe9..df564388905ee019cd5553f8b37= e678da59e3222 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -109,7 +109,7 @@ ENTRY(ret_to_user_from_irq) movs r1, r1, lsl #16 bne slow_work_pending no_work_pending: - asm_irqentry_exit_to_user_mode save =3D 0 + asm_irqentry_exit_to_user_mode =20 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK bl stackleak_erase_on_task_stack diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index fb5bb019199b2871e29e306a29bea8fdf47dd7f3..50c0b55adc7421e7be123c9d00f= 94b1ebb93ff9e 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -365,28 +365,14 @@ ALT_UP_B(.L1_\@) * Context tracking and other mode transitions. Used to instrument transit= ions * between user and kernel mode. */ - .macro asm_irqentry_enter_from_user_mode, save =3D 1 - .if \save - stmdb sp!, {r0-r3, ip, lr} + .macro asm_irqentry_enter_from_user_mode mov r0, sp @ regs bl irqentry_enter_from_user_mode - ldmia sp!, {r0-r3, ip, lr} - .else - mov r0, sp @ regs - bl irqentry_enter_from_user_mode - .endif .endm =20 - .macro asm_irqentry_exit_to_user_mode, save =3D 1 - .if \save - stmdb sp!, {r0-r3, ip, lr} + .macro asm_irqentry_exit_to_user_mode mov r0, sp @ regs bl irqentry_exit_to_user_mode - ldmia sp!, {r0-r3, ip, lr} - .else - mov r0, sp @ regs - bl irqentry_exit_to_user_mode - .endif .endm =20 /* --=20 2.49.0