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Fri, 18 Apr 2025 22:19:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHRbu7EqDkT1Nj/uU8mVqGS+zdhQm81Ykk2C//aenToa25p2Tc/dc5T7ALGhEC7c4FKDOyS6w== X-Received: by 2002:a05:6a20:c90e:b0:1f5:9098:e446 with SMTP id adf61e73a8af0-203cbc0573emr8333308637.2.1745039988817; Fri, 18 Apr 2025 22:19:48 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbfaac258sm2607932b3a.144.2025.04.18.22.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 22:19:48 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 19 Apr 2025 10:49:26 +0530 Subject: [PATCH v3 3/3] arm64: qcom: sc7280: Move phy, perst to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250419-perst-v3-3-1afec3c4ea62@oss.qualcomm.com> References: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> In-Reply-To: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745039969; l=3429; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=3DnAtxNAZDqNQqcmKUvx3DsvQPY0Kl35D9B1JCC1B6M=; b=DkSLSP7iTAUMhyijELwXlNgBv5oqQeFeYWwepFB2dZoS6R8mMcJt/WlFR72Rni98O5mLUSOEt I91VDY8Pa5yA8+u/2AHDaN1UzlvOeEfsYAXRomY41Exvys59O681HAi X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: sCSV2rBh2aG0Hw3kNKXyUtlx-6Sj5Zqy X-Authority-Analysis: v=2.4 cv=CYgI5Krl c=1 sm=1 tr=0 ts=68033276 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=qQkGquXN9PvF_GGjQ98A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: sCSV2rBh2aG0Hw3kNKXyUtlx-6Sj5Zqy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-19_01,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504190040 There are many places we agreed to move the wake and perst gpio's and phy etc to the pcie root port node instead of bridge node[1]. So move the phy, phy-names, wake-gpio's in the root port. There is already reset-gpio defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++---- 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index 7a36c90ad4ec8b52f30b22b1621404857d6ef336..3dd58986ad5da0f898537a51715= bb5d0fecbe100 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -709,8 +709,11 @@ &mdss_edp_phy { status =3D "okay"; }; =20 +&pcie1_port0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1 { - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; =20 pinctrl-0 =3D <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index 2ba4ea60cb14736c9cfbf9f4a9048f20a4c921f2..ff11d85d015bdab6a90bd8a0eb9= 113a339866953 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,10 +472,13 @@ &pcie1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; =20 - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply =3D <&pp3300_ssd>; }; =20 +&pcie1_port0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pm8350c_pwm { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 7370aa0dbf0e3f9e7a3e38c3f00686e1d3dcbc9f..3209bb15dfec36299cabae07d34= f3dc82db6de77 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -414,9 +414,12 @@ &lpass_va_macro { vdd-micb-supply =3D <&vreg_bob>; }; =20 +&pcie1_port0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1 { status =3D "okay"; - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; =20 vddpe-3v3-supply =3D <&nvme_3v3_regulator>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0f2caf36910b65c398c9e03800a8ce0a8a1f8fc7..376fabf3b4eac34d75bb79ef902= c9d83490c45f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 { =20 power-domains =3D <&gcc GCC_PCIE_1_GDSC>; =20 - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie1_clkreq_n>; =20 @@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 { =20 status =3D "disabled"; =20 - pcie@0 { + pcie1_port0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; @@ -2292,6 +2289,7 @@ pcie@0 { #address-cells =3D <3>; #size-cells =3D <2>; ranges; + phys =3D <&pcie1_phy>; }; }; =20 --=20 2.34.1