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Fri, 18 Apr 2025 22:19:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFPh2UeIFjUcCzHCt69mzwi3ZCMKTL2uPeLdpaaSj3UslSxHPnSkJhYpDWJ3gVtSp9W80kOGA== X-Received: by 2002:a05:6a00:4acc:b0:736:b9f5:47c6 with SMTP id d2e1a72fcca58-73dc1566938mr6532756b3a.16.1745039984023; Fri, 18 Apr 2025 22:19:44 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbfaac258sm2607932b3a.144.2025.04.18.22.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 22:19:43 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 19 Apr 2025 10:49:25 +0530 Subject: [PATCH v3 2/3] PCI: qcom: Add support for multi-root port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250419-perst-v3-2-1afec3c4ea62@oss.qualcomm.com> References: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> In-Reply-To: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Currently, qcom controllers only support single port, and all properties are present in the controller node itself. This is incorrect, as properties like phy, perst, wake, etc. can vary per port and should be present in the root port node. To maintain DT backwards compatibility, fallback to the legacy method of parsing the controller node if the port parsing fails. pci-bus-common.yaml uses reset-gpios property for representing PERST, use same property instead of perst-gpios. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 169 +++++++++++++++++++++++++++--= ---- 1 file changed, 142 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index dc98ae63362db0422384b1879a2b9a7dc564d091..e97e5076f5f77acbbdfb982af7a= cc69daf9bf307 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -262,6 +262,11 @@ struct qcom_pcie_cfg { bool no_l0s; }; =20 +struct qcom_pcie_port { + struct list_head list; + struct gpio_desc *reset; + struct phy *phy; +}; struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ @@ -276,22 +281,35 @@ struct qcom_pcie { struct dentry *debugfs; bool suspended; bool use_pm_opp; + struct list_head ports; }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) =20 -static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +static void qcom_perst_assert_deassert(struct qcom_pcie *pcie, bool assert) { - gpiod_set_value_cansleep(pcie->reset, 1); + struct qcom_pcie_port *port, *tmp; + int val =3D assert ? 1 : 0; + + if (list_empty(&pcie->ports)) + gpiod_set_value_cansleep(pcie->reset, val); + else + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + gpiod_set_value_cansleep(port->reset, val); + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 +static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +{ + qcom_perst_assert_deassert(pcie, true); +} + static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) { /* Ensure that PERST has been asserted for at least 100 ms */ msleep(100); - gpiod_set_value_cansleep(pcie->reset, 0); - usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); + qcom_perst_assert_deassert(pcie, false); } =20 static int qcom_pcie_start_link(struct dw_pcie *pci) @@ -1229,6 +1247,59 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } =20 +static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + + if (list_empty(&pcie->ports)) + phy_exit(pcie->phy); + else + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + phy_exit(port->phy); +} + +static void qcom_pcie_phy_off(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + + if (list_empty(&pcie->ports)) { + phy_power_off(pcie->phy); + } else { + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + phy_power_off(port->phy); + } +} + +static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + int ret =3D 0; + + if (list_empty(&pcie->ports)) { + ret =3D phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + goto out; + + ret =3D phy_power_on(pcie->phy); + if (ret) + goto out; + } else { + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + ret =3D phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + goto out; + + ret =3D phy_power_on(port->phy); + if (ret) { + qcom_pcie_phy_off(pcie); + goto out; + } + } + } +out: + return ret; +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1241,11 +1312,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; =20 - ret =3D phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); - if (ret) - goto err_deinit; - - ret =3D phy_power_on(pcie->phy); + ret =3D qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; =20 @@ -1268,7 +1335,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) err_assert_reset: qcom_ep_reset_assert(pcie); err_disable_phy: - phy_power_off(pcie->phy); + qcom_pcie_phy_off(pcie); err_deinit: pcie->cfg->ops->deinit(pcie); =20 @@ -1281,7 +1348,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *= pp) struct qcom_pcie *pcie =3D to_qcom_pcie(pci); =20 qcom_ep_reset_assert(pcie); - phy_power_off(pcie->phy); + qcom_pcie_phy_off(pcie); pcie->cfg->ops->deinit(pcie); } =20 @@ -1579,11 +1646,41 @@ static irqreturn_t qcom_pcie_global_irq_thread(int = irq, void *data) return IRQ_HANDLED; } =20 +static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *node) +{ + struct device *dev =3D pcie->pci->dev; + struct qcom_pcie_port *port; + struct gpio_desc *reset; + struct phy *phy; + + reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), + "reset", GPIOD_OUT_HIGH, "PERST#"); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + phy =3D devm_of_phy_get(dev, node, NULL); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->reset =3D reset; + port->phy =3D phy; + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; unsigned long max_freq =3D ULONG_MAX; + struct qcom_pcie_port *port, *tmp; struct device *dev =3D &pdev->dev; + struct device_node *of_port; struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; @@ -1611,6 +1708,8 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) if (ret < 0) goto err_pm_runtime_put; =20 + INIT_LIST_HEAD(&pcie->ports); + pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; pp =3D &pci->pp; @@ -1619,12 +1718,6 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 pcie->cfg =3D pcie_cfg; =20 - pcie->reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); - if (IS_ERR(pcie->reset)) { - ret =3D PTR_ERR(pcie->reset); - goto err_pm_runtime_put; - } - pcie->parf =3D devm_platform_ioremap_resource_byname(pdev, "parf"); if (IS_ERR(pcie->parf)) { ret =3D PTR_ERR(pcie->parf); @@ -1647,12 +1740,6 @@ static int qcom_pcie_probe(struct platform_device *p= dev) } } =20 - pcie->phy =3D devm_phy_optional_get(dev, "pciephy"); - if (IS_ERR(pcie->phy)) { - ret =3D PTR_ERR(pcie->phy); - goto err_pm_runtime_put; - } - /* OPP table is optional */ ret =3D devm_pm_opp_of_add_table(dev); if (ret && ret !=3D -ENODEV) { @@ -1699,9 +1786,35 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 pp->ops =3D &qcom_pcie_dw_ops; =20 - ret =3D phy_init(pcie->phy); - if (ret) - goto err_pm_runtime_put; + for_each_available_child_of_node(dev->of_node, of_port) { + ret =3D qcom_pcie_parse_port(pcie, of_port); + of_node_put(of_port); + if (ret) + break; + } + + /* + * In the case of failure in parsing the port nodes, fallback to the + * legacy method of parsing the controller node. This is to maintain DT + * backwards compatibility. + */ + if (ret) { + pcie->phy =3D devm_phy_optional_get(dev, "pciephy"); + if (IS_ERR(pcie->phy)) { + ret =3D PTR_ERR(pcie->phy); + goto err_pm_runtime_put; + } + + pcie->reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); + if (IS_ERR(pcie->reset)) { + ret =3D PTR_ERR(pcie->reset); + goto err_pm_runtime_put; + } + + ret =3D phy_init(pcie->phy); + if (ret) + goto err_pm_runtime_put; + } =20 platform_set_drvdata(pdev, pcie); =20 @@ -1746,10 +1859,12 @@ static int qcom_pcie_probe(struct platform_device *= pdev) err_host_deinit: dw_pcie_host_deinit(pp); err_phy_exit: - phy_exit(pcie->phy); + qcom_pcie_phy_exit(pcie); err_pm_runtime_put: pm_runtime_put(dev); pm_runtime_disable(dev); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_del(&port->list); =20 return ret; } --=20 2.34.1