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Fri, 18 Apr 2025 11:47:28 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:27 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Date: Fri, 18 Apr 2025 19:46:58 +0100 Message-ID: <20250418184658.456398-16-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Simplifed V2H DSI timings array to save space - Switched to use fsleep() instead of udelay() v1->v2: - Dropped unused macros - Added missing LPCLK flag to rzvv2h info --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 344 ++++++++++++++++++ .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++ 2 files changed, 378 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 133a8f306d47..a957b6c5f28d 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corporation */ #include +#include #include #include #include @@ -32,6 +33,9 @@ #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) #define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2) =20 +#define RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA (80 * MEGA) +#define RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA (1500 * MEGA) + struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { @@ -42,6 +46,7 @@ struct rzg2l_mipi_dsi_hw_info { u64 *hsfreq_millihz); unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq); + const struct rzv2h_pll_div_limits *cpg_dsi_limits; u32 phy_reg_offset; u32 link_reg_offset; unsigned long max_dclk; @@ -49,6 +54,11 @@ struct rzg2l_mipi_dsi_hw_info { u8 features; }; =20 +struct rzv2h_dsi_mode_calc { + unsigned long mode_freq; + u64 mode_freq_hz; +}; + struct rzg2l_mipi_dsi { struct device *dev; void __iomem *mmio; @@ -70,6 +80,18 @@ struct rzg2l_mipi_dsi { unsigned int num_data_lanes; unsigned int lanes; unsigned long mode_flags; + + struct rzv2h_dsi_mode_calc mode_calc; + struct rzv2h_plldsi_parameters dsi_parameters; +}; + +static const struct rzv2h_pll_div_limits rzv2h_plldsi_div_limits =3D { + .fvco =3D { .min =3D 1050 * MEGA, .max =3D 2100 * MEGA }, + .m =3D { .min =3D 64, .max =3D 1023 }, + .p =3D { .min =3D 1, .max =3D 4 }, + .s =3D { .min =3D 0, .max =3D 5 }, + .k =3D { .min =3D -32768, .max =3D 32767 }, + .csdiv =3D { .min =3D 1, .max =3D 1 }, }; =20 static inline struct rzg2l_mipi_dsi * @@ -186,6 +208,155 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi= _dsi_global_timings[] =3D { }, }; =20 +struct rzv2h_mipi_dsi_timings { + const u8 *hsfreq; + u8 len; + u8 start_index; +}; + +enum { + TCLKPRPRCTL, + TCLKZEROCTL, + TCLKPOSTCTL, + TCLKTRAILCTL, + THSPRPRCTL, + THSZEROCTL, + THSTRAILCTL, + TLPXCTL, + THSEXITCTL, +}; + +static const u8 tclkprprctl[] =3D { + 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150, +}; + +static const u8 tclkzeroctl[] =3D { + 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38, + 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73, + 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105, + 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132, + 134, 137, 139, 141, 143, 146, 148, 150, +}; + +static const u8 tclkpostctl[] =3D { + 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150, +}; + +static const u8 tclktrailctl[] =3D { + 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150, +}; + +static const u8 thsprprctl[] =3D { + 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150, +}; + +static const u8 thszeroctl[] =3D { + 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90, + 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150, +}; + +static const u8 thstrailctl[] =3D { + 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150, +}; + +static const u8 tlpxctl[] =3D { + 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150, +}; + +static const u8 thsexitctl[] =3D { + 15, 23, 31, 39, 47, 55, 63, 71, 79, 87, + 95, 103, 111, 119, 127, 135, 143, 150, +}; + +static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] =3D { + [TCLKPRPRCTL] =3D { + .hsfreq =3D tclkprprctl, + .len =3D ARRAY_SIZE(tclkprprctl), + .start_index =3D 0, + }, + [TCLKZEROCTL] =3D { + .hsfreq =3D tclkzeroctl, + .len =3D ARRAY_SIZE(tclkzeroctl), + .start_index =3D 2, + }, + [TCLKPOSTCTL] =3D { + .hsfreq =3D tclkpostctl, + .len =3D ARRAY_SIZE(tclkpostctl), + .start_index =3D 6, + }, + [TCLKTRAILCTL] =3D { + .hsfreq =3D tclktrailctl, + .len =3D ARRAY_SIZE(tclktrailctl), + .start_index =3D 1, + }, + [THSPRPRCTL] =3D { + .hsfreq =3D thsprprctl, + .len =3D ARRAY_SIZE(thsprprctl), + .start_index =3D 0, + }, + [THSZEROCTL] =3D { + .hsfreq =3D thszeroctl, + .len =3D ARRAY_SIZE(thszeroctl), + .start_index =3D 0, + }, + [THSTRAILCTL] =3D { + .hsfreq =3D thstrailctl, + .len =3D ARRAY_SIZE(thstrailctl), + .start_index =3D 3, + }, + [TLPXCTL] =3D { + .hsfreq =3D tlpxctl, + .len =3D ARRAY_SIZE(tlpxctl), + .start_index =3D 0, + }, + [THSEXITCTL] =3D { + .hsfreq =3D thsexitctl, + .len =3D ARRAY_SIZE(thsexitctl), + .start_index =3D 1, + }, +}; + +static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq) +{ + const unsigned long hsfreq[] =3D { + 1953125UL, + 3906250UL, + 7812500UL, + 15625000UL, + }; + const u16 ulpsexit[] =3D {49, 98, 195, 391}; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(hsfreq); i++) { + if (freq <=3D hsfreq[i]) + break; + } + + if (i =3D=3D ARRAY_SIZE(hsfreq)) + i -=3D 1; + + return ulpsexit[i]; +} + +static u16 rzv2h_dphy_find_timings_val(unsigned long freq, u8 index) +{ + const struct rzv2h_mipi_dsi_timings *timings; + u16 i; + + timings =3D &rzv2h_dsi_timings_tables[index]; + for (i =3D 0; i < timings->len; i++) { + unsigned long hsfreq =3D timings->hsfreq[i] * 10000000UL; + + if (freq <=3D hsfreq) + break; + } + + if (i =3D=3D timings->len) + i -=3D 1; + + return timings->start_index + i; +}; + static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, = u32 data) { iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); @@ -307,6 +478,158 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi= *dsi, unsigned long mode_f return 0; } =20 +static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq) +{ + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi->dsi_parameters; + u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz; + struct rzv2h_plldsi_parameters cpg_dsi_parameters; + unsigned int bpp, i; + + bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + for (i =3D 0; i < 10; i +=3D 1) { + unsigned long hsfreq; + bool parameters_found; + + mode_freq_hz =3D mode_freq * KILO + i; + mode_freq_millihz =3D mode_freq_hz * KILO * 1ULL; + parameters_found =3D rzv2h_dsi_get_pll_parameters_values(dsi->info->cpg_= dsi_limits, + &cpg_dsi_parameters, + mode_freq_millihz); + if (!parameters_found) + continue; + + hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(cpg_dsi_parameters.freq_millihz= * bpp, + dsi->lanes); + parameters_found =3D rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_d= iv_limits, + dsi_parameters, + hsfreq_millihz); + if (!parameters_found) + continue; + + if (abs(dsi_parameters->error_millihz) >=3D 500) + continue; + + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); + if (hsfreq >=3D RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA && + hsfreq <=3D RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA) { + dsi->mode_calc.mode_freq_hz =3D mode_freq_hz; + dsi->mode_calc.mode_freq =3D mode_freq; + return MODE_OK; + } + } + + return MODE_CLOCK_RANGE; +} + +static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, + u64 *hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi->dsi_parameters; + unsigned long status; + + if (dsi->mode_calc.mode_freq !=3D mode_freq) { + status =3D rzv2h_dphy_mode_clk_check(dsi, mode_freq); + if (status !=3D MODE_OK) { + dev_err(dsi->dev, "No PLL parameters found for mode clk %lu\n", + mode_freq); + return -EINVAL; + } + } + + clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz); + *hsfreq_millihz =3D dsi_parameters->freq_millihz; + + return 0; +} + +static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, + u64 hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi->dsi_parameters; + unsigned long lpclk_rate =3D clk_get_rate(dsi->lpclk); + u32 phytclksetr, phythssetr, phytlpxsetr, phycr; + struct rzg2l_mipi_dsi_timings dphy_timings; + u16 ulpsexit; + u64 hsfreq; + + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); + + if (dsi_parameters->freq_millihz =3D=3D hsfreq_millihz) + goto parameters_found; + + if (rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_div_limits, + dsi_parameters, hsfreq_millihz)) + goto parameters_found; + + dev_err(dsi->dev, "No PLL parameters found for HSFREQ %lluHz\n", hsfreq); + return -EINVAL; + +parameters_found: + dphy_timings.tclk_trail =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKTRAILCTL); + dphy_timings.tclk_post =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKPOSTCTL); + dphy_timings.tclk_zero =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKZEROCTL); + dphy_timings.tclk_prepare =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKPRPRCTL); + dphy_timings.ths_exit =3D + rzv2h_dphy_find_timings_val(hsfreq, THSEXITCTL); + dphy_timings.ths_trail =3D + rzv2h_dphy_find_timings_val(hsfreq, THSTRAILCTL); + dphy_timings.ths_zero =3D + rzv2h_dphy_find_timings_val(hsfreq, THSZEROCTL); + dphy_timings.ths_prepare =3D + rzv2h_dphy_find_timings_val(hsfreq, THSPRPRCTL); + dphy_timings.tlpx =3D + rzv2h_dphy_find_timings_val(hsfreq, TLPXCTL); + ulpsexit =3D rzv2h_dphy_find_ulpsexit(lpclk_rate); + + phytclksetr =3D PHYTCLKSETR_TCLKTRAILCTL(dphy_timings.tclk_trail) | + PHYTCLKSETR_TCLKPOSTCTL(dphy_timings.tclk_post) | + PHYTCLKSETR_TCLKZEROCTL(dphy_timings.tclk_zero) | + PHYTCLKSETR_TCLKPRPRCTL(dphy_timings.tclk_prepare); + phythssetr =3D PHYTHSSETR_THSEXITCTL(dphy_timings.ths_exit) | + PHYTHSSETR_THSTRAILCTL(dphy_timings.ths_trail) | + PHYTHSSETR_THSZEROCTL(dphy_timings.ths_zero) | + PHYTHSSETR_THSPRPRCTL(dphy_timings.ths_prepare); + phytlpxsetr =3D rzg2l_mipi_dsi_phy_read(dsi, PHYTLPXSETR) & ~GENMASK(7, 0= ); + phytlpxsetr |=3D PHYTLPXSETR_TLPXCTL(dphy_timings.tlpx); + phycr =3D rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0); + phycr |=3D PHYCR_ULPSEXIT(ulpsexit); + + /* Setting all D-PHY Timings Registers */ + rzg2l_mipi_dsi_phy_write(dsi, PHYTCLKSETR, phytclksetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTHSSETR, phythssetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTLPXSETR, phytlpxsetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYCR, phycr); + + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET0R, + PLLCLKSET0R_PLL_S(dsi_parameters->s) | + PLLCLKSET0R_PLL_P(dsi_parameters->p) | + PLLCLKSET0R_PLL_M(dsi_parameters->m)); + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R, PLLCLKSET1R_PLL_K(dsi_paramete= rs->k)); + fsleep(20); + + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, PLLENR_PLLEN); + fsleep(500); + + return 0; +} + +static void rzv2h_mipi_dsi_dphy_late_init(struct rzg2l_mipi_dsi *dsi) +{ + fsleep(220); + rzg2l_mipi_dsi_phy_write(dsi, PHYRSTR, PHYRSTR_PHYMRSTN); +} + +static void rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) +{ + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, 0); +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { @@ -409,6 +732,9 @@ static void rzg2l_mipi_dsi_set_display_timing(struct rz= g2l_mipi_dsi *dsi, case 18: vich1ppsetr =3D VICH1PPSETR_DT_RGB18; break; + case 16: + vich1ppsetr =3D VICH1PPSETR_DT_RGB16; + break; } =20 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) && @@ -864,6 +1190,23 @@ static void rzg2l_mipi_dsi_remove(struct platform_dev= ice *pdev) pm_runtime_disable(&pdev->dev); } =20 +RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits); + +static const struct rzg2l_mipi_dsi_hw_info rzv2h_mipi_dsi_info =3D { + .dphy_init =3D rzv2h_mipi_dsi_dphy_init, + .dphy_late_init =3D rzv2h_mipi_dsi_dphy_late_init, + .dphy_exit =3D rzv2h_mipi_dsi_dphy_exit, + .dphy_mode_clk_check =3D rzv2h_dphy_mode_clk_check, + .dphy_conf_clks =3D rzv2h_dphy_conf_clks, + .cpg_dsi_limits =3D &rzv2h_cpg_pll_dsi_limits, + .phy_reg_offset =3D 0x10000, + .link_reg_offset =3D 0, + .max_dclk =3D 187500, + .min_dclk =3D 5440, + .features =3D RZ_MIPI_DSI_FEATURE_16BPP | + RZ_MIPI_DSI_FEATURE_LPCLK, +}; + static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info =3D { .dphy_init =3D rzg2l_mipi_dsi_dphy_init, .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, @@ -875,6 +1218,7 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_= dsi_info =3D { }; =20 static const struct of_device_id rzg2l_mipi_dsi_of_table[] =3D { + { .compatible =3D "renesas,r9a09g057-mipi-dsi", .data =3D &rzv2h_mipi_dsi= _info, }, { .compatible =3D "renesas,rzg2l-mipi-dsi", .data =3D &rzg2l_mipi_dsi_inf= o, }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/= gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h index 16efe4dc59f4..68165395d61c 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h @@ -40,6 +40,39 @@ #define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) =20 +/* RZ/V2H DPHY Registers */ +#define PLLENR 0x000 +#define PLLENR_PLLEN BIT(0) + +#define PHYRSTR 0x004 +#define PHYRSTR_PHYMRSTN BIT(0) + +#define PLLCLKSET0R 0x010 +#define PLLCLKSET0R_PLL_S(x) ((x) << 0) +#define PLLCLKSET0R_PLL_P(x) ((x) << 8) +#define PLLCLKSET0R_PLL_M(x) ((x) << 16) + +#define PLLCLKSET1R 0x014 +#define PLLCLKSET1R_PLL_K(x) ((x) << 0) + +#define PHYTCLKSETR 0x020 +#define PHYTCLKSETR_TCLKTRAILCTL(x) ((x) << 0) +#define PHYTCLKSETR_TCLKPOSTCTL(x) ((x) << 8) +#define PHYTCLKSETR_TCLKZEROCTL(x) ((x) << 16) +#define PHYTCLKSETR_TCLKPRPRCTL(x) ((x) << 24) + +#define PHYTHSSETR 0x024 +#define PHYTHSSETR_THSEXITCTL(x) ((x) << 0) +#define PHYTHSSETR_THSTRAILCTL(x) ((x) << 8) +#define PHYTHSSETR_THSZEROCTL(x) ((x) << 16) +#define PHYTHSSETR_THSPRPRCTL(x) ((x) << 24) + +#define PHYTLPXSETR 0x028 +#define PHYTLPXSETR_TLPXCTL(x) ((x) << 0) + +#define PHYCR 0x030 +#define PHYCR_ULPSEXIT(x) ((x) << 0) + /* --------------------------------------------------------*/ =20 /* Link Status Register */ @@ -116,6 +149,7 @@ =20 /* Video-Input Channel 1 Pixel Packet Set Register */ #define VICH1PPSETR 0x420 +#define VICH1PPSETR_DT_RGB16 (0x0e << 16) #define VICH1PPSETR_DT_RGB18 (0x1e << 16) #define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) #define VICH1PPSETR_DT_RGB24 (0x3e << 16) --=20 2.49.0