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Fri, 18 Apr 2025 11:47:26 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:25 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling Date: Fri, 18 Apr 2025 19:46:57 +0100 Message-ID: <20250418184658.456398-15-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration. On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not present. To accommodate this difference, add an `lpclk` clock handle in `rzg2l_mipi_dsi` and update the probe function to conditionally acquire LPCLK if the SoC supports it. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - Added LPCLK as feature flag --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 67520bb21dad..133a8f306d47 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -30,6 +30,7 @@ =20 #define RZ_MIPI_DSI_FEATURE_DPHY_RST BIT(0) #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) +#define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2) =20 struct rzg2l_mipi_dsi; =20 @@ -63,6 +64,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; =20 struct clk *vclk; + struct clk *lpclk; =20 enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -788,6 +790,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device= *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); =20 + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_LPCLK) { + dsi->lpclk =3D devm_clk_get(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + } + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_DPHY_RST) { dsi->rstc =3D devm_reset_control_get_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) --=20 2.49.0