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Peter Anvin" CC: Subject: [PATCH v5 02/16] x86/bugs: Restructure TAA mitigation Date: Fri, 18 Apr 2025 11:17:07 -0500 Message-ID: <20250418161721.1855190-3-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250418161721.1855190-1-david.kaplan@amd.com> References: <20250418161721.1855190-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|DS4PR12MB9562:EE_ X-MS-Office365-Filtering-Correlation-Id: 4dcc5a20-9ff8-402e-f289-08dd7e9486bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?W99eU3Q8IYvADfkXf70h1uns6Nc8/l6J9LhTEmEX2J8AOfIh2sYoLeNMnUIc?= =?us-ascii?Q?dLErY/eqOVH/6Y5Cwhg2r/v4IecV3Ps74anP0wU0ciH7N5lqylnLGuT9FP9M?= =?us-ascii?Q?/OvJUoBEL4wPsfRIqYIHfRbaJS37HFVMisDMvn0hT5NSSCNVHuRH17sUljR+?= =?us-ascii?Q?Ucy10lgHCZdr08TL4CWDBXIj72JNoNnaIn7MTzRwgwCxkVOkkYIygVEfcijL?= =?us-ascii?Q?DLFunqG9IkHmFXt9IScf1YGsNBMsZfcsPcVVrtzuETl46WiKhseatBY5kzLR?= =?us-ascii?Q?Sj0zad63utTKBkWuZqn1mJgb01/fU1vVVBwdkuGUmy6cVlw+fQzrz3nP1/8x?= =?us-ascii?Q?t3w6DAzv18rUMGiBAvBGOYYhZcfEJFrNn/Xnor87OOY7nBNucxvoNKPrMdVU?= =?us-ascii?Q?/Qo8gwsNcfxu72Dy8g2Gv7DcfuOxmO55nYFIqzZ163v/5qJbQGsZ4Mc9ggZa?= =?us-ascii?Q?w1QWpEEKkSrXLoQittV3Aihr/dzAEGUnFH38akKPQVB26EG9TwT07aSYGa28?= =?us-ascii?Q?4Melk8Y/2WB9skwkZFOdqtLUCEcsZ7PZJv7CvhdLuKd3CSNubm/XevyplaK0?= =?us-ascii?Q?WTGldA3Sg298fEuvrUlbZvbsmVqH8QCijePkMqMiBOSpNAPrXbi+A7ahW4Qf?= =?us-ascii?Q?5jd3eaiW+jtB1rPw5p6OJT9X/npftzSOgd4rKD5wPblqy+dYDTg9+y+Jf8JT?= =?us-ascii?Q?34uuLxmOOy10TIEdWs/MiTL2ylc0MPaitLUMCJMHLQByrh/Ec6nMuLfbnxrc?= =?us-ascii?Q?X6neYAZ33xZf4bP4yotBLhM9uny+/OEh2zJzccEADMQ1Be8z0Nd6XGAi/uKr?= =?us-ascii?Q?STT+AGOfgol2h3ZQ8sEuTWHQq666Y1sar8G3OGnj/VYUeDNu9KLE2saYq5Mf?= =?us-ascii?Q?ULtXqxM0zC7jM+1zMcNIgPmpnn+bCbf/fWCf2HcHOhYxfMuJkwtzgsgtjC8C?= =?us-ascii?Q?qEPyMWwPyiyuTnHOogNE/QgpWMdRNUuQYqzDEenwKs0mJoMqb1dW74dFaoUa?= =?us-ascii?Q?YX1C/JT5kSP2vpNSMaBjsyIgYGLLzUM6ddYz5tk9XkDhzlxuNJ3mbfPMPWfO?= =?us-ascii?Q?t/zlWfKlZEsail47Q6TsIiOH1Cvzz65Hy1O6jAVc4tezZGuNA2kr1i1W9oI2?= =?us-ascii?Q?AtDxia+VukNheFLM5CKPJ4jgS+0GdhrMS4pZIJqcFPJ5N0YVLb+Blw3fIjyI?= =?us-ascii?Q?CZEQZAmWsA0s+ATTHuUli4FWqoqHvC5xfPfgwTDMiFhbJ0aXox38ppqELdE7?= =?us-ascii?Q?LjO4/89S6K4qU3KRP6Sj1MT7pHcrQjccF0Wo7ZSDNG56BDPj1JiFfDV5neMN?= =?us-ascii?Q?N7y9pnK+ShXPMZ3aTAWoltqUt6YdNWjstOhJpIJoPQVynFxAvH5tSCll34hh?= =?us-ascii?Q?mrwZApt9pA+ucQFlJbcVNe63+E9PCcuUraZnxKEjCJ+AXmd5vZsdFcgJs1/m?= =?us-ascii?Q?8qYu9ktGTXAsHrOCHc5E027lEZcso75vGunPWomiqBXBuLY/0GtijovpDMcD?= =?us-ascii?Q?1WU30GzlU94zDt/llB9zM4sQdVbWbSe2tau4?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2025 16:17:33.6361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4dcc5a20-9ff8-402e-f289-08dd7e9486bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9562 Content-Type: text/plain; charset="utf-8" Restructure TAA mitigation to use select/update/apply functions to create consistent vulnerability handling. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 94 ++++++++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 35 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4295502ea082..c0ba034ae1f9 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,6 +65,8 @@ static void __init mds_apply_mitigation(void); static void __init md_clear_update_mitigation(void); static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); +static void __init taa_update_mitigation(void); +static void __init taa_apply_mitigation(void); static void __init mmio_select_mitigation(void); static void __init srbds_select_mitigation(void); static void __init l1d_flush_select_mitigation(void); @@ -194,6 +196,7 @@ void __init cpu_select_mitigations(void) ssb_select_mitigation(); l1tf_select_mitigation(); mds_select_mitigation(); + taa_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); @@ -210,8 +213,10 @@ void __init cpu_select_mitigations(void) * choices. */ mds_update_mitigation(); + taa_update_mitigation(); =20 mds_apply_mitigation(); + taa_apply_mitigation(); } =20 /* @@ -394,6 +399,11 @@ static const char * const taa_strings[] =3D { [TAA_MITIGATION_TSX_DISABLED] =3D "Mitigation: TSX disabled", }; =20 +static bool __init taa_vulnerable(void) +{ + return boot_cpu_has_bug(X86_BUG_TAA) && boot_cpu_has(X86_FEATURE_RTM); +} + static void __init taa_select_mitigation(void) { if (!boot_cpu_has_bug(X86_BUG_TAA)) { @@ -407,48 +417,63 @@ static void __init taa_select_mitigation(void) return; } =20 - if (cpu_mitigations_off()) { + if (cpu_mitigations_off()) taa_mitigation =3D TAA_MITIGATION_OFF; - return; - } =20 - /* - * TAA mitigation via VERW is turned off if both - * tsx_async_abort=3Doff and mds=3Doff are specified. - */ - if (taa_mitigation =3D=3D TAA_MITIGATION_OFF && - mds_mitigation =3D=3D MDS_MITIGATION_OFF) + /* Microcode will be checked in taa_update_mitigation(). */ + if (taa_mitigation =3D=3D TAA_MITIGATION_AUTO) + taa_mitigation =3D TAA_MITIGATION_VERW; + + if (taa_mitigation !=3D TAA_MITIGATION_OFF) + verw_mitigation_selected =3D true; +} + +static void __init taa_update_mitigation(void) +{ + if (!taa_vulnerable() || cpu_mitigations_off()) return; =20 - if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) + if (verw_mitigation_selected) taa_mitigation =3D TAA_MITIGATION_VERW; - else - taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; =20 - /* - * VERW doesn't clear the CPU buffers when MD_CLEAR=3D1 and MDS_NO=3D1. - * A microcode update fixes this behavior to clear CPU buffers. It also - * adds support for MSR_IA32_TSX_CTRL which is enumerated by the - * ARCH_CAP_TSX_CTRL_MSR bit. - * - * On MDS_NO=3D1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode - * update is required. - */ - if ( (x86_arch_cap_msr & ARCH_CAP_MDS_NO) && - !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)) - taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; + if (taa_mitigation =3D=3D TAA_MITIGATION_VERW) { + /* Check if the requisite ucode is available. */ + if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) + taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; =20 - /* - * TSX is enabled, select alternate mitigation for TAA which is - * the same as MDS. Enable MDS static branch to clear CPU buffers. - * - * For guests that can't determine whether the correct microcode is - * present on host, enable the mitigation for UCODE_NEEDED as well. - */ - setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); + /* + * VERW doesn't clear the CPU buffers when MD_CLEAR=3D1 and MDS_NO=3D1. + * A microcode update fixes this behavior to clear CPU buffers. It also + * adds support for MSR_IA32_TSX_CTRL which is enumerated by the + * ARCH_CAP_TSX_CTRL_MSR bit. + * + * On MDS_NO=3D1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode + * update is required. + */ + if ((x86_arch_cap_msr & ARCH_CAP_MDS_NO) && + !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)) + taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; + } =20 - if (taa_nosmt || cpu_mitigations_auto_nosmt()) - cpu_smt_disable(false); + pr_info("%s\n", taa_strings[taa_mitigation]); +} + +static void __init taa_apply_mitigation(void) +{ + if (taa_mitigation =3D=3D TAA_MITIGATION_VERW || + taa_mitigation =3D=3D TAA_MITIGATION_UCODE_NEEDED) { + /* + * TSX is enabled, select alternate mitigation for TAA which is + * the same as MDS. Enable MDS static branch to clear CPU buffers. + * + * For guests that can't determine whether the correct microcode is + * present on host, enable the mitigation for UCODE_NEEDED as well. + */ + setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); + + if (taa_nosmt || cpu_mitigations_auto_nosmt()) + cpu_smt_disable(false); + } } =20 static int __init tsx_async_abort_parse_cmdline(char *str) @@ -654,7 +679,6 @@ static void __init md_clear_update_mitigation(void) =20 static void __init md_clear_select_mitigation(void) { - taa_select_mitigation(); mmio_select_mitigation(); rfds_select_mitigation(); =20 --=20 2.34.1