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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:14 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/7] clk: spacemit: define new syscons with only resets Date: Fri, 18 Apr 2025 09:53:58 -0500 Message-ID: <20250418145401.2603648-7-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 93 +++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index dfc8aa60d4345..c2f057aecb705 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,36 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct ccu_reset_data { u32 offset; u32 assert_mask; @@ -1177,6 +1207,57 @@ static const struct spacemit_ccu_data k1_ccu_apmu_da= ta =3D { .reset_num =3D ARRAY_SIZE(apmu_reset_data), }; =20 +static const struct ccu_reset_data rcpu_reset_data[] =3D { + [RESET_RCPU_SSP0] =3D RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_I2C0] =3D RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART1] =3D RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RESET_RCPU_IR] =3D RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RESET_RCPU_CAN] =3D RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART0] =3D RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_HDMI_AUDIO] =3D RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu_data =3D { + /* No clocks in the RCPU CCU */ + .reset_data =3D rcpu_reset_data, + .reset_num =3D ARRAY_SIZE(rcpu_reset_data), +}; + +static const struct ccu_reset_data rcpu2_reset_data[] =3D { + [RESET_RCPU2_PWM0] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM9] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu2_data =3D { + /* No clocks in the RCPU2 CCU */ + .reset_data =3D rcpu2_reset_data, + .reset_num =3D ARRAY_SIZE(rcpu2_reset_data), +}; + +static const struct ccu_reset_data apbc2_reset_data[] =3D { + [RESET_APBC2_UART1] =3D RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), + [RESET_APBC2_SSP2] =3D RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), + [RESET_APBC2_TWSI3] =3D RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), + [RESET_APBC2_RTC] =3D RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC2_TIMERS0] =3D RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC2_KPC] =3D RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), + [RESET_APBC2_GPIO] =3D RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), +}; + +static const struct spacemit_ccu_data k1_ccu_apbc2_data =3D { + /* No clocks in the APBC2 CCU */ + .reset_data =3D apbc2_reset_data, + .reset_num =3D ARRAY_SIZE(apbc2_reset_data), +}; + static int spacemit_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -1351,6 +1432,18 @@ static const struct of_device_id of_k1_ccu_match[] = =3D { .compatible =3D "spacemit,k1-syscon-apmu", .data =3D &k1_ccu_apmu_data, }, + { + .compatible =3D "spacemit,k1-syscon-rcpu", + .data =3D &k1_ccu_rcpu_data, + }, + { + .compatible =3D "spacemit,k1-syscon-rcpu2", + .data =3D &k1_ccu_rcpu2_data, + }, + { + .compatible =3D "spacemit,k1-syscon-apbc2", + .data =3D &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); --=20 2.45.2