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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:11 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/7] clk: spacemit: define existing syscon resets Date: Fri, 18 Apr 2025 09:53:56 -0500 Message-ID: <20250418145401.2603648-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 120 ++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 9152cce00ce90..ad5f41695f8db 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -136,6 +136,13 @@ struct ccu_reset_data { u32 deassert_mask; }; =20 +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + struct spacemit_ccu_data { struct clk_hw **clk_hws; /* array */ size_t clk_num; @@ -836,6 +843,7 @@ static struct clk_hw *k1_ccu_pll_hws[] =3D { static const struct spacemit_ccu_data k1_ccu_pll_data =3D { .clk_hws =3D k1_ccu_pll_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_pll_hws), + /* No resets in the PLL CCU */ }; =20 static struct clk_hw *k1_ccu_mpmu_hws[] =3D { @@ -874,9 +882,15 @@ static struct clk_hw *k1_ccu_mpmu_hws[] =3D { [CLK_WDT_BUS] =3D &wdt_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data mpmu_reset_data[] =3D { + [RESET_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_mpmu_data =3D { .clk_hws =3D k1_ccu_mpmu_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), + .reset_data =3D mpmu_reset_data, + .reset_num =3D ARRAY_SIZE(mpmu_reset_data), }; =20 static struct clk_hw *k1_ccu_apbc_hws[] =3D { @@ -982,9 +996,65 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { [CLK_IPC_AP2AUD_BUS] =3D &ipc_ap2aud_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data apbc_reset_data[] =3D { + [RESET_UART0] =3D RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] =3D RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] =3D RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_apbc_data =3D { .clk_hws =3D k1_ccu_apbc_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_apbc_hws), + .reset_data =3D apbc_reset_data, + .reset_num =3D ARRAY_SIZE(apbc_reset_data), }; =20 static struct clk_hw *k1_ccu_apmu_hws[] =3D { @@ -1052,9 +1122,59 @@ static struct clk_hw *k1_ccu_apmu_hws[] =3D { [CLK_EMMC_BUS] =3D &emmc_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data apmu_reset_data[] =3D { + [RESET_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] =3D RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] =3D RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] =3D RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; + static const struct spacemit_ccu_data k1_ccu_apmu_data =3D { .clk_hws =3D k1_ccu_apmu_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_apmu_hws), + .reset_data =3D apmu_reset_data, + .reset_num =3D ARRAY_SIZE(apmu_reset_data), }; =20 static int spacemit_reset_update(struct reset_controller_dev *rcdev, --=20 2.45.2