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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:07 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/7] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Date: Fri, 18 Apr 2025 09:53:53 -0500 Message-ID: <20250418145401.2603648-2-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will (initially) support only resets. They do not incorporate power domain functionality. Previously the clock properties were required for all compatible nodes. Make that requirement only apply to the three existing CCUs (APBC, APMU, and MPMU), so that the new reset-only CCUs can go without specifying them. Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks). Signed-off-by: Alex Elder Reviewed-by: Krzysztof Kozlowski Reviewed-by: Yixun Lan --- .../soc/spacemit/spacemit,k1-syscon.yaml | 29 +++- .../dt-bindings/clock/spacemit,k1-syscon.h | 128 ++++++++++++++++++ 2 files changed, 150 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-sys= con.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-sysco= n.yaml index 30aaf49da03d3..133a391ee68cd 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -19,6 +19,9 @@ properties: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 =20 reg: maxItems: 1 @@ -47,9 +50,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - - "#clock-cells" - "#reset-cells" =20 allOf: @@ -57,13 +57,28 @@ allOf: properties: compatible: contains: - const: spacemit,k1-syscon-apbc + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu then: - properties: - "#power-domain-cells": false - else: required: - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu + then: + required: + - clocks + - clock-names + - "#clock-cells" =20 additionalProperties: false =20 diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bi= ndings/clock/spacemit,k1-syscon.h index 35968ae982466..f5965dda3b905 100644 --- a/include/dt-bindings/clock/spacemit,k1-syscon.h +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -78,6 +78,9 @@ #define CLK_APB 31 #define CLK_WDT_BUS 32 =20 +/* MPMU resets */ +#define RESET_WDT 0 + /* APBC clocks */ #define CLK_UART0 0 #define CLK_UART2 1 @@ -180,6 +183,59 @@ #define CLK_TSEN_BUS 98 #define CLK_IPC_AP2AUD_BUS 99 =20 +/* APBC resets */ +#define RESET_UART0 0 +#define RESET_UART2 1 +#define RESET_UART3 2 +#define RESET_UART4 3 +#define RESET_UART5 4 +#define RESET_UART6 5 +#define RESET_UART7 6 +#define RESET_UART8 7 +#define RESET_UART9 8 +#define RESET_GPIO 9 +#define RESET_PWM0 10 +#define RESET_PWM1 11 +#define RESET_PWM2 12 +#define RESET_PWM3 13 +#define RESET_PWM4 14 +#define RESET_PWM5 15 +#define RESET_PWM6 16 +#define RESET_PWM7 17 +#define RESET_PWM8 18 +#define RESET_PWM9 19 +#define RESET_PWM10 20 +#define RESET_PWM11 21 +#define RESET_PWM12 22 +#define RESET_PWM13 23 +#define RESET_PWM14 24 +#define RESET_PWM15 25 +#define RESET_PWM16 26 +#define RESET_PWM17 27 +#define RESET_PWM18 28 +#define RESET_PWM19 29 +#define RESET_SSP3 30 +#define RESET_RTC 31 +#define RESET_TWSI0 32 +#define RESET_TWSI1 33 +#define RESET_TWSI2 34 +#define RESET_TWSI4 35 +#define RESET_TWSI5 36 +#define RESET_TWSI6 37 +#define RESET_TWSI7 38 +#define RESET_TWSI8 39 +#define RESET_TIMERS1 40 +#define RESET_TIMERS2 41 +#define RESET_AIB 42 +#define RESET_ONEWIRE 43 +#define RESET_SSPA0 44 +#define RESET_SSPA1 45 +#define RESET_DRO 46 +#define RESET_IR 47 +#define RESET_TSEN 48 +#define RESET_IPC_AP2AUD 49 +#define RESET_CAN0 50 + /* APMU clocks */ #define CLK_CCI550 0 #define CLK_CPU_C0_HI 1 @@ -244,4 +300,76 @@ #define CLK_V2D 60 #define CLK_EMMC_BUS 61 =20 +/* APMU resets */ +#define RESET_CCIC_4X 0 +#define RESET_CCIC1_PHY 1 +#define RESET_SDH_AXI 2 +#define RESET_SDH0 3 +#define RESET_SDH1 4 +#define RESET_SDH2 5 +#define RESET_USBP1_AXI 6 +#define RESET_USB_AXI 7 +#define RESET_USB3_0 8 +#define RESET_QSPI 9 +#define RESET_QSPI_BUS 10 +#define RESET_DMA 11 +#define RESET_AES 12 +#define RESET_VPU 13 +#define RESET_GPU 14 +#define RESET_EMMC 15 +#define RESET_EMMC_X 16 +#define RESET_AUDIO 17 +#define RESET_HDMI 18 +#define RESET_PCIE0 19 +#define RESET_PCIE1 20 +#define RESET_PCIE2 21 +#define RESET_EMAC0 22 +#define RESET_EMAC1 23 +#define RESET_JPG 24 +#define RESET_CCIC2PHY 25 +#define RESET_CCIC3PHY 26 +#define RESET_CSI 27 +#define RESET_ISP_CPP 28 +#define RESET_ISP_BUS 29 +#define RESET_ISP 30 +#define RESET_ISP_CI 31 +#define RESET_DPU_MCLK 32 +#define RESET_DPU_ESC 33 +#define RESET_DPU_HCLK 34 +#define RESET_DPU_SPIBUS 35 +#define RESET_DPU_SPI_HBUS 36 +#define RESET_V2D 37 +#define RESET_MIPI 38 +#define RESET_MC 39 + +/* RCPU resets */ +#define RESET_RCPU_SSP0 0 +#define RESET_RCPU_I2C0 1 +#define RESET_RCPU_UART1 2 +#define RESET_RCPU_IR 3 +#define RESET_RCPU_CAN 4 +#define RESET_RCPU_UART0 5 +#define RESET_RCPU_HDMI_AUDIO 6 + +/* RCPU2 resets */ +#define RESET_RCPU2_PWM0 0 +#define RESET_RCPU2_PWM1 1 +#define RESET_RCPU2_PWM2 2 +#define RESET_RCPU2_PWM3 3 +#define RESET_RCPU2_PWM4 4 +#define RESET_RCPU2_PWM5 5 +#define RESET_RCPU2_PWM6 6 +#define RESET_RCPU2_PWM7 7 +#define RESET_RCPU2_PWM8 8 +#define RESET_RCPU2_PWM9 9 + +/* APBC2 resets */ +#define RESET_APBC2_UART1 0 +#define RESET_APBC2_SSP2 1 +#define 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:08 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/7] clk: spacemit: rename spacemit_ccu_data fields Date: Fri, 18 Apr 2025 09:53:54 -0500 Message-ID: <20250418145401.2603648-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add "clk_" to the names of the fields in the spacemit_ccu_data structure type. This prepares it for the addition of two similar fields dedicated to resets. Signed-off-by: Alex Elder Reviewed-by: Haylen Chu Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cdde37a052353..a7712d1681a11 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,8 +130,8 @@ #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 struct spacemit_ccu_data { - struct clk_hw **hws; - size_t num; + struct clk_hw **clk_hws; + size_t clk_num; }; =20 /* APBS clocks start, APBS region contains and only contains all PLL clock= s */ @@ -819,8 +819,8 @@ static struct clk_hw *k1_ccu_pll_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_pll_data =3D { - .hws =3D k1_ccu_pll_hws, - .num =3D ARRAY_SIZE(k1_ccu_pll_hws), + .clk_hws =3D k1_ccu_pll_hws, + .clk_num =3D ARRAY_SIZE(k1_ccu_pll_hws), }; =20 static struct clk_hw *k1_ccu_mpmu_hws[] =3D { @@ -860,8 +860,8 @@ static struct clk_hw *k1_ccu_mpmu_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_mpmu_data =3D { - .hws =3D k1_ccu_mpmu_hws, - .num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), + .clk_hws =3D k1_ccu_mpmu_hws, + .clk_num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), }; =20 static struct clk_hw *k1_ccu_apbc_hws[] =3D { @@ -968,8 +968,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_apbc_data =3D { - .hws =3D k1_ccu_apbc_hws, - .num =3D ARRAY_SIZE(k1_ccu_apbc_hws), + .clk_hws =3D k1_ccu_apbc_hws, + .clk_num =3D ARRAY_SIZE(k1_ccu_apbc_hws), }; =20 static struct clk_hw *k1_ccu_apmu_hws[] =3D { @@ -1038,8 +1038,8 @@ static struct clk_hw *k1_ccu_apmu_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_apmu_data =3D { - .hws =3D k1_ccu_apmu_hws, - .num =3D ARRAY_SIZE(k1_ccu_apmu_hws), + .clk_hws =3D k1_ccu_apmu_hws, + .clk_num =3D ARRAY_SIZE(k1_ccu_apmu_hws), }; =20 static int spacemit_ccu_register(struct device *dev, @@ -1050,13 +1050,13 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:10 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/7] clk: spacemit: add reset controller support Date: Fri, 18 Apr 2025 09:53:55 -0500 Message-ID: <20250418145401.2603648-4-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define ccu_reset_data as a structure that contains the constant register offset and bitmasks used to assert and deassert a reset control on a SpacemiT K1 CCU. Add a pointer to an array of those structures to the spacemit_ccu_data structure, along with a field indicating how many elements are in that array. Resets will be optional, and if none are defined the reset array pointer will be null. Define a new ccu_reset_controller structure, which (for a CCU with resets) contains a pointer to the constant reset data, the regmap to be used for the controller, and an embedded a reset controller structure. Each reset control is asserted or deasserted by updating bits in a register. The bits used are defined by an assert mask and a deassert mask. In some cases, one (non-zero) mask asserts reset and a different (non-zero) mask deasserts it. Otherwise one mask is nonzero, and the other is zero. Either way, the bits in both masks are cleared, then either the assert mask or the deassert mask is set in a register to affect the state of a reset control. Signed-off-by: Alex Elder Reviewed-by: Philipp Zabel Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 86 +++++++++++++++++++++++++++++++++-- 1 file changed, 83 insertions(+), 3 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index a7712d1681a11..9152cce00ce90 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "ccu_common.h" #include "ccu_pll.h" @@ -129,9 +130,23 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + struct spacemit_ccu_data { - struct clk_hw **clk_hws; + struct clk_hw **clk_hws; /* array */ size_t clk_num; + const struct ccu_reset_data *reset_data; /* array */ + size_t reset_num; +}; + +struct ccu_reset_controller { + struct regmap *regmap; + const struct spacemit_ccu_data *data; + struct reset_controller_dev rcdev; }; =20 /* APBS clocks start, APBS region contains and only contains all PLL clock= s */ @@ -1042,6 +1057,39 @@ static const struct spacemit_ccu_data k1_ccu_apmu_da= ta =3D { .clk_num =3D ARRAY_SIZE(k1_ccu_apmu_hws), }; =20 +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller =3D container_of(rcdev, struct ccu_reset_controller, rcdev); + data =3D &controller->data->reset_data[id]; + mask =3D data->assert_mask | data->deassert_mask; + val =3D assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops spacemit_reset_control_ops =3D { + .assert =3D spacemit_reset_assert, + .deassert =3D spacemit_reset_deassert, +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, @@ -1090,9 +1138,37 @@ static int spacemit_ccu_register(struct device *dev, return ret; } =20 +static int spacemit_reset_controller_register(struct device *dev, + struct regmap *regmap, + const struct spacemit_ccu_data *data) +{ + struct ccu_reset_controller *controller; + struct reset_controller_dev *rcdev; + + /* Resets are optional */ + if (!data->reset_data) + return 0; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + + controller->regmap =3D regmap; + controller->data =3D data; + + rcdev =3D &controller->rcdev; + rcdev->ops =3D &spacemit_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D data->reset_num; + + return devm_reset_controller_register(dev, rcdev); +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap =3D NULL; + const struct spacemit_ccu_data *data; struct device *dev =3D &pdev->dev; int ret; =20 @@ -1121,11 +1197,15 @@ static int k1_ccu_probe(struct platform_device *pde= v) "failed to get lock regmap\n"); } =20 - ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + data =3D of_device_get_match_data(dev); + ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, data); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); =20 + ret =3D spacemit_reset_controller_register(dev, base_regmap, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register reset controller\n"); + return 0; } =20 --=20 2.45.2 From nobody Sun Feb 8 13:09:22 2026 Received: from mail-qt1-f179.google.com (mail-qt1-f179.google.com [209.85.160.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D0091DE2A4 for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:11 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/7] clk: spacemit: define existing syscon resets Date: Fri, 18 Apr 2025 09:53:56 -0500 Message-ID: <20250418145401.2603648-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 120 ++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 9152cce00ce90..ad5f41695f8db 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -136,6 +136,13 @@ struct ccu_reset_data { u32 deassert_mask; }; =20 +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + struct spacemit_ccu_data { struct clk_hw **clk_hws; /* array */ size_t clk_num; @@ -836,6 +843,7 @@ static struct clk_hw *k1_ccu_pll_hws[] =3D { static const struct spacemit_ccu_data k1_ccu_pll_data =3D { .clk_hws =3D k1_ccu_pll_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_pll_hws), + /* No resets in the PLL CCU */ }; =20 static struct clk_hw *k1_ccu_mpmu_hws[] =3D { @@ -874,9 +882,15 @@ static struct clk_hw *k1_ccu_mpmu_hws[] =3D { [CLK_WDT_BUS] =3D &wdt_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data mpmu_reset_data[] =3D { + [RESET_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_mpmu_data =3D { .clk_hws =3D k1_ccu_mpmu_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), + .reset_data =3D mpmu_reset_data, + .reset_num =3D ARRAY_SIZE(mpmu_reset_data), }; =20 static struct clk_hw *k1_ccu_apbc_hws[] =3D { @@ -982,9 +996,65 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { [CLK_IPC_AP2AUD_BUS] =3D &ipc_ap2aud_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data apbc_reset_data[] =3D { + [RESET_UART0] =3D RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] =3D RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] =3D RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_apbc_data =3D { .clk_hws =3D k1_ccu_apbc_hws, .clk_num =3D ARRAY_SIZE(k1_ccu_apbc_hws), + .reset_data =3D apbc_reset_data, + .reset_num =3D ARRAY_SIZE(apbc_reset_data), }; =20 static struct clk_hw *k1_ccu_apmu_hws[] =3D { @@ -1052,9 +1122,59 @@ static struct clk_hw *k1_ccu_apmu_hws[] =3D { [CLK_EMMC_BUS] =3D &emmc_bus_clk.common.hw, }; =20 +static const struct ccu_reset_data apmu_reset_data[] =3D { + [RESET_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] =3D RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] =3D RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] =3D RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:12 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/7] clk: spacemit: make clocks optional Date: Fri, 18 Apr 2025 09:53:57 -0500 Message-ID: <20250418145401.2603648-6-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are some syscon devices that support both clocks and resets, but for now only their reset functionality is required. Make defining clocks optional for a SpacemiT CCU, though at least one clock or at least one reset controller must be defined. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index ad5f41695f8db..dfc8aa60d4345 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -1218,6 +1218,10 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; int i, ret; =20 + /* Clocks are optional */ + if (!data->clk_hws) + return 0; + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, data->clk_num), GFP_KERNEL); if (!clk_data) @@ -1329,6 +1333,7 @@ static int k1_ccu_probe(struct platform_device *pdev) return 0; } =20 +/* Match data is required; its clk_hws or reset_data field must be non-nul= l */ static const struct of_device_id of_k1_ccu_match[] =3D { { .compatible =3D "spacemit,k1-pll", --=20 2.45.2 From nobody Sun Feb 8 13:09:22 2026 Received: from mail-qt1-f179.google.com (mail-qt1-f179.google.com [209.85.160.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B00DC1E1A20 for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:14 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/7] clk: spacemit: define new syscons with only resets Date: Fri, 18 Apr 2025 09:53:58 -0500 Message-ID: <20250418145401.2603648-7-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 93 +++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index dfc8aa60d4345..c2f057aecb705 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,36 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct ccu_reset_data { u32 offset; u32 assert_mask; @@ -1177,6 +1207,57 @@ static const struct spacemit_ccu_data k1_ccu_apmu_da= ta =3D { .reset_num =3D ARRAY_SIZE(apmu_reset_data), }; =20 +static const struct ccu_reset_data rcpu_reset_data[] =3D { + [RESET_RCPU_SSP0] =3D RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_I2C0] =3D RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART1] =3D RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RESET_RCPU_IR] =3D RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RESET_RCPU_CAN] =3D RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART0] =3D RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_HDMI_AUDIO] =3D RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu_data =3D { + /* No clocks in the RCPU CCU */ + .reset_data =3D rcpu_reset_data, + .reset_num =3D ARRAY_SIZE(rcpu_reset_data), +}; + +static const struct ccu_reset_data rcpu2_reset_data[] =3D { + [RESET_RCPU2_PWM0] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM9] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu2_data =3D { + /* No clocks in the RCPU2 CCU */ + .reset_data =3D rcpu2_reset_data, + .reset_num =3D ARRAY_SIZE(rcpu2_reset_data), +}; + +static const struct ccu_reset_data apbc2_reset_data[] =3D { + [RESET_APBC2_UART1] =3D RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), + [RESET_APBC2_SSP2] =3D RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), + [RESET_APBC2_TWSI3] =3D RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), + [RESET_APBC2_RTC] =3D RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC2_TIMERS0] =3D RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC2_KPC] =3D RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), + [RESET_APBC2_GPIO] =3D RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), +}; + +static const struct spacemit_ccu_data k1_ccu_apbc2_data =3D { + /* No clocks in the APBC2 CCU */ + .reset_data =3D apbc2_reset_data, + .reset_num =3D ARRAY_SIZE(apbc2_reset_data), +}; + static int spacemit_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -1351,6 +1432,18 @@ static const struct of_device_id of_k1_ccu_match[] = =3D { .compatible =3D "spacemit,k1-syscon-apmu", .data =3D &k1_ccu_apmu_data, }, + { + .compatible =3D "spacemit,k1-syscon-rcpu", + .data =3D &k1_ccu_rcpu_data, + }, + { + .compatible =3D "spacemit,k1-syscon-rcpu2", + .data =3D &k1_ccu_rcpu2_data, + }, + { + .compatible =3D "spacemit,k1-syscon-apbc2", + .data =3D &k1_ccu_apbc2_data, + }, { } }; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:15 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 7/7] riscv: dts: spacemit: add reset support for the K1 SoC Date: Fri, 18 Apr 2025 09:53:59 -0500 Message-ID: <20250418145401.2603648-8-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 584f0dbc60f5b..491ab891788b8 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -346,6 +346,18 @@ soc { dma-noncoherent; ranges; =20 + syscon_rcpu: system-controller@c0880000 { + compatible =3D "spacemit,k1-syscon-rcpu"; + reg =3D <0x0 0xc0880000 0x0 0x2048>; + #reset-cells =3D <1>; + }; + + syscon_rcpu2: system-controller@c0888000 { + compatible =3D "spacemit,k1-syscon-rcpu2"; + reg =3D <0x0 0xc0888000 0x0 0x28>; + #reset-cells =3D <1>; + }; + syscon_apbc: system-control@d4015000 { compatible =3D "spacemit,k1-syscon-apbc"; reg =3D <0x0 0xd4015000 0x0 0x1000>; @@ -514,6 +526,12 @@ clint: timer@e4000000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; =20 + syscon_apbc2: system-controller@f0610000 { + compatible =3D "spacemit,k1-syscon-apbc2"; + reg =3D <0x0 0xf0610000 0x0 0x20>; + #reset-cells =3D <1>; + }; + sec_uart1: serial@f0612000 { compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; reg =3D <0x0 0xf0612000 0x0 0x100>; --=20 2.45.2