From nobody Sun Dec 14 12:34:09 2025 Received: from mta-65-225.siemens.flowmailer.net (mta-65-225.siemens.flowmailer.net [185.136.65.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8094269CF4 for ; Fri, 18 Apr 2025 07:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744962067; cv=none; b=UEW5Xte4zbaIb0tr8gO99EBJPijxLOKjr5hKKWbv1oE4jpm4KIRkBvNbW0OyCiiye5S9mX1xWQV5DBBM3LuSRQlJJNU2IM7XY1i9N1LLpgQ01xhwN4QhYzA2PeO3pATOyNkiHxkCVnxU0R01vOztXEBlz0tOU7YB66F4wV1W4zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744962067; c=relaxed/simple; bh=iJEcfFsiWJ1V9+dLXeuoWVpKyPfbNwN8bvVTcoioenc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GOOHXKVO+88sSI8FGyRMV/h0uzrOMuhLZC9Po+ZcoWEftq8PlD/1f6s+04R8DNlrBdDhLlawuMxLrAcrxTTXhlttHN1AeDlxoiBOHhZwoPFE+s9JK/uZ4ylgT2zMrbLDTgAeVuVJ4yr+YU6WRlH7niu4SWN/McVRa2AHrG79SgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b=MhmmKpvo; arc=none smtp.client-ip=185.136.65.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b="MhmmKpvo" Received: by mta-65-225.siemens.flowmailer.net with ESMTPSA id 2025041807305421ce0c7b4baf023998 for ; Fri, 18 Apr 2025 09:30:54 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=oH4biYNRIXbUPcZJxbqF385p1W7crfHf3KjlM5z89+Q=; b=MhmmKpvoP1mPw44HiJ3RiLjiBHPih8+nD719nw0Vzna9NCuV7EelAKVqIMbH+lNlFxORhA F8FQfuwx+0RLYO37/Ra8wUhhDiIMx9mpNeiLFlD2vc7MVpXCF5+yGYoV0AsRQE7C2Aaq1ZPN mFNr9UvXSxBBfUqWvVTewLklwni0K0z7WnnU+y+MrEdkcJcH0SkOl3+P0B2Vi3gw0Xn+qUv/ lqc3kS2IG/87OK3rO10HxXHWSPzR4xOkofnUjJLYHECLoJbgVA9UBeKkfthk24spiSKPYYWB Qv/Cujl+Dj93idJ186UvK4IxIYV0ChXQzfpKjybyPzU8dyDmy1i+vS3Q==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH v7 1/8] dt-bindings: soc: ti: Add AM65 peripheral virtualization unit Date: Fri, 18 Apr 2025 15:30:19 +0800 Message-Id: <20250418073026.2418728-2-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The PVU allows to define a limited set of mappings for incoming DMA requests to the system memory. It is not a real IOMMU, thus hooked up under the TI SoC bindings. Signed-off-by: Jan Kiszka Reviewed-by: Krzysztof Kozlowski Signed-off-by: Li Hua Qian --- .../bindings/soc/ti/ti,am654-pvu.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.y= aml diff --git a/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml b/D= ocumentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml new file mode 100644 index 000000000000..e4a5fc47d674 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) Siemens AG, 2024 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,am654-pvu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM654 Peripheral Virtualization Unit + +maintainers: + - Jan Kiszka + +properties: + compatible: + enum: + - ti,am654-pvu + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: tlbif + + interrupts: + items: + - description: fault interrupt + + interrupt-names: + items: + - const: pvu + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + iommu@30f80000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0x30f80000 0x1000>, + <0x36000000 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 390>; + interrupt-names =3D "pvu"; + }; --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E4771DF728 for ; Fri, 18 Apr 2025 07:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961468; cv=none; b=sXYUbDz+R1yGg0epTIW+znqRbtu/KKKUr2GUs8bW1jyQ25+Te5ibh3RbrjVKnXMxYCa3xxAe0jxu37AuxIYQNnCUq8N/Yj7Zke5xMN/yHmhOgFQa7sewBICgggzfG0fNwjzC+eMUoRZKapv3W7+80o7c6+bDcJ285aK3mOQ47dM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961468; c=relaxed/simple; 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Fri, 18 Apr 2025 09:31:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=81MJsMNbogkYe+Rx2MtdDb/7nc44T96h+II7KVTEBl0=; b=IsWipH/wzFhscWMIqwaXxolbV74wP/+NY7hss/R3C8wsYGt41Hiphe3S7tzd1EJ/pwe9jG GsTEZz5Mtv5Iv9mtDwJoxrj3OXcHZK7qq8eLaBaD0rXMOxS3PyberjS4K1ag2nG5uwkL3JhG 1VJGW/XUT3L/K+PFrZYvYxWbVMrGJypFBwO8z2Q3TIXm6c4y0vXxDGybeiqAlbmFBY3Yi4b2 ChcqgcTmdNbqqyWVOhoq7uG/ajQr95j8kHJzxg6q43ePGEp1Ndhk4I3vsdg1KdsfPOYe6PF2 DVzbZo0lapcKtHfs/OMQ5yQa8hpqz+fgrm/D9SDJPpGttz+6+c7yNLug==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH v7 2/8] dt-bindings: PCI: ti,am65: Extend for use with PVU Date: Fri, 18 Apr 2025 15:30:20 +0800 Message-Id: <20250418073026.2418728-3-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka Reviewed-by: Krzysztof Kozlowski Signed-off-by: Li Hua Qian --- .../bindings/pci/ti,am65-pci-host.yaml | 34 +++++++++++++++++-- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/= Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..7916325e0b39 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie =20 reg: - maxItems: 4 + minItems: 4 + maxItems: 6 =20 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp =20 interrupts: maxItems: 1 @@ -69,6 +73,15 @@ properties: items: pattern: '^pcie-phy[0-1]$' =20 + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + Note that enforcement via the PVU will only be available to + ti,am654-pcie-rc devices. + required: - compatible - reg @@ -89,6 +102,19 @@ then: - power-domains - msi-map - num-viewport + - memory-region + properties: + reg: + minItems: 6 + reg-names: + minItems: 6 +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 =20 unevaluatedProperties: false =20 @@ -104,8 +130,10 @@ examples: reg =3D <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp= "; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-64-226.siemens.flowmailer.net (mta-64-226.siemens.flowmailer.net [185.136.64.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B6121DE2BA for ; Fri, 18 Apr 2025 07:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961478; cv=none; b=QiTvWEz3DNhJCEbqr/AEYZ9unrYVAqFoR4ypiIiZfYpsEZlWYeT+A9A9VnMy+JurF9JwG7cwY+RLzU/b2f0hBf4W6ZIxj1cDZAdyF/qi05M0bJ8q7DWCFsc85aWA4q82bZQ8z/zAe2rkMAlS8htNkLc4GELu83dUdK9KB2nW/0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961478; c=relaxed/simple; bh=AyYu5kU2aIs78eLyElyU75ZfNPA4knURed0I3XNBo6U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mHOEwmDQVVKPceEHeo2dHURy/xuApzIEudsrOo3xWxUb/sApo24OLfM5fCbCpkMW5JvJC28QI17OskZHP62e3MvM0osoTPBASYytLhudA3oYuMcc7jBv3C4kCfQGsD4ao5Ea1PP7ABi8YhbmCXYdFpx6HVpzUjs9cGNwqGVWRWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b=dH9tpzxj; arc=none smtp.client-ip=185.136.64.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b="dH9tpzxj" Received: by mta-64-226.siemens.flowmailer.net with ESMTPSA id 20250418073113b6e6126760a090b758 for ; Fri, 18 Apr 2025 09:31:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=7KKlKsyWBMFhvLQRuvSvZsxl+EKLaAI+mZf9xSsCBzo=; b=dH9tpzxj4crpEDkOxl0ApZi/lu41+IfFbU4QOsPyhwa1KJkvZfLHXLrBXDqcrnopf3WXSH QNlDZ4BkRP9P2HcwwFN7KdfqQWfYGelc3v9hiW2zzL4eI/bM7yrE4GCEIFamtI+DcoXdK95+ d6QOviNAdSniOeGpuODXLXnJ16CQXKWaDT3pJTWjkTXjk46Lo9F/qym8Pflvc2X/R2qIAhH/ 7U7OpzdJ7CijY3Lg90mOvPa1H8R2+K9D5MtYV4qB3p0EAdvUDdDU+oceJ6M4ckFxCmRgG6mq fAaoDG0TJGJJnL7U87IvOm+IWyDDc/GsdS2Kys2JBHS/C7zd8UXOdBkA==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 3/8] soc: ti: Add IOMMU-like PVU driver Date: Fri, 18 Apr 2025 15:30:21 +0800 Message-Id: <20250418073026.2418728-4-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The TI Peripheral Virtualization Unit (PVU) permits to define a limited set of mappings for DMA requests on the system memory. Unlike with an IOMMU, there is no fallback to a memory-backed page table, only a fixed set of register-backed TLBs. Emulating an IOMMU behavior appears to be the more fragile the more fragmentation of pending requests occur. Therefore, this driver does not expose the PVU as an IOMMU. It rather introduces a simple, static interface to devices that are under restricted-dma-pool constraints. They can register their pools with the PVUs, enabling only those pools to work for DMA. As also MSI is issued as DMA, the PVU already register the related translator region of the AM654 as valid DMA target. This driver is the essential building block for limiting DMA from untrusted devices to clearly defined memory regions in the absence of a real IOMMU (SMMU). Co-developed-by: Diogo Ivo Signed-off-by: Diogo Ivo Signed-off-by: Jan Kiszka Signed-off-by: Li Hua Qian --- drivers/soc/ti/Kconfig | 4 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/ti-pvu.c | 500 ++++++++++++++++++++++++++++++++++++++++ include/linux/ti-pvu.h | 32 +++ 4 files changed, 537 insertions(+) create mode 100644 drivers/soc/ti/ti-pvu.c create mode 100644 include/linux/ti-pvu.h diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 1a93001c9e36..af7173ad84de 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -82,6 +82,10 @@ config TI_PRUSS processors on various TI SoCs. It's safe to say N here if you're not interested in the PRU or if you are unsure. =20 +config TI_PVU + bool "TI Peripheral Virtualization Unit driver" + depends on ARCH_K3 && DMA_RESTRICTED_POOL + endif # SOC_TI =20 config TI_SCI_INTA_MSI_DOMAIN diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index cb800a745e66..ecff3fd8c433 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TI_K3_RINGACC) +=3D k3-ringacc.o obj-$(CONFIG_TI_K3_SOCINFO) +=3D k3-socinfo.o obj-$(CONFIG_TI_PRUSS) +=3D pruss.o obj-$(CONFIG_POWER_AVS_OMAP) +=3D smartreflex.o +obj-$(CONFIG_TI_PVU) +=3D ti-pvu.o diff --git a/drivers/soc/ti/ti-pvu.c b/drivers/soc/ti/ti-pvu.c new file mode 100644 index 000000000000..38996c74cce7 --- /dev/null +++ b/drivers/soc/ti/ti-pvu.c @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#include +#include +#include +#include +#include +#include + +#define PVU_CONFIG 0x4 +#define PVU_ENABLE 0x10 +#define PVU_VIRTID_MAP1 0x14 +#define PVU_VIRTID_MAP2 0x18 +#define PVU_EXCEPTION_LOGGING_CONTROL 0x120 +#define PVU_EXCEPTION_LOGGING_HEADER0 0x124 +#define PVU_EXCEPTION_LOGGING_HEADER1 0x128 +#define PVU_EXCEPTION_LOGGING_DATA0 0x12c +#define PVU_EXCEPTION_LOGGING_DATA1 0x130 +#define PVU_EXCEPTION_LOGGING_DATA2 0x134 +#define PVU_EXCEPTION_LOGGING_DATA2_SECURE BIT(0) +#define PVU_EXCEPTION_LOGGING_DATA2_PRIV BIT(1) +#define PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE BIT(2) +#define PVU_EXCEPTION_LOGGING_DATA2_DEBUG BIT(3) +#define PVU_EXCEPTION_LOGGING_DATA2_READ BIT(4) +#define PVU_EXCEPTION_LOGGING_DATA2_WRITE BIT(5) +#define PVU_EXCEPTION_LOGGING_DATA3 0x138 +#define PVU_EXCEPTION_ENABLE_SET 0x148 +#define PVU_EOI_REG 0x150 + +#define PVU_CHAIN 0x0 +#define PVU_CHAIN_EN BIT(31) +#define PVU_CHAIN_LOG_DIS BIT(30) +#define PVU_CHAIN_FAULT BIT(29) +#define PVU_CHAIN_MASK 0xfff +#define PVU_ENTRY0 0x20 +#define PVU_ENTRY1 0x24 +#define PVU_ENTRY1_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY1_VBASE_H_MASK 0xffff +#define PVU_ENTRY2 0x28 +#define PVU_ENTRY2_RESERVED_MASK 0x1fd00080 +#define PVU_ENTRY2_INVALID (0U << 30) +#define PVU_ENTRY2_VALID (2U << 30) +#define PVU_ENTRY2_MODE_MASK 0xc0000000 +#define PVU_ENTRY2_PSIZE_SHIFT 16 +#define PVU_ENTRY2_PSIZE_MASK 0xf +#define PVU_ENTRY2_PERM_SX BIT(15) +#define PVU_ENTRY2_PERM_SW BIT(14) +#define PVU_ENTRY2_PERM_SR BIT(13) +#define PVU_ENTRY2_PERM_UX BIT(12) +#define PVU_ENTRY2_PERM_UW BIT(11) +#define PVU_ENTRY2_PERM_UR BIT(10) +#define PVU_ENTRY2_MEM_WRITETHROUGH (2 << 8) +#define PVU_ENTRY2_OUTER_SHARABLE BIT(4) +#define PVU_ENTRY2_IS_NOALLOC (0 << 2) +#define PVU_ENTRY2_OS_NOALLOC (0 << 0) +#define PVU_ENTRY4 0x30 +#define PVU_ENTRY5 0x34 +#define PVU_ENTRY5_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY5_PBASE_H_MASK 0xffff +#define PVU_ENTRY6 0x38 +#define PVU_ENTRY6_RESERVED_MASK 0xffffffe0 + +#define NUM_VIRTIDS 1 + +static const struct regmap_config pvu_cfg_regmap_cfg =3D { + .name =3D "pvu-cfg", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D PVU_EOI_REG, +}; + +enum pvu_cfg_regfields { + PVU_TLBS, + PVU_TLB_ENTRIES, + PVU_ENABLED, + PVU_DMA_CNT, + PVU_DMA_CL0, + PVU_DMA_CL1, + PVU_DMA_CL2, + PVU_DMA_CL3, + PVU_MAX_VIRTID, + PVU_EXC_SRC_ID, + PVU_EXC_CODE, + PVU_EXC_ADDR_L, + PVU_EXC_ADDR_H, + PVU_EXC_PRIV_ID, + PVU_EXC_PROPS, + PVU_EXC_ROUTE_ID, + PVU_EXC_BYTE_CNT, + PVU_EXC_ENABLE, + PVU_EOI, + PVU_MAX_CFG_FIELDS, +}; + +static const struct reg_field pvu_cfg_reg_fields[] =3D { + [PVU_TLBS] =3D REG_FIELD(PVU_CONFIG, 0, 15), + [PVU_TLB_ENTRIES] =3D REG_FIELD(PVU_CONFIG, 16, 23), + [PVU_ENABLED] =3D REG_FIELD(PVU_ENABLE, 0, 0), + [PVU_DMA_CNT] =3D REG_FIELD(PVU_VIRTID_MAP1, 0, 11), + [PVU_DMA_CL0] =3D REG_FIELD(PVU_VIRTID_MAP1, 16, 17), + [PVU_DMA_CL1] =3D REG_FIELD(PVU_VIRTID_MAP1, 18, 19), + [PVU_DMA_CL2] =3D REG_FIELD(PVU_VIRTID_MAP1, 20, 21), + [PVU_DMA_CL3] =3D REG_FIELD(PVU_VIRTID_MAP1, 22, 23), + [PVU_MAX_VIRTID] =3D REG_FIELD(PVU_VIRTID_MAP2, 0, 11), + [PVU_EXC_SRC_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER0, 8, 23), + [PVU_EXC_CODE] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER1, 16, 23), + [PVU_EXC_ADDR_L] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA0, 0, 31), + [PVU_EXC_ADDR_H] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA1, 0, 15), + [PVU_EXC_PRIV_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 0, 7), + [PVU_EXC_PROPS] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 8, 13), + [PVU_EXC_ROUTE_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 16, 27), + [PVU_EXC_BYTE_CNT] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA3, 0, 9), + [PVU_EXC_ENABLE] =3D REG_FIELD(PVU_EXCEPTION_ENABLE_SET, 0, 0), + [PVU_EOI] =3D REG_FIELD(PVU_EOI_REG, 0, 15), +}; + +struct ti_pvu { + struct list_head entry; + struct platform_device *pdev; + struct regmap *cfg; + struct regmap_field *cfg_fields[PVU_MAX_CFG_FIELDS]; + void __iomem *tlbif_base; + unsigned int num_tlbs; + unsigned int num_entries; +}; + +static const char *pvu_excp_code_string[] =3D { + "PVU miss", + "maximum VirtID violation", + "", + "read permission violation", + "write permission violation", + "execute permission violation", + "prefetch permission violation", + "", +}; + +static const u64 pvu_page_size[] =3D { + 4 * 1024ULL, + 16 * 1024ULL, + 64 * 1024ULL, + 2 * 1024 * 1024ULL, + 32 * 1024 * 1024ULL, + 512 * 1024 * 1024ULL, + 1 * 1024 * 1024 * 1024ULL, + 16 * 1024 * 1024 * 1024ULL +}; + +static DEFINE_MUTEX(ti_pvu_lock); +static LIST_HEAD(ti_pvu_list); + +static unsigned int pvu_field_read(struct ti_pvu *pvu, enum pvu_cfg_regfie= lds f) +{ + int ret; + unsigned int val; + + ret =3D regmap_field_read(pvu->cfg_fields[f], &val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to read field\n"); + + return val; +} + +static void pvu_field_write(struct ti_pvu *pvu, enum pvu_cfg_regfields f, + unsigned int val) +{ + int ret; + + ret =3D regmap_field_write(pvu->cfg_fields[f], val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to write field\n"); +} + +static irqreturn_t pvu_fault_isr(int irq, void *dev_id) +{ + u32 code, bytes, route_id, priv_id, props; + struct ti_pvu *pvu =3D dev_id; + const char *code_str; + u64 address; + + code =3D pvu_field_read(pvu, PVU_EXC_CODE); + code_str =3D pvu_excp_code_string[ + min(code, (u32)ARRAY_SIZE(pvu_excp_code_string) - 1)]; + + dev_err(&pvu->pdev->dev, "fault detected, code %d (%s)\n", + code, code_str); + + address =3D pvu_field_read(pvu, PVU_EXC_ADDR_L); + address |=3D (u64)pvu_field_read(pvu, PVU_EXC_ADDR_H) << 32; + + bytes =3D pvu_field_read(pvu, PVU_EXC_BYTE_CNT); + + route_id =3D pvu_field_read(pvu, PVU_EXC_ROUTE_ID); + priv_id =3D pvu_field_read(pvu, PVU_EXC_PRIV_ID); + props =3D pvu_field_read(pvu, PVU_EXC_PROPS); + + dev_err(&pvu->pdev->dev, + " address 0x%016llx size %d route-ID %d priv-ID %d flags %c%c%c%c%c%c\n= ", + address, bytes, route_id, priv_id, + (props & PVU_EXCEPTION_LOGGING_DATA2_WRITE) ? 'W' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_READ) ? 'R' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_DEBUG) ? 'D' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE) ? 'C' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_PRIV) ? 'P' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_SECURE) ? 'S' : '-'); + + pvu_field_write(pvu, PVU_EOI, 0); + + return IRQ_HANDLED; +} + +static void __iomem *pvu_get_entry_base(struct ti_pvu *pvu, unsigned int e= ntry) +{ + return pvu->tlbif_base + (entry / pvu->num_entries) * 0x1000 + + (entry % pvu->num_entries) * 0x20; +} + +static int pvu_get_free_entry(struct ti_pvu *pvu) +{ + unsigned int n; + u32 val; + + /* We use up to 2 TLBs via chainging */ + for (n =3D 0; n < pvu->num_entries * 2; n++) { + val =3D readl(pvu_get_entry_base(pvu, n) + PVU_ENTRY2); + if ((val & PVU_ENTRY2_MODE_MASK) =3D=3D PVU_ENTRY2_INVALID) + return n; + } + return -ENOSPC; +} + +static void pvu_write_entry(struct ti_pvu *pvu, unsigned int entry, + u64 addr, u32 psize) +{ + void __iomem *entry_base =3D pvu_get_entry_base(pvu, entry); + u32 val; + + writel((u32)addr, entry_base + PVU_ENTRY0); + + val =3D readl(entry_base + PVU_ENTRY1); + val &=3D PVU_ENTRY1_RESERVED_MASK; + val |=3D (addr >> 32) & PVU_ENTRY1_VBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY1); + + writel((u32)addr, entry_base + PVU_ENTRY4); + + val =3D readl(entry_base + PVU_ENTRY5); + val &=3D PVU_ENTRY5_RESERVED_MASK; + val |=3D (addr >> 32) & PVU_ENTRY5_PBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY5); + + val =3D readl(entry_base + PVU_ENTRY6); + val &=3D PVU_ENTRY6_RESERVED_MASK; + writel(val, entry_base + PVU_ENTRY6); + + val =3D readl(entry_base + PVU_ENTRY2); + val &=3D PVU_ENTRY2_RESERVED_MASK; + val |=3D psize << PVU_ENTRY2_PSIZE_SHIFT; + val |=3D PVU_ENTRY2_VALID | + PVU_ENTRY2_PERM_UR | PVU_ENTRY2_PERM_SR | + PVU_ENTRY2_PERM_UW | PVU_ENTRY2_PERM_SW | + PVU_ENTRY2_PERM_UX | PVU_ENTRY2_PERM_SX | + PVU_ENTRY2_MEM_WRITETHROUGH | PVU_ENTRY2_OUTER_SHARABLE | + PVU_ENTRY2_IS_NOALLOC | PVU_ENTRY2_OS_NOALLOC; + writel(val, entry_base + PVU_ENTRY2); +} + +static int pvu_create_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + u64 page_size; + int psize; + int entry; + + while (size > 0) { + entry =3D pvu_get_free_entry(pvu); + if (entry < 0) { + dev_err(&pvu->pdev->dev, "ran out of TLB entries\n"); + return -ENOSPC; + } + + for (psize =3D ARRAY_SIZE(pvu_page_size) - 1; psize >=3D 0; psize--) { + page_size =3D pvu_page_size[psize]; + if (size >=3D page_size && (addr & (page_size - 1)) =3D=3D 0) + break; + } + if (psize < 0) { + dev_err(&pvu->pdev->dev, "unaligned region provided\n"); + return -EINVAL; + } + + pvu_write_entry(pvu, entry, addr, psize); + dev_info(&pvu->pdev->dev, + "created TLB entry %d.%d: 0x%08llx, psize %d (0x%08llx)\n", + entry / pvu->num_entries, entry % pvu->num_entries, + addr, psize, page_size); + + size -=3D page_size; + addr +=3D page_size; + } + + return 0; +} + +static void pvu_remove_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + void __iomem *entry_base; + unsigned int n, psize; + u64 entry_addr; + u32 entry2; + + for (n =3D 0; n < pvu->num_entries * 2; n++) { + entry_base =3D pvu_get_entry_base(pvu, n); + entry2 =3D readl(entry_base + PVU_ENTRY2); + if ((entry2 & PVU_ENTRY2_MODE_MASK) !=3D PVU_ENTRY2_VALID) + continue; + + entry_addr =3D readl(entry_base + PVU_ENTRY0); + entry_addr |=3D (u64)(readl(entry_base + PVU_ENTRY1) & + PVU_ENTRY1_VBASE_H_MASK) << 32; + + psize =3D (entry2 >> PVU_ENTRY2_PSIZE_SHIFT) & + PVU_ENTRY2_PSIZE_MASK; + if (psize >=3D ARRAY_SIZE(pvu_page_size)) + continue; + + if (entry_addr >=3D addr && + (entry_addr + pvu_page_size[psize]) <=3D (addr + size)) { + entry2 &=3D ~PVU_ENTRY2_MODE_MASK; + entry2 |=3D PVU_ENTRY2_INVALID; + writel(entry2, entry_base + PVU_ENTRY2); + + dev_info(&pvu->pdev->dev, "removed TLB entry %d.%d\n", + n / pvu->num_entries, n % pvu->num_entries); + } + } +} + +int ti_pvu_create_region(unsigned int virt_id, const struct resource *regi= on) +{ + struct ti_pvu *pvu; + int err =3D 0; + + if (virt_id >=3D NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + err =3D pvu_create_region(pvu, region->start, + region->end + 1 - region->start); + if (err) + break; + } + + mutex_unlock(&ti_pvu_lock); + + return err; +} + +int ti_pvu_remove_region(unsigned int virt_id, const struct resource *regi= on) +{ + struct ti_pvu *pvu; + + if (virt_id >=3D NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + pvu_remove_region(pvu, region->start, + region->end + 1 - region->start); + } + + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static int ti_pvu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *its_node; + void __iomem *base; + struct ti_pvu *pvu; + u32 val; + int ret; + + pvu =3D devm_kzalloc(dev, sizeof(*pvu), GFP_KERNEL); + if (!pvu) + return -ENOMEM; + + pvu->pdev =3D pdev; + + base =3D devm_platform_ioremap_resource_byname(pdev, "cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + + pvu->cfg =3D devm_regmap_init_mmio(dev, base, &pvu_cfg_regmap_cfg); + if (IS_ERR(pvu->cfg)) + return dev_err_probe(dev, PTR_ERR(pvu->cfg), "failed to init cfg regmap"= ); + + ret =3D devm_regmap_field_bulk_alloc(dev, pvu->cfg, pvu->cfg_fields, + pvu_cfg_reg_fields, PVU_MAX_CFG_FIELDS); + if (ret) + return dev_err_probe(dev, ret, "failed to alloc cfg regmap fields"); + + pvu->num_tlbs =3D pvu_field_read(pvu, PVU_TLBS); + pvu->num_entries =3D pvu_field_read(pvu, PVU_TLB_ENTRIES); + dev_info(dev, "TLBs: %d, entries per TLB: %d\n", pvu->num_tlbs, + pvu->num_entries); + + pvu->tlbif_base =3D devm_platform_ioremap_resource_byname(pdev, "tlbif"); + if (IS_ERR(pvu->tlbif_base)) + return PTR_ERR(pvu->tlbif_base); + + its_node =3D of_find_compatible_node(0, 0, "arm,gic-v3-its"); + if (its_node) { + u32 pre_its_window[2]; + + ret =3D of_property_read_u32_array(its_node, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window)); + if (ret) { + dev_err(dev, "failed to read pre-its property\n"); + return ret; + } + + ret =3D pvu_create_region(pvu, pre_its_window[0], + pre_its_window[1]); + if (ret) + return ret; + } + + /* Enable the first two TLBs, chaining from 0 to 1 */ + val =3D readl(pvu->tlbif_base + PVU_CHAIN); + val |=3D PVU_CHAIN_EN | 1; + writel(val, pvu->tlbif_base + PVU_CHAIN); + + val =3D readl(pvu->tlbif_base + PVU_CHAIN + 0x1000); + val |=3D PVU_CHAIN_EN; + writel(val, pvu->tlbif_base + PVU_CHAIN + 0x1000); + + pvu_field_write(pvu, PVU_DMA_CNT, 0); + pvu_field_write(pvu, PVU_DMA_CL0, 0); + pvu_field_write(pvu, PVU_DMA_CL1, 0); + pvu_field_write(pvu, PVU_DMA_CL2, 0); + pvu_field_write(pvu, PVU_DMA_CL3, 0); + pvu_field_write(pvu, PVU_MAX_VIRTID, NUM_VIRTIDS); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get irq\n"); + + ret =3D devm_request_irq(dev, ret, pvu_fault_isr, 0, dev_name(dev), pvu); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + pvu_field_write(pvu, PVU_EXC_ENABLE, 1); + pvu_field_write(pvu, PVU_ENABLED, 1); + + dev_set_drvdata(dev, pvu); + + mutex_lock(&ti_pvu_lock); + list_add(&pvu->entry, &ti_pvu_list); + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static void ti_pvu_remove(struct platform_device *pdev) +{ + struct ti_pvu *pvu =3D dev_get_drvdata(&pdev->dev); + + mutex_lock(&ti_pvu_lock); + list_del(&pvu->entry); + mutex_unlock(&ti_pvu_lock); +} + +static const struct of_device_id ti_pvu_of_match[] =3D { + { .compatible =3D "ti,am654-pvu", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ti_pvu_of_match); + +static struct platform_driver ti_pvu_driver =3D { + .driver =3D { + .name =3D "ti-pvu", + .of_match_table =3D ti_pvu_of_match, + }, + .probe =3D ti_pvu_probe, + .remove =3D ti_pvu_remove, +}; +module_platform_driver(ti_pvu_driver); diff --git a/include/linux/ti-pvu.h b/include/linux/ti-pvu.h new file mode 100644 index 000000000000..7088da8dad9a --- /dev/null +++ b/include/linux/ti-pvu.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#ifndef _LINUX_TI_PVU_H +#define _LINUX_TI_PVU_H + +#include + +#if IS_ENABLED(CONFIG_TI_PVU) +int ti_pvu_create_region(unsigned int virt_id, + const struct resource *region); +int ti_pvu_remove_region(unsigned int virt_id, + const struct resource *region); +#else +static inline int ti_pvu_create_region(unsigned int virt_id, + const struct resource *region) +{ + return 0; +} + +static inline int ti_pvu_remove_region(unsigned int virt_id, + const struct resource *region) +{ + return 0; +} +#endif + +#endif /* _LINUX_TI_PVU_H */ --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86132698BF for ; Fri, 18 Apr 2025 07:31:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961486; cv=none; b=RjNpSd8tIgjmpmAx4h9n+R7CB6BdZ3Cfg6r8/seJUzzqUrnLuWUyjDxwMthbMKKH92OnT6Vgq3L7G1f52+p+dr/1COxeJ6XFzaytDNq0FWx+5Nqhu3gtDP1EncpZWBOxAlmBzXFoSNGecQuRt+jXM6Zky8UrR4zzqLJJxHYPVi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961486; c=relaxed/simple; bh=2cGP1WDTDxQg94xFUUjsdxt82RySxGXJfxiIITkq/UM=; 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Fri, 18 Apr 2025 09:31:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=ALx3OwONbiKV86DkkxNexBFSZ9zvI3K6YFsdRD8NtRk=; b=FGR5STVpHPnc737lEOHV92SGfESAT3wC999XDSSTRxtJoJfvwUOXmmWGfwDzNDQjWq9GTr BsRdrs4u7vOxmFEJ0fVbsVFds4XqCbr5bC7binOncA+IGZxamh/0hKIWvqr3ge5LN8xqOzZ+ Jv2nT8Q+19YS7mlmKdt+lxn0aB4lKUK2aq6lXhDdyEETFhE61KIL93FwV9AB+B39Zolu2rMD LX4x86telj8rRvbyIRTiU/9e3lMbYmWF2jrK6eXHVA+YRfJq0SSfNPZQp+qCbdJPO5+fTM5C f/c7Rrd3k+5ECYEB2QZsbSNGDj7e3qgBOdGvEkFSyLq28jd7l3LlzaJA==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 4/8] PCI: keystone: Add support for PVU-based DMA isolation on AM654 Date: Fri, 18 Apr 2025 15:30:22 +0800 Message-Id: <20250418073026.2418728-5-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The AM654 lacks an IOMMU, thus does not support isolating DMA requests from untrusted PCI devices to selected memory regions this way. Use static PVU-based protection instead. The PVU, when enabled, will only accept DMA requests that address previously configured regions. Use the availability of a restricted-dma-pool memory region as trigger and register it as valid DMA target with the PVU. In addition, enable the mapping of requester IDs to VirtIDs in the PCI RC. Use only a single VirtID so far, catching all devices. This may be extended later on. Signed-off-by: Jan Kiszka Acked-by: Bjorn Helgaas Signed-off-by: Li Hua Qian --- drivers/pci/controller/dwc/pci-keystone.c | 106 ++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index 76a37368ae4f..30aaaf28d6a4 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include =20 #include "../../pci.h" #include "pcie-designware.h" @@ -111,6 +113,16 @@ =20 #define PCI_DEVICE_ID_TI_AM654X 0xb00c =20 +#define KS_PCI_VIRTID 0 + +#define PCIE_VMAP_xP_CTRL 0x0 +#define PCIE_VMAP_xP_REQID 0x4 +#define PCIE_VMAP_xP_VIRTID 0x8 + +#define PCIE_VMAP_xP_CTRL_EN BIT(0) + +#define PCIE_VMAP_xP_VIRTID_VID_MASK 0xfff + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -1137,6 +1149,94 @@ static const struct of_device_id ks_pcie_of_match[] = =3D { { }, }; =20 +static int ks_init_vmap(struct platform_device *pdev, const char *vmap_nam= e) +{ + struct resource *res; + void __iomem *base; + u32 val; + + if (!IS_ENABLED(CONFIG_TI_PVU)) + return 0; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, vmap_name); + base =3D devm_pci_remap_cfg_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + writel(0, base + PCIE_VMAP_xP_REQID); + + val =3D readl(base + PCIE_VMAP_xP_VIRTID); + val &=3D ~PCIE_VMAP_xP_VIRTID_VID_MASK; + val |=3D KS_PCI_VIRTID; + writel(val, base + PCIE_VMAP_xP_VIRTID); + + val =3D readl(base + PCIE_VMAP_xP_CTRL); + val |=3D PCIE_VMAP_xP_CTRL_EN; + writel(val, base + PCIE_VMAP_xP_CTRL); + + return 0; +} + +static int ks_init_restricted_dma(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct of_phandle_iterator it; + struct resource phys; + int err; + + if (!IS_ENABLED(CONFIG_TI_PVU)) + return 0; + + /* Only process the first restricted DMA pool, more are not allowed */ + of_for_each_phandle(&it, err, dev->of_node, "memory-region", + NULL, 0) { + if (of_device_is_compatible(it.node, "restricted-dma-pool")) + break; + } + if (err) + return err =3D=3D -ENOENT ? 0 : err; + + err =3D of_address_to_resource(it.node, 0, &phys); + if (err < 0) { + dev_err(dev, "failed to parse memory region %pOF: %d\n", + it.node, err); + return 0; + } + + /* Map all incoming requests on low and high prio port to virtID 0 */ + err =3D ks_init_vmap(pdev, "vmap_lp"); + if (err) + return err; + err =3D ks_init_vmap(pdev, "vmap_hp"); + if (err) + return err; + + /* + * Enforce DMA pool usage with the help of the PVU. + * Any request outside will be dropped and raise an error at the PVU. + */ + return ti_pvu_create_region(KS_PCI_VIRTID, &phys); +} + +static void ks_release_restricted_dma(struct platform_device *pdev) +{ + struct of_phandle_iterator it; + struct resource phys; + int err; + + if (!IS_ENABLED(CONFIG_TI_PVU)) + return; + + of_for_each_phandle(&it, err, pdev->dev.of_node, "memory-region", + NULL, 0) { + if (of_device_is_compatible(it.node, "restricted-dma-pool") && + of_address_to_resource(it.node, 0, &phys) =3D=3D 0) { + ti_pvu_remove_region(KS_PCI_VIRTID, &phys); + break; + } + } +} + static int ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; @@ -1285,6 +1385,10 @@ static int ks_pcie_probe(struct platform_device *pde= v) if (ret < 0) goto err_get_sync; =20 + ret =3D ks_init_restricted_dma(pdev); + if (ret < 0) + goto err_get_sync; + switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { @@ -1366,6 +1470,8 @@ static void ks_pcie_remove(struct platform_device *pd= ev) int num_lanes =3D ks_pcie->num_lanes; struct device *dev =3D &pdev->dev; =20 + ks_release_restricted_dma(pdev); + pm_runtime_put(dev); pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-64-228.siemens.flowmailer.net (mta-64-228.siemens.flowmailer.net [185.136.64.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB3326A0F3 for ; Fri, 18 Apr 2025 07:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 5/8] arm64: dts: ti: k3-am65-main: Add PVU nodes Date: Fri, 18 Apr 2025 15:30:23 +0800 Message-Id: <20250418073026.2418728-6-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Add nodes for the two PVUs of the AM65. Keep them disabled, though, because the board has to additionally define DMA pools and the devices to be isolated. Signed-off-by: Jan Kiszka Signed-off-by: Li Hua Qian --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 94a812a1355b..977c66a3a7c7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -841,6 +841,26 @@ main_cpts_mux: refclk-mux { assigned-clock-parents =3D <&k3_clks 118 5>; }; }; + + ti_pvu0: iommu@30f80000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0 0x30f80000 0 0x1000>, + <0 0x36000000 0 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 390>; + interrupt-names =3D "pvu"; + status =3D "disabled"; + }; + + ti_pvu1: iommu@30f81000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0 0x30f81000 0 0x1000>, + <0 0x36100000 0 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 389>; + interrupt-names =3D "pvu"; + status =3D "disabled"; + }; }; =20 main_gpio0: gpio@600000 { --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00A4126A1C2 for ; Fri, 18 Apr 2025 07:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961505; cv=none; b=Z1gOUuz5av/kcSBY2hNnA1rEvGoW4iFSXupI+OkJDPH36Br9U+tS3tdZ3rze8P5JiMXCewRgnKLOYLDX5OB3lRgUw8WxWvErURNwUIQgHKy+YN8//IGfOHSTLVTPxD7DWYVG+2oJqSSCbfPqmWuEAsJxjBgp0r3dTlsdf03aDVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961505; c=relaxed/simple; bh=5mBkSocatgO9jSyNhYC0BuhTkviGB1V5hfeJAbpimJI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rJimL0UsyqZzxvQxyfqux0yXIIvtoFX1fqBWd8CwI9veR0Ubq51aPxaPNc0W9sOl/JvLXv/leunUfncB+lxloje7mNxV1V441UnpLVKOjXOdLbDahjUWh9ivIGRK97fRzMkdqcWyhsfEn88M/cXTKMto/oocBhUPhzrgvy9CbS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b=EgKnHAJT; arc=none smtp.client-ip=185.136.64.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b="EgKnHAJT" Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 202504180731406e8b97949c727205ba for ; Fri, 18 Apr 2025 09:31:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=XNsdU6/xpqG6iIOFThnIblqGVb0yhpa5hT7U9NLK9MM=; b=EgKnHAJT7LhBb8ssRvPWElxrDBpgCeeZ7TssiXmo+l6X6iESVoDPncWJKgTH9uXgrdIyOC 3zR5uxoVOdTHjKoNvfFgDIUvmky6MA7ea+7iEy0Xe2QguqzHnV7+br/UyrxpAyoL3vvsnmeG Wrd0YsIJZAz5lVyMhsj7QbPZYOV1oUQmw+XWWc5LL5bYBp9ZTnKv+FRV/dQUnzIt7c32k2Ca U77mQH9cNHe/Lq8Xh3Fj+7c+3R570AciemaNlXkmX4Kth33P7MUsnPrk/ci+3dbISQoMwHP8 Ui2zGmRZkXS5Wa3/NEkIfWh3baOtJ+QxJdnqDzJlR7Ki+DAHupi+44uQ==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 6/8] arm64: dts: ti: k3-am65-main: Add VMAP registers to PCI root complexes Date: Fri, 18 Apr 2025 15:30:24 +0800 Message-Id: <20250418073026.2418728-7-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Rewrap the long lines at this chance. Signed-off-by: Jan Kiszka Signed-off-by: Li Hua Qian --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 977c66a3a7c7..e816c03569ff 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -895,8 +895,13 @@ main_gpio1: gpio@601000 { =20 pcie0_rc: pcie@5500000 { compatible =3D "ti,am654-pcie-rc"; - reg =3D <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x1= 0000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + reg =3D <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x2000>, + <0x0 0x5506000 0x0 0x1000>, + <0x0 0x2900000 0x0 0x1000>, + <0x0 0x2908000 0x0 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 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From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 7/8] arm64: dts: ti: iot2050: Add overlay for DMA isolation for devices behind PCI RC Date: Fri, 18 Apr 2025 15:30:25 +0800 Message-Id: <20250418073026.2418728-8-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Reserve a 64M memory region and ensure that all PCI devices do their DMA only inside that region. This is configured via a restricted-dma-pool and enforced with the help of the first PVU. Applying this isolation is not totally free in terms of overhead and memory consumption. It makes only sense for variants that support secure booting, and generally only when this is actually enable. Therefore model it as overlay that can be activated on demand. The firmware will take care of this via DT fixup during boot and will also provide a way to adjust the pool size. Signed-off-by: Jan Kiszka Signed-off-by: Li Hua Qian --- arch/arm64/boot/dts/ti/Makefile | 5 +++ ...am6548-iot2050-advanced-dma-isolation.dtso | 33 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-i= solation.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 03d4cecfc001..12c2cee955f2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -73,8 +73,10 @@ k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb \ k3-am654-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-icssg2.dtbo k3-am654-idk-dtbs :=3D k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-us= b2.dtbo k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-dtbs :=3D k3-am6548-iot2050-a= dvanced-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo k3-am6548-iot2050-advanced-m2-bkey-usb3-dtbs :=3D k3-am6548-iot2050-advanc= ed-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic-pg2.dtb @@ -261,7 +263,10 @@ DTC_FLAGS_k3-am62p5-sk +=3D -@ DTC_FLAGS_k3-am642-evm +=3D -@ DTC_FLAGS_k3-am642-phyboard-electra-rdk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-pg2 +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-sm +=3D -@ DTC_FLAGS_k3-am68-sk-base-board +=3D -@ DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j7200-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolatio= n.dtso b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dt= so new file mode 100644 index 000000000000..dfd75d2dc245 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050, overlay for isolating DMA requests via PVU + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + */ + +/dts-v1/; +/plugin/; + +&{/reserved-memory} { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pci_restricted_dma_region: restricted-dma@c0000000 { + compatible =3D "restricted-dma-pool"; + reg =3D <0 0xc0000000 0 0x4000000>; + }; +}; + +&pcie0_rc { + memory-region =3D <&pci_restricted_dma_region>; +}; + +&pcie1_rc { + memory-region =3D <&pci_restricted_dma_region>; +}; + +&ti_pvu0 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Sun Dec 14 12:34:09 2025 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663F326A0AB for ; Fri, 18 Apr 2025 07:32:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744961522; cv=none; b=KLx57O6MoLHoSmrjp5fiiCFgDQ+w13g0QY7bRU6eYZX/u7+iMKuMO9rGTem3MI/4X4qThSexyxEdklwCsr65UVkC4K7t/5jkiHDfKaERIX0yb1RpwG8GrlWLMB4siSNL5IU7J/KjZeQO+P7DE2zfLcj5hLObhtxyUr1eAyN5ssI= ARC-Message-Signature: i=1; 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Fri, 18 Apr 2025 09:31:58 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=nt46wyX3vInf9nEJO3STUSubJKhNa7Mq0IAjgmyGm+I=; b=ew0/N7SV8ocpPGEhZTz/xQ+DyeZbuMX14POxCPjdsGVFWNSMS5S1mPfkMH7o7gJKLlwyY/ pCvAEvD3KsHwOU59DVCIcMKh169q3voszK33WG4F50eYslAn71Ysc+19mNiaTuYCLlHgaeNT 1JF3popdz30s9xnL7PFitb8uNE3CUTgUBY9DOa9pX0eSzAa3jZpbaqDfPJUdiwUzedHiqz2U a5RdyNEKx/yvTrDixV27oUAiLeXHaMxOxg+KMqW55TVYD4A8jNV8nu5FuJug6KIPfH86NzUI xVBSPIHs2Xj34+25AhFfWpvYf21V4Kue+T/64+g/fCusrFI+EvBvOWMg==; From: huaqian.li@siemens.com To: helgaas@kernel.org, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, s-vadapalli@ti.com, ssantosh@kernel.org, vigneshr@ti.com, iommu@lists.linux.dev Subject: [PATCH v7 8/8] swiotlb: Make IO_TLB_SEGSIZE configurable Date: Fri, 18 Apr 2025 15:30:26 +0800 Message-Id: <20250418073026.2418728-9-huaqian.li@siemens.com> In-Reply-To: <20250418073026.2418728-1-huaqian.li@siemens.com> References: <20241030205703.GA1219329@bhelgaas> <20250418073026.2418728-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Li Hua Qian In some applications, the default value of 128 is not sufficient for memory allocation and can cause runtime errors. This change makes IO_TLB_SEGSIZE configurable, allowing it to be increased if needed. Signed-off-by: Li Hua Qian --- include/linux/swiotlb.h | 2 +- kernel/dma/Kconfig | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h index 3dae0f592063..145c71f8329d 100644 --- a/include/linux/swiotlb.h +++ b/include/linux/swiotlb.h @@ -23,7 +23,7 @@ struct scatterlist; * must be a power of 2. What is the appropriate value ? * The complexity of {map,unmap}_single is linearly dependent on this valu= e. */ -#define IO_TLB_SEGSIZE 128 +#define IO_TLB_SEGSIZE CONFIG_SWIOTLB_SEGSIZE =20 /* * log of the size of each IO TLB slab. The number of slabs is command li= ne diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 31cfdb6b4bc3..38bfa84b96b6 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -102,6 +102,13 @@ config SWIOTLB_DYNAMIC =20 If unsure, say N. =20 +config SWIOTLB_SEGSIZE + int "SWIOTLB segment size" + default 128 + help + Set the maximum allowable number of contiguous slabs to map. + Must be a power of 2. + config DMA_BOUNCE_UNALIGNED_KMALLOC bool depends on SWIOTLB --=20 2.34.1