From nobody Sun Dec 14 12:18:13 2025 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AED9425E806; Fri, 18 Apr 2025 01:49:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744940973; cv=none; b=rrIz5cnvYRElhI+5Buq0FExWV5yMk2MqjLJG+RC1REhxwD3wdw+BpyPO6jRrg/W5h6zrEz6STi6gCUGtkgSFdGhslgaGQKYROYVVZq7k9YG/hEBREw2lqIaZd1fF+LSOtaCcIiH6lMICBcwVGAiI/3nCvi4edEto1pR97QV8Q9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744940973; c=relaxed/simple; bh=/8a5mLEI5UEQSmLbE8liiHB9ztaIjPYAXnVs77qlR18=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=asioKxvXIm0RUc4yTifpqX7sSQqS39D2p6gNOfvy8+KnzkwQQfICxWNbeSixcsggyJHPeO0ByNLOdGGf69+hjZR+789oLHTHUVSB91FYoXJYVVefT2GYzmbI2CiAAlTWTN2cu/bZq23K+PrgIIK6ekRIyTXH9k4nKQE2PtFWrRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=airkyi.com; spf=none smtp.mailfrom=airkyi.com; arc=none smtp.client-ip=54.204.34.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=airkyi.com X-QQ-mid: izesmtp80t1744940897tacfebf76 X-QQ-Originating-IP: 1/RhFsCMqFycRYtj3mLsaPlfRGcihZnNKNg8dOyeGe4= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 18 Apr 2025 09:48:12 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 13519601627997338796 EX-QQ-RecipientCnt: 20 From: Chaoyi Chen To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonas Karlman , Kever Yang , Jianfeng Liu , Dragan Simic , Jimmy Hon , Quentin Schulz , FUKAUMI Naoki , Cristian Ciocaltea , Alexey Charkov , Geert Uytterhoeven , Sebastian Reichel , Chaoyi Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add rk3588 evb2 board Date: Fri, 18 Apr 2025 09:47:56 +0800 Message-Id: <20250418014757.336-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250418014757.336-1-kernel@airkyi.com> References: <20250418014757.336-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: izesmtp:airkyi.com:qybglogicsvrsz:qybglogicsvrsz4a-0 X-QQ-XMAILINFO: NY6OurWw+pG/jA8BsncHgmx6s5Fe/MGMLPsyfTo3dyYZwQrb37G1yvya EPERJawYzgk9wGov4raH1MUlnv134y+iurxUeqBxgrZDMpJTRN/rFBPv0HVGpHuiQx/NViz STMcX+3tgQA0pXc1ZI6/RSJRpDThVgZHgDZZqpFsRevgeT9e0FLXneGYwBgV3UFKmT1kAT9 g4GBz9kDxfaYy6y6Z+btKbPE1fX7JWsHY3KRMed+/uYcqUWyO9U0XWqt8CwG8ryMCCmL40+ 8riJd1+X6/DrFzkht2WNGPdHldPtvThJgFRBZKRNVHa4H+0Py1hr97BbsIEleYTQWAuyMWy 8W/TR+xBH1a//wBxKHsN4DWalEjjehjRSKGTun6RKkrW6zifnJKkvGQVTr3gtGNBJlGlEUf DlkfhW+3rGXZeXrx0rt+mIn8Te6a5kcf/fx6F43ZetKtGeWdsDLUB7oXn1sZSB1Hi09r9Sn z+hcw+NBPj3hEioTjF0JzAP4Oj0bp9OWKgmi31fupOIoKGRMY//QmVfLtv+rH/4NQD47Ukd jrDKkJhmtaEepDoscoYimo6Xryhoq94wOaZLhju056blxZByD7zehiDyHod3IpzKazZltuF gY9wTE8jEqa46D7NUBkpqIu5D2plGvlB3ubUxIYbCTChkmDL8UBP51D7lK0SMhkijNgGlpJ gMurtRjHt90jKSfyQSUVHS+6vhSrF8AFt0r5AQaVRnPzfhbzBBhVzzS88jo0WReeBMhqfFS I1e20Z7pGVZoQv0sur3JAI79kUxBmmL0syGJoOECSaPpfQJiX80J1KR4wPCcQvhJcoZ1p5U LBdHw7lpGNwNuqd4RfsToIlgBXKpQKDDee96nwz3vF1InQcrFFduHo1rKRs3Rw3SZSSg+XP dtyY4bkTueGcmwgktrQecQqDTatpXOO9koz6i/D5+V4ngOcw1YJ6Ns7UIxixaJFW1lnvAuW H2/2f5FwM/rl8kbjXVLOoRPoZtjaFQLN7iu49/z9IwGaevZO08sLJqi+Bv3nWFgksh+T/D2 vBbr0zA4vs0DrHtFG+1sfH7DiE1Wz58C/tRHlYFV6VgGD3Xpcw6dU2G2K3RAw= X-QQ-XMRINFO: M/715EihBoGSf6IYSX1iLFg= X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chaoyi Chen Add devicetree binding for the rk3588 evb2 board. Signed-off-by: Chaoyi Chen Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/rockchip.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 650fb833d96e..455fbb290b77 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1074,7 +1074,9 @@ properties: =20 - description: Rockchip RK3588 Evaluation board items: - - const: rockchip,rk3588-evb1-v10 + - enum: + - rockchip,rk3588-evb1-v10 + - rockchip,rk3588-evb2-v10 - const: rockchip,rk3588 =20 - description: Rockchip RK3588S Evaluation board --=20 2.49.0 From nobody Sun Dec 14 12:18:13 2025 Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6DC825E810; Fri, 18 Apr 2025 01:49:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744940974; cv=none; b=A7VP9lg9PT0D0QufuHp2xP2m4sgJ6fVtqHXV/0xLtyXqwGFaJXM742aEsoHPK0Miuct1sTYvRGqdSaHtAvazmNKgq22SyntpHM1Qsbip/7HgWxdQQJHEEiNabwmoL/hmfAd2HIXDRvCrc4PJOl5Fy2s9Q9YTTf4gKFf2SuYtwjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744940974; c=relaxed/simple; bh=TU3KAg66KaJzq+NS+TnK8lvoIUuJnbQtz2Gx94FCNgM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Z+DzbxtEKVOEmuAsxFixo2uTHyhzb+/sR45yI35XjLPPFnr4OqaNK1655vbxvoYdwvs5dmT3fk1EQySp53tV7ZrHD3RLkVxLIpsAz/J2T+JXPTE8JpLJypybNcwJVOYKfQvfc8dSjti35KFhoMpnHM8UFkmdmQlOxt1TlwMMQfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=airkyi.com; spf=none smtp.mailfrom=airkyi.com; arc=none smtp.client-ip=54.92.39.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=airkyi.com X-QQ-mid: izesmtp80t1744940902td5561ea2 X-QQ-Originating-IP: nNjEPbZ/+If6ADt59AMPTDHO6KkMnPIH/Um5zHeZN/s= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 18 Apr 2025 09:48:19 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 962928493100271343 EX-QQ-RecipientCnt: 20 From: Chaoyi Chen To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonas Karlman , Kever Yang , Jianfeng Liu , Dragan Simic , Jimmy Hon , Quentin Schulz , FUKAUMI Naoki , Cristian Ciocaltea , Alexey Charkov , Geert Uytterhoeven , Sebastian Reichel , Chaoyi Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add rk3588 evb2 board Date: Fri, 18 Apr 2025 09:47:57 +0800 Message-Id: <20250418014757.336-3-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250418014757.336-1-kernel@airkyi.com> References: <20250418014757.336-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: izesmtp:airkyi.com:qybglogicsvrsz:qybglogicsvrsz4a-0 X-QQ-XMAILINFO: OA8qd4daQrT+EgGJooko6It2S5b0ODJTLQ3cotiwiJ4fc7oQqZvnIlxa QJQdbctEO5OL9cYy/NCCKjlVCivB6XktimUiMAn8nj41kcbGi0PKjc1oQUT1XoCxRFLL3eq QsQso+vgdgMT/pWpP16eVr6lAsfJtJcDZOXDp7wphBMCjlV8XYNzen2N4TTyQJXyz/ETtbd Hhy8BtGiPKPfDrQ9VOv131soL6eRYnzOs4zL/Kx4y16qfNOSuNBa830lb617PL+tnhqma6g rfRZeZz7hEUlQoXUSf5DiWEpml1ij350ufQSuM5sEpI1odn15cgm3wjnZoUn84s4SNYksxq SFxd24pIIxAqaOGzbzAvnxB3edhdSegzhGVx/RZy7eL4IsZSiNn7ENlJzOcNrgKQeRVxmkL 97+980a1EnCDNyHROYNtXZ/duItt572k/ZZYYsWFg463BgkzJgK1yLbJu+rSZfqDVWvwBsr WpsIP8jBsoyW96YGrB4yTTBoqU/lpayOhPcF9Fh0P5+cEJ4CYco9ccNtqm0S6vCcC6horEm mefyktSfvjZ9aXQ6CxsYLI0SHao+bBaqSKqIaqbNrzo7d1Bxfsqna8hO3pthaQJioa01S3g d8ml0K/NOWC5/4OIJmy6AfMcAF+sqsD9o7Zjt5kxUs0/rLAi8Ys6Ks9B9JJdGQx9xs+1RNp 3OxY/Z2s1elNZJaIGXEYeGBEcBSr6OSNpr8WXB/ND0IcnH8QIuDoeWrq3NNcLwSqutfdEZw EBf54iHw1FdE5gsmnQ+Wmw17C2QvyGKaKHduZ+ZXVDb37B5hJCNlpbhVTKXyLjyppc9Q72v DBZRyJVso81cQpgR5eP/zh7WxN6lzO88DEprsYeFP8CCSb/l2h4aE8XFEZR9mgeCA+TsD3z ibC04U6l4mHDpfHM9rn2piKM611YNmlL/gcDTBWFx8iLxmiWLzJDbkHvjm0uqy62Q8rKNMS Smhvr8IDKPUOTD+EKCMSjD8PRp8Nwh4GTcF810u/hyeT18DRwXcAFTfw8Iuq4prt477Krvv MxgYspHrp7+x1Sp2BU0SWghFjLs6lddxsl3riObw== X-QQ-XMRINFO: OWPUhxQsoeAVDbp3OJHYyFg= X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chaoyi Chen General features for rk3588 evb2 board: - Rockchip RK3588 - LPDDR4/4X - eMMC5.1 - RK806-2x2pcs + DiscretePower - 1x HDMI2.1 TX / HDMI2.0 RX - 1x full size DisplayPort - 3x USB3.0 Host - 1x USB2.0 Host - WIFI/BT Tested with HDMI/GPU/USB2.0/USB3.0/WIFI module. Signed-off-by: Chaoyi Chen --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-evb2-v10.dts | 931 ++++++++++++++++++ 2 files changed, 932 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 3e8771ef69ba..555d72651bd5 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-i= o.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-h96-max-v58.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb2-v10.dts new file mode 100644 index 000000000000..91fe810d38d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Rockchip RK3588 EVB2 V10 Board"; + compatible =3D "rockchip,rk3588-evb2-v10", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&hym8563>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_host: vcc5v0-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usbdcin>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: regulator-vcc5v0-usbdcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + sram-supply =3D <&vdd_gpu_mem_s0>; + status =3D "okay"; +}; + +&hdmi0 { + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + wakeup-source; + }; +}; + +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins =3D <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status =3D "okay"; +}; + +&sdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdiom0_pins>; + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency =3D <150000000>; + mmc-pwrseq =3D <&sdio_pwrseq>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&gpio2>; + interrupts =3D ; + interrupt-names =3D "host-wake"; + pinctrl-0 =3D <&wifi_host_wake_irq>; + pinctrl-names =3D "default"; + }; +}; + +&spi2 { + status =3D "okay"; + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <2>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <1000000>; + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc5v0_sys>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-coupled-with =3D <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <400>; + regulator-name =3D "vdd_gpu_mem_s0"; + regulator-coupled-with =3D <&vdd_gpu_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible =3D "rockchip,rk806"; + reg =3D <0x01>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_2v0_pldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread =3D <10000>; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux =3D <2 3>; + status =3D "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux =3D <2 3>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; --=20 2.49.0