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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add DT entries for the sm8650 iris decoder. Since the firmware is required to be signed, only enable on Qualcomm development boards where the firmware is available. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 94 +++++++++++++++++++++++++++++= ++++ 4 files changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8650-hdk.dts index d0912735b54e5090f9f213c2c9341e03effbbbff..69db971d9d2d32cdee7bb1c3093= c7849b94798a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -894,6 +894,11 @@ &ipa { status =3D "okay"; }; =20 +&iris { + firmware-name =3D "qcom/vpu/vpu33_p4.mbn"; + status =3D "okay"; +}; + &gpu { status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8650-mtp.dts index 76ef43c10f77d8329ccf0a05c9d590a46372315f..04108235d9bc6f977e9cf1b887b= 0c89537723387 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -585,6 +585,11 @@ vreg_l7n_3p3: ldo7 { }; }; =20 +&iris { + firmware-name =3D "qcom/vpu/vpu33_p4.mbn"; + status =3D "okay"; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins =3D "gpio21"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8650-qrd.dts index 71033fba21b56bc63620dca3e453c14191739675..58bdc6619ac55eda122f3fe6e68= 0e0e61967d019 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -824,6 +824,11 @@ &ipa { status =3D "okay"; }; =20 +&iris { + firmware-name =3D "qcom/vpu/vpu33_p4.mbn"; + status =3D "okay"; +}; + &gpu { status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index c2937f7217943c4ca91a91eadc8259b2d6a01372..9afde0582ec9b8fef44c0af0324= bfae9b20d1d60 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4955,6 +4955,100 @@ opp-202000000 { }; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,sm8650-iris"; + reg =3D <0 0x0aa00000 0 0xf0000>; + + interrupts =3D ; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx"; + + operating-points-v2 =3D <&iris_opp_table>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + /* FW load region */ + memory-region =3D <&video_mem>; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names =3D "bus", + "xo", + "core"; + + iommus =3D <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-196000000 { + opp-hz =3D /bits/ 64 <196000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-380000000 { + opp-hz =3D /bits/ 64 <380000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-435000000 { + opp-hz =3D /bits/ 64 <435000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + required-opps =3D <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-533333334 { + opp-hz =3D /bits/ 64 <533333334>; + required-opps =3D <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible =3D "qcom,sm8650-videocc"; reg =3D <0 0x0aaf0000 0 0x10000>; --- base-commit: a7dca088884312d607fff89f2666c670cb7073ac change-id: 20250418-topic-sm8x50-upstream-iris-8650-dt-d2c64a59505f Best regards, --=20 Neil Armstrong