From nobody Sun Dec 14 12:18:20 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CE9B2040B2; Thu, 17 Apr 2025 23:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; cv=none; b=eWPK/7hAY2N/5QlRngrXkgPvPwwS2XHAwhCR9qKTwrjwvO6cxHZMm4FJEl7jTd5Ou0o+fKn6xZHj0EQMgkYVUmrGfg+8F8geN6caG33fH4NFfPif6ePYtshen7Z3zbx2P6G+4IzxinjOWggOHr6cjU5anxWtsgCvLFSjwFGDEqQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; c=relaxed/simple; bh=JF+w8wmf10+jcWDvzLRc7NzcG6KMv0F4Ct0bjQsGJgU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ENxS8DG+1XC/XxVb8QZuIXQkuXVnVaXF8RMEEuZCkgPz/cBJByTv82xbjPoSOjrc1EcnfMRaq8SCcHgD15JOwtAuaMpPVhhIQO0a68mXhsn+M7kZIsXRrvXIrhcstg4YdjtNolrYjybOYAgMnej8vAB8/oVKRgbHU+1kTR8RiK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Bf+sOS8P; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Bf+sOS8P" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUe2A781170 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 18:30:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744932640; bh=9nJp0mD9Fz2Zcm3q8ukJFhKlX3gPM3uekDV5Vo0ilmc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Bf+sOS8PT6glExPtEr3RHEdxortS9MoCHMBv7L+Fa5w2Pcpb95Cy+FOdsyor4T5lD fUeCPCEe7D4eH7938zwr1YsQLeTx1md4PDiuRwACdz2dpRDZKBkWZhqMAWxRuYF6OQ bUGjOLbXeXQviUuOTjukGAr4PxmIc4jTLvhYcmU0= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUe9v096088 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 18:30:40 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 18:30:40 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 18:30:40 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HNUePf023286; Thu, 17 Apr 2025 18:30:40 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah Subject: [PATCH v2 1/5] arm64: dts: ti: k3-am6*: Set eMMC clock parents to default Date: Thu, 17 Apr 2025 18:30:36 -0500 Message-ID: <20250417233040.3658761-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417233040.3658761-1-jm@ti.com> References: <20250417233040.3658761-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and we have a non-glich-free mux. To remove any potential issues, lets switch back to the defaults. Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Fixes: d3ae4e8d8b6a ("arm64: dts: ti: k3-am62a-main: Add sdhci0 instance") Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Signed-off-by: Judith Mendez Acked-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 2 -- 3 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 7d355aa73ea21..0c286f600296c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -552,8 +552,6 @@ sdhci0: mmc@fa10000 { power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 57 5>, <&k3_clks 57 6>; clock-names =3D "clk_ahb", "clk_xin"; - assigned-clocks =3D <&k3_clks 57 6>; - assigned-clock-parents =3D <&k3_clks 57 8>; bus-width =3D <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index a1daba7b1fad5..455ccc770f16a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -575,8 +575,6 @@ sdhci0: mmc@fa10000 { power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 57 5>, <&k3_clks 57 6>; clock-names =3D "clk_ahb", "clk_xin"; - assigned-clocks =3D <&k3_clks 57 6>; - assigned-clock-parents =3D <&k3_clks 57 8>; bus-width =3D <8>; mmc-hs200-1_8v; ti,clkbuf-sel =3D <0x7>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 6e3beb5c2e010..f9b5c97518d68 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -564,8 +564,6 @@ sdhci0: mmc@fa10000 { power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 57 1>, <&k3_clks 57 2>; clock-names =3D "clk_ahb", "clk_xin"; - assigned-clocks =3D <&k3_clks 57 2>; - assigned-clock-parents =3D <&k3_clks 57 4>; bus-width =3D <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; --=20 2.49.0 From nobody Sun Dec 14 12:18:20 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6B5E2116E0; Thu, 17 Apr 2025 23:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; cv=none; b=q31aCUufwX760sIGrEeOuHZLprKUUhSSUDXu3fCpa+k7kqORpF6+VStmnp+nsXAyVpHTnoorLpAFfPD5ffibFn423QPTbMt/cOLVv8gNvnbOs25oSsLf88xpk4o/IelnF0VHqDGrbWKMkXDekGflBbIZPIChvNvM+W/oJfM1J7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; c=relaxed/simple; bh=rpszKideZPcl4PnxosYFAiekHU3Yf3PYWLiMSd78ay8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Thu, 17 Apr 2025 18:30:39 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HNUePg023286; Thu, 17 Apr 2025 18:30:40 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah Subject: [PATCH v2 2/5] arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC boot Date: Thu, 17 Apr 2025 18:30:37 -0500 Message-ID: <20250417233040.3658761-3-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417233040.3658761-1-jm@ti.com> References: <20250417233040.3658761-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. For eMMC and SD boot modes, voltage regulator nodes, io-expander nodes, gpio nodes, and MMC nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot and eMMC boot. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index 8e9fc00a6b3c7..aafdb90c0eb70 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -69,6 +69,7 @@ vddshv_sdio: regulator-4 { gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; states =3D <1800000 0x0>, <3300000 0x1>; + bootph-all; }; }; =20 @@ -77,12 +78,14 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; + bootph-all; }; =20 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; + bootph-all; }; =20 pmic_irq_pins_default: pmic-irq-default-pins { @@ -118,6 +121,7 @@ exp1: gpio@22 { =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; }; =20 exp2: gpio@23 { @@ -229,6 +233,14 @@ &tlv320aic3106 { DVDD-supply =3D <&buck2_reg>; }; =20 +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + &gpmc0 { ranges =3D <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = =3D 16MB */ }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 1c9d95696c839..7de4a9f139ad4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -313,6 +313,7 @@ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_= DAT5 */ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; =20 main_mmc1_pins_default: main-mmc1-default-pins { @@ -615,6 +616,7 @@ &sdhci0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; disable-wp; + bootph-all; }; =20 &sdhci1 { --=20 2.49.0 From nobody Sun Dec 14 12:18:20 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 811D01DF260; Thu, 17 Apr 2025 23:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932648; cv=none; b=YwZcYFNDm8UkBMYDOpTT2wNRQun8XqN+9e4AmyWdUUQcAya0Wp3ukqiVUDMT4SzfnyH50/2blNnfH4rRZgEHQVdXJwpXP+y/MVRvTQmg2p78H4or3WFuGCTgoAX8OSSuN47sKcqBAjneklQlTqikskcwBgk5gNnzVKXmsIvZM7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932648; c=relaxed/simple; bh=5zsOBMyKDRrYus2KS6jpmLIaZ3RdH7jmamJy8CjOZZ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EP0sQIXZ1BvZVGho69bfw0B54VHWS9DM45hYoQDbxVajGRDiEiTNgouxTOMsMWYeRi5CIQMbbHTvcizzkwrdAG27mQUP1AbA8VQGNb8Cr/F3opyoZqZE/RcB40o+yH4OimI7+141HPDZCsaJ3bYd60zOuRbX4Z+bgUQayhVuleo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=NC4wC3iA; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NC4wC3iA" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUeWv781174 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 18:30:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744932640; bh=LlfNYEA3GcNF5ETHru+TFzjorIT8qkTiM1wG+X+ViQo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NC4wC3iAOVY5D0vY+Zm9YDvjshgfXj3KKiSscRdf/SBQqbmVZH3Bjhmbedp/RVbLL l/BIBhMmZP+9Pa2FrQ9Dj1xpITcZM+gfE9QyXZ2Zgtf8A/EyvWixvsEE7tC3YHD+Ts puh8nEE0TTEz/cPRY/LPHXZkUSnJh9/foQKttKa8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUekk003887 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 18:30:40 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 18:30:40 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 18:30:40 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HNUePh023286; Thu, 17 Apr 2025 18:30:40 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah Subject: [PATCH v2 3/5] arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0 Date: Thu, 17 Apr 2025 18:30:38 -0500 Message-ID: <20250417233040.3658761-4-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417233040.3658761-1-jm@ti.com> References: <20250417233040.3658761-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" For am65x, add missing ITAPDLYSEL values for Default Speed and High Speed SDR modes to sdhci0 node according to the device datasheet [0]. Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel va= lues") [0] https://www.ti.com/lit/gpn/am6548 Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 94a812a1355ba..5ebf7ada6e485 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -449,6 +449,8 @@ sdhci0: mmc@4f80000 { ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-ddr52 =3D <0x5>; ti,otap-del-sel-hs200 =3D <0x5>; + ti,itap-del-sel-legacy =3D <0xa>; + ti,itap-del-sel-mmc-hs =3D <0x1>; ti,itap-del-sel-ddr52 =3D <0x0>; dma-coherent; status =3D "disabled"; --=20 2.49.0 From nobody Sun Dec 14 12:18:20 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B6120E02A; Thu, 17 Apr 2025 23:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; cv=none; b=Dj4mesBOYZLKz5PNaH+gms0JiT3mPXs8GnkEwICeJjtTXgDTFDH6HCN8s6zyo1bl8WVbsXiTTchvmW4kxJFe5be2riwXMO5g33njiyFws64BhhvZq1eToPeVPUbTysF1EonoWFjU+5U2Qw+BBZ+udgjCUu/bjaxPAPTGnFUgwfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744932650; c=relaxed/simple; bh=q43B7p3uClxu4DVuAKwWE6EdnhZUAtwoL5jvyr3rx1c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sRLNRysxl4XvRAbnHRmFrTsfIPAFhYlNdukNkaWxJ29J0ATZ5wZWBQuwwUSEZsIo/UKho1nyd67csKAffOrZlQR6tGtvKil8eGAZ70cJE92aiJeklHbTRxMDcqJgAPkTFhQVPkzcmQkzYtshXiCVWjLPjjN7rubFjCzYEg+uAZ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EcedokKt; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EcedokKt" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUePH149455 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 18:30:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744932641; bh=Do5gyYIYR+XxRDrHM0vtw2Vw4BTYQBOwQE1WrrVFmw8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EcedokKty3i0FgcfhI7dzzE4UoQ3KxMcUm1FT8kEvTXhBFqsUSglerCKepwLhR5yl qQKOrUOjrsWxFmMZMgiia1+GMuTyKZGGTMOGR6k15zg8O7oC44WwPqnMEbLoqlvJFD 1hbPFnzfYGnsgL/LAS5jwoDh5efIHAID32gD6zlQ= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HNUeRe096098 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 18:30:40 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 18:30:40 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 18:30:40 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HNUePi023286; Thu, 17 Apr 2025 18:30:40 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah Subject: [PATCH v2 4/5] arm64: dts: ti: k3-am62*: Add non-removable flag for eMMC Date: Thu, 17 Apr 2025 18:30:39 -0500 Message-ID: <20250417233040.3658761-5-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417233040.3658761-1-jm@ti.com> References: <20250417233040.3658761-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" EMMC device is non-removable so add 'non-removable' DT property to avoid having to redetect the eMMC after suspend/resume. Signed-off-by: Judith Mendez Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index a5469f2712f09..1c8b4d13fb491 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -832,6 +832,7 @@ &main_spi2 { =20 &sdhci0 { bootph-all; + non-removable; pinctrl-names =3D "default"; pinctrl-0 =3D <&emmc_pins_default>; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index d29f524600af0..43fcb57b34ebf 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -454,6 +454,7 @@ &main_i2c2 { =20 &sdhci0 { status =3D "okay"; + non-removable; ti,driver-strength-ohm =3D <50>; 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Thu, 17 Apr 2025 18:30:40 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HNUePj023286; Thu, 17 Apr 2025 18:30:40 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah Subject: [PATCH v2 5/5] arm64: dts: ti: k3-am6*: Remove disable-wp for eMMC Date: Thu, 17 Apr 2025 18:30:40 -0500 Message-ID: <20250417233040.3658761-6-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417233040.3658761-1-jm@ti.com> References: <20250417233040.3658761-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remove disable-wp flag for eMMC nodes since this flag is only applicable to SD according to the binding doc (mmc/mmc-controller-common.yaml). For eMMC, this flag should be ignored but lets remove anyways to cleanup sdhci nodes. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 - arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 - arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 - arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am69-sk.dts | 1 - 10 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 55ed418c023bc..e5be92aa12189 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -381,7 +381,6 @@ serial_flash: flash@0 { &sdhci0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; - disable-wp; non-removable; bootph-all; status =3D "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 1c8b4d13fb491..72b09f9c69d8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -835,7 +835,6 @@ &sdhci0 { non-removable; pinctrl-names =3D "default"; pinctrl-0 =3D <&emmc_pins_default>; - disable-wp; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 147d56b879843..0d4115590b9c3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -338,7 +338,6 @@ serial_flash: flash@0 { &sdhci0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; - disable-wp; non-removable; bootph-all; status =3D "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 7de4a9f139ad4..625ce8f8958b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -615,7 +615,6 @@ &sdhci0 { non-removable; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; - disable-wp; bootph-all; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 43fcb57b34ebf..1025062c77d57 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -456,7 +456,6 @@ &sdhci0 { status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; - disable-wp; bootph-all; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 561916c6e151c..9d933e837dd4b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -437,7 +437,6 @@ &sdhci0 { non-removable; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; - disable-wp; }; =20 &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index f8ec40523254b..5c6197ba842e4 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -597,7 +597,6 @@ &sdhci0 { status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; - disable-wp; bootph-all; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index aa7139cc8a92b..c30425960398e 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -456,7 +456,6 @@ &sdhci0 { bus-width =3D <8>; non-removable; ti,driver-strength-ohm =3D <50>; - disable-wp; }; =20 /* diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi = b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index ae842b85b70de..12af6cb7f65cf 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -50,5 +50,4 @@ &sdhci0 { bus-width =3D <8>; non-removable; ti,driver-strength-ohm =3D <50>; - disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index b85227052f97e..f28375629739c 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -940,7 +940,6 @@ &main_sdhci0 { status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; - disable-wp; }; =20 &main_sdhci1 { --=20 2.49.0