From nobody Mon Feb 9 19:26:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC3B9253329; Thu, 17 Apr 2025 17:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744909226; cv=none; b=kq+T+RQJVnusbtfjxKnsd72fKx4wwvQ0LWBQei7n/4noqEbS6lmBaCKC4Xfsy6cTHkLOW8RlfEEWvOOp7p3MpScKTt4H0A4zFzxBAjLcwPiMtd9W8J0sPJIDwyp0l0W7sfRVE9PYE2sI+o0rjPdBUGTzTj6elYFkJqm5of3alWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744909226; c=relaxed/simple; bh=JLgK9+nY1vCjbvflNygPDXg0ccB+OawZkKOhP1y56kE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DcgPYlKDvEl5mpS0Ai7YV2sajxqs377jjhpv5ZDcbeGkJpnhEFKXuV8TEEmUCCbzM8EJdkkaPqltMai6sWUokjQ2KDrWv8VfOj9z7KhbguRnlKZ2HXvlYL7NY8kvnXcTrHw5IcGTnIGKYEaIHSA1tC9i7UIO/YGRmLC/J8CiuK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ndZi0pln; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ndZi0pln" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744909225; x=1776445225; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JLgK9+nY1vCjbvflNygPDXg0ccB+OawZkKOhP1y56kE=; b=ndZi0plnxx0Yh5YFQNgIO5WfO5kC+tGSE3z15+JyjhPX1mBXnm6UmaRp P9tPiarKVXFSUJDM0nIqpTkXWDQ+1BXmjCJ4f5eP1H+0vMHTDEadKUm5u NMkOGDZjjOOuzLxYz5n+pvBBQUDe/bjY/+k0CtGXqzarWsbl5qUzaWCIo AVTB8bni0K+LbPeBi4EEMIdgUmitvpjUZkhllox5BElJ74emLUXdFviF4 kpAnwaw2MieCks66MKfzcx9Mo4tyMlhzZidPebFhDNgE5019QmSEEGMVt clxhn2O0NGTfWTkFk7l0ourVBJ68P99cssMbWxtbB6d+aCXzAoeJoiRRo w==; X-CSE-ConnectionGUID: il7bO7o4TE6Bd8SIy9SVUA== X-CSE-MsgGUID: rt+4iNaZR5CvCVwhrVzuIA== X-IronPort-AV: E=McAfee;i="6700,10204,11406"; a="57896201" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="57896201" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 10:00:23 -0700 X-CSE-ConnectionGUID: YxOQGs4cRMichYL+ubehKQ== X-CSE-MsgGUID: 6vbxRKq5S4usfu2I4EfDzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="131411694" Received: from spandruv-desk.jf.intel.com ([10.54.75.16]) by fmviesa010.fm.intel.com with ESMTP; 17 Apr 2025 10:00:23 -0700 From: Srinivas Pandruvada To: hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Pandruvada Subject: [PATCH 1/2] platform/x86: ISST: Support SST-TF revision 2 Date: Thu, 17 Apr 2025 10:00:10 -0700 Message-ID: <20250417170011.1243858-2-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250417170011.1243858-1-srinivas.pandruvada@linux.intel.com> References: <20250417170011.1243858-1-srinivas.pandruvada@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SST-TF revision 2 supports a higher number of cores per bucket, as the current limit of 256 cores may be insufficient. To accommodate this, a new offset, "SST_TF_INFO-8," is introduced, allowing for a higher core count. Utilize this offset instead of the current "SST_TF_INFO-1" offset, based on SST-TF revision 2 or higher, and if there is a non-zero core count in any bucket. Signed-off-by: Srinivas Pandruvada --- .../intel/speed_select_if/isst_tpmi_core.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/= drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c index 9978cdd19851..bc4089d3d421 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c @@ -1328,9 +1328,14 @@ static int isst_if_get_tpmi_instance_count(void __us= er *argp) #define SST_TF_INFO_0_OFFSET 0 #define SST_TF_INFO_1_OFFSET 8 #define SST_TF_INFO_2_OFFSET 16 +#define SST_TF_INFO_8_OFFSET 64 +#define SST_TF_INFO_8_BUCKETS 3 =20 #define SST_TF_MAX_LP_CLIP_RATIOS TRL_MAX_LEVELS =20 +#define SST_TF_FEATURE_REV_START 4 +#define SST_TF_FEATURE_REV_WIDTH 8 + #define SST_TF_LP_CLIP_RATIO_0_START 16 #define SST_TF_LP_CLIP_RATIO_0_WIDTH 8 =20 @@ -1340,10 +1345,14 @@ static int isst_if_get_tpmi_instance_count(void __u= ser *argp) #define SST_TF_NUM_CORE_0_START 0 #define SST_TF_NUM_CORE_0_WIDTH 8 =20 +#define SST_TF_NUM_MOD_0_START 0 +#define SST_TF_NUM_MOD_0_WIDTH 16 + static int isst_if_get_turbo_freq_info(void __user *argp) { static struct isst_turbo_freq_info turbo_freq; struct tpmi_per_power_domain_info *power_domain_info; + u8 feature_rev; int i, j; =20 if (copy_from_user(&turbo_freq, argp, sizeof(turbo_freq))) @@ -1360,6 +1369,10 @@ static int isst_if_get_turbo_freq_info(void __user *= argp) turbo_freq.max_trl_levels =3D TRL_MAX_LEVELS; turbo_freq.max_clip_freqs =3D SST_TF_MAX_LP_CLIP_RATIOS; =20 + _read_tf_level_info("feature_rev", feature_rev, turbo_freq.level, + SST_TF_INFO_0_OFFSET, SST_TF_FEATURE_REV_START, + SST_TF_FEATURE_REV_WIDTH, SST_MUL_FACTOR_NONE); + for (i =3D 0; i < turbo_freq.max_clip_freqs; ++i) _read_tf_level_info("lp_clip*", turbo_freq.lp_clip_freq_mhz[i], turbo_freq.level, SST_TF_INFO_0_OFFSET, @@ -1376,12 +1389,32 @@ static int isst_if_get_turbo_freq_info(void __user = *argp) SST_MUL_FACTOR_FREQ) } =20 + if (feature_rev >=3D 2) { + bool valid =3D false; + + for (i =3D 0; i < SST_TF_INFO_8_BUCKETS; ++i) { + _read_tf_level_info("bucket_*_mod_count", turbo_freq.bucket_core_counts= [i], + turbo_freq.level, SST_TF_INFO_8_OFFSET, + SST_TF_NUM_MOD_0_WIDTH * i, SST_TF_NUM_MOD_0_WIDTH, + SST_MUL_FACTOR_NONE) + + if (!valid && turbo_freq.bucket_core_counts[i]) + valid =3D true; + } + + if (valid) + goto done_core_count; + } + for (i =3D 0; i < TRL_MAX_BUCKETS; ++i) _read_tf_level_info("bucket_*_core_count", turbo_freq.bucket_core_counts= [i], turbo_freq.level, SST_TF_INFO_1_OFFSET, SST_TF_NUM_CORE_0_WIDTH * i, SST_TF_NUM_CORE_0_WIDTH, SST_MUL_FACTOR_NONE) =20 + +done_core_count: + if (copy_to_user(argp, &turbo_freq, sizeof(turbo_freq))) return -EFAULT; =20 --=20 2.48.1 From nobody Mon Feb 9 19:26:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 466BA254840; Thu, 17 Apr 2025 17:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744909227; cv=none; b=sPZhwiBryjLoDaeQXI6b8QDuKVUrq2zFd1hAEbNpPe52bWmJGY1Eub46x+Noa/9f0UA1EeTiWlHzDLOKouaGaTYFZDVe1lQGZYls6PzLTT8Wg6vw5gte2zIWnh8/2bYgZn2nqvaBJl3sw6pX2IHjeGF6ogGEyd1qms0muXljQc8= ARC-Message-Signature: i=1; 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d="scan'208";a="131411700" Received: from spandruv-desk.jf.intel.com ([10.54.75.16]) by fmviesa010.fm.intel.com with ESMTP; 17 Apr 2025 10:00:23 -0700 From: Srinivas Pandruvada To: hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Pandruvada Subject: [PATCH 2/2] platform/x86: ISST: Support SST-PP revision 2 Date: Thu, 17 Apr 2025 10:00:11 -0700 Message-ID: <20250417170011.1243858-3-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250417170011.1243858-1-srinivas.pandruvada@linux.intel.com> References: <20250417170011.1243858-1-srinivas.pandruvada@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SST PP revision 2 added fabric 1 P0, P1 and Pm frequencies. Export them by using a new IOCTL ISST_IF_GET_PERF_LEVEL_FABRIC_INFO. This IOCTL requires platforms with SST PP revision 2 or higher. To accommodate potential future increases in fabric count and avoid ABI changes, support is extended for up to 8 fabrics. Signed-off-by: Srinivas Pandruvada --- .../intel/speed_select_if/isst_tpmi_core.c | 66 +++++++++++++++++++ include/uapi/linux/isst_if.h | 26 ++++++++ 2 files changed, 92 insertions(+) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/= drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c index bc4089d3d421..b868ea0ce8f6 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c @@ -1016,6 +1016,7 @@ static int isst_if_set_perf_feature(void __user *argp) =20 #define SST_PP_INFO_10_OFFSET 80 #define SST_PP_INFO_11_OFFSET 88 +#define SST_PP_INFO_12_OFFSET 96 =20 #define SST_PP_P1_SSE_START 0 #define SST_PP_P1_SSE_WIDTH 8 @@ -1068,6 +1069,15 @@ static int isst_if_set_perf_feature(void __user *arg= p) #define SST_PP_CORE_RATIO_PM_FABRIC_START 48 #define SST_PP_CORE_RATIO_PM_FABRIC_WIDTH 8 =20 +#define SST_PP_CORE_RATIO_P0_FABRIC_1_START 0 +#define SST_PP_CORE_RATIO_P0_FABRIC_1_WIDTH 8 + +#define SST_PP_CORE_RATIO_P1_FABRIC_1_START 8 +#define SST_PP_CORE_RATIO_P1_FABRIC_1_WIDTH 8 + +#define SST_PP_CORE_RATIO_PM_FABRIC_1_START 16 +#define SST_PP_CORE_RATIO_PM_FABRIC_1_WIDTH 8 + static int isst_if_get_perf_level_info(void __user *argp) { struct isst_perf_level_data_info perf_level; @@ -1167,6 +1177,59 @@ static int isst_if_get_perf_level_info(void __user *= argp) return 0; } =20 +static int isst_if_get_perf_level_fabric_info(void __user *argp) +{ + struct isst_perf_level_fabric_info perf_level_fabric; + struct tpmi_per_power_domain_info *power_domain_info; + int start =3D SST_PP_CORE_RATIO_P0_FABRIC_START; + int width =3D SST_PP_CORE_RATIO_P0_FABRIC_WIDTH; + int offset =3D SST_PP_INFO_11_OFFSET; + int i; + + if (copy_from_user(&perf_level_fabric, argp, sizeof(perf_level_fabric))) + return -EFAULT; + + power_domain_info =3D get_instance(perf_level_fabric.socket_id, + perf_level_fabric.power_domain_id); + if (!power_domain_info) + return -EINVAL; + + if (perf_level_fabric.level > power_domain_info->max_level) + return -EINVAL; + + if (power_domain_info->pp_header.feature_rev < 2) + return -EINVAL; + + if (!(power_domain_info->pp_header.level_en_mask & BIT(perf_level_fabric.= level))) + return -EINVAL; + + /* For revision 2, maximum number of fabrics is 2 */ + perf_level_fabric.max_fabrics =3D 2; + + for (i =3D 0; i < perf_level_fabric.max_fabrics; i++) { + _read_pp_level_info("p0_fabric_freq_mhz", perf_level_fabric.p0_fabric_fr= eq_mhz[i], + perf_level_fabric.level, offset, start, width, + SST_MUL_FACTOR_FREQ) + start +=3D width; + + _read_pp_level_info("p1_fabric_freq_mhz", perf_level_fabric.p1_fabric_fr= eq_mhz[i], + perf_level_fabric.level, offset, start, width, + SST_MUL_FACTOR_FREQ) + start +=3D width; + + _read_pp_level_info("pm_fabric_freq_mhz", perf_level_fabric.pm_fabric_fr= eq_mhz[i], + perf_level_fabric.level, offset, start, width, + SST_MUL_FACTOR_FREQ) + offset =3D SST_PP_INFO_12_OFFSET; + start =3D 0; + } + + if (copy_to_user(argp, &perf_level_fabric, sizeof(perf_level_fabric))) + return -EFAULT; + + return 0; +} + #define SST_PP_FUSED_CORE_COUNT_START 0 #define SST_PP_FUSED_CORE_COUNT_WIDTH 8 =20 @@ -1453,6 +1516,9 @@ static long isst_if_def_ioctl(struct file *file, unsi= gned int cmd, case ISST_IF_GET_PERF_LEVEL_INFO: ret =3D isst_if_get_perf_level_info(argp); break; + case ISST_IF_GET_PERF_LEVEL_FABRIC_INFO: + ret =3D isst_if_get_perf_level_fabric_info(argp); + break; case ISST_IF_GET_PERF_LEVEL_CPU_MASK: ret =3D isst_if_get_perf_level_mask(argp); break; diff --git a/include/uapi/linux/isst_if.h b/include/uapi/linux/isst_if.h index 0df1a1c3caf4..8197a4800604 100644 --- a/include/uapi/linux/isst_if.h +++ b/include/uapi/linux/isst_if.h @@ -375,6 +375,30 @@ struct isst_perf_level_data_info { __u16 trl_freq_mhz[TRL_MAX_LEVELS][TRL_MAX_BUCKETS]; }; =20 +#define MAX_FABRIC_COUNT 8 + +/** + * struct isst_perf_level_fabric_info - Structure to get SST-PP fabric det= ails + * @socket_id: Socket/package id + * @power_domain_id: Power Domain id + * @level: SST-PP level for which caller wants to get information + * @max_fabrics: Count of fabrics in resonse + * @p0_fabric_freq_mhz: Fabric (Uncore) maximum frequency + * @p1_fabric_freq_mhz: Fabric (Uncore) TDP frequency + * @pm_fabric_freq_mhz: Fabric (Uncore) minimum frequency + * + * Structure used to get information on frequencies for fabrics. + */ +struct isst_perf_level_fabric_info { + __u8 socket_id; + __u8 power_domain_id; + __u16 level; + __u16 max_fabrics; + __u16 p0_fabric_freq_mhz[MAX_FABRIC_COUNT]; + __u16 p1_fabric_freq_mhz[MAX_FABRIC_COUNT]; + __u16 pm_fabric_freq_mhz[MAX_FABRIC_COUNT]; +}; + /** * struct isst_perf_level_cpu_mask - Structure to get SST-PP level CPU mask * @socket_id: Socket/package id @@ -471,5 +495,7 @@ struct isst_turbo_freq_info { #define ISST_IF_GET_BASE_FREQ_INFO _IOR(ISST_IF_MAGIC, 14, struct isst_bas= e_freq_info *) #define ISST_IF_GET_BASE_FREQ_CPU_MASK _IOR(ISST_IF_MAGIC, 15, struct isst= _perf_level_cpu_mask *) #define ISST_IF_GET_TURBO_FREQ_INFO _IOR(ISST_IF_MAGIC, 16, struct isst_tu= rbo_freq_info *) +#define ISST_IF_GET_PERF_LEVEL_FABRIC_INFO _IOR(ISST_IF_MAGIC, 17,\ + struct isst_perf_level_fabric_info *) =20 #endif --=20 2.48.1