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charset="utf-8" Convert the clock device tree bindings to yaml for the Altera SoCFPGA Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are subnodes to Altera SOCFPGA Clock Manager, the yaml was added to socfpga-clk-manager.yaml. Signed-off-by: Matthew Gerlach --- .../arm/altera/socfpga-clk-manager.yaml | 118 +++++++++++++++++- .../bindings/clock/altr_socfpga.txt | 30 ----- 2 files changed, 117 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/altr_socfpga.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manag= er.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.= yaml index 572381306681..4cda13259530 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -9,17 +9,133 @@ title: Altera SOCFPGA Clock Manager maintainers: - Dinh Nguyen =20 -description: test +description: + This binding describes the Altera SOCFGPA Clock Manager and its associat= ed + tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arri= a10 + chip families. =20 properties: compatible: items: - const: altr,clk-mgr + reg: maxItems: 1 =20 + clocks: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^osc[0-9]$": + type: object + + "^[a-z0-9,_]+[clk,pll,clk_gate,clk_divided](@[a-f0-9]+)?$": + type: object + additionalProperties: false + + properties: + + compatible: + enum: + - altr,socfpga-pll-clock + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-pll-clock + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + - fixed-clock + + clocks: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: one or more phandles to input clock + + "#address-cells": + const: 1 + + "#clock-cells": + const: 0 + + "#size-cells": + const: 0 + + clk-gate: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: gating register offset + - description: bit index + + div-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: divider register offset + - description: bit shift + - description: bit width + + fixed-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + + reg: + maxItems: 1 + + patternProperties: + "^[a-z0-9,_]+[clk,pll](@[a-f0-9]+)?$": + type: object + additionalProperties: false + + properties: + compatible: + enum: + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + + "#clock-cells": + const: 0 + + clocks: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: one or more phandles to input clock + + clk-gate: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: gating register offset + - description: bit index + + div-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: divider register offset + - description: bit shift + - description: bit width + + fixed-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + + reg: + maxItems: 1 + + required: + - compatible + - clocks + - "#clock-cells" + + required: + - compatible + - "#clock-cells" + required: - compatible + - reg =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Doc= umentation/devicetree/bindings/clock/altr_socfpga.txt deleted file mode 100644 index f72e80e0dade..000000000000 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for Altera's SoCFPGA platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "altr,socfpga-pll-clock" - for a PLL clock - "altr,socfpga-perip-clock" - The peripheral clock divided from the - PLL clock. - "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and - can get gated. - -- reg : shall be the control register offset from CLOCK_MANAGER's base for= the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding, shall be set to 0. - -Optional properties: -- fixed-divider : If clocks have a fixed divider value, use this property. -- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register - and the bit index. -- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg con= tains - the divider register, bit shift, and width. -- clk-phase : For the sdmmc_clk, contains the value of the clock phase tha= t controls - the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the s= econd - value is the cclk_in_drv(drvsel). The clk-phase is used to enable the cor= rect - hold/delay times that is needed for the SD/MMC CIU clock. The values of b= oth - can be 0-315 degrees, in 45 degree increments. --=20 2.35.3