From nobody Tue Feb 10 03:20:50 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76AD824C065; Thu, 17 Apr 2025 13:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744896211; cv=none; b=FMaGfJBG2RFb0BHiSF03+eb35g3An1p9LOxXtFC0RMdF1TGv7IxOllyIM2cgM4msGZMAzj+3KK/e2pzdbNtg4PN3LQhl4BmfdxRVFDWLrZvo9za1qNxbUWmINbJOJgGS7KjDUijvqXo3q82+Uwg/YjZRvdVP1TQw5q7f+/Fyak4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744896211; c=relaxed/simple; bh=SAogXjErmnUKWUV3LPeC/KcgOjnw/QZRkCVS8VQvp7g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SOVNRZ89da/13P/CkQpVH5nlE9NEyTg082cLVqWqi2mTazUZ0dFfmv3OPsOLuJ/QXTXuhGqcU8pB+QuiMZ1bjEONF4EtBA9jVHMpHZSYSfvVcGcDDxrzryOESh5ZAyP4dmFjYBu6j7hx1qxH76W7m/YwMO923ogWbMwE4T/f7rM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=vbs1VLFt; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="vbs1VLFt" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53HB3H6o007078; Thu, 17 Apr 2025 15:22:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= D1vrqcKSTo7wXwCZBje6dgQBk+XJl1AKFrrz1y87N6A=; b=vbs1VLFtptaUArvg 0+ANFYsmT+kBHV3k25Ygtk3S9LVXM4ypToKl/IRszAxx+hV9hST9tbaubPR4+mA1 AupFrloIdQCXTwqi3dea7N+lqmoO0/1FCJGBZbJtujw+pg4Ep6SyvnM2vgquIEbb TsE0nrgU9uu4gEpA0iI98ILECGrgE7lCqmSdpQhl1RM6GAck5lp1gDGYrtnEYq+2 6UiaUR4Tl1O70f6qmYBmOO4fUklhunS5R9Zir4bM0REF2t8uCZ8VRFn79/v8Vokz uWOXmbLm7WpaOd+tm9nnet4xZa+ALT+D4sBTQAiyk4r+4pD3yqMGUQ1HPRWhJg1X M6gp0Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4601r4pc06-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Apr 2025 15:22:50 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6B93B4004A; Thu, 17 Apr 2025 15:21:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 84E2D9927DE; Thu, 17 Apr 2025 15:20:14 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 17 Apr 2025 15:20:14 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 9/9] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Date: Thu, 17 Apr 2025 15:18:33 +0200 Message-ID: <20250417131833.3427126-10-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417131833.3427126-1-christian.bruel@foss.st.com> References: <20250417131833.3427126-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-17_03,2025-04-17_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 1b88485a62a1..a7646503d6b2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -225,6 +225,27 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&pcie_ep { + pinctrl-names =3D "default", "init"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + status =3D "disabled"; +}; + +&pcie_rc { + pinctrl-names =3D "default", "init", "sleep"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + pinctrl-2 =3D <&pcie_sleep_pins_a>; + status =3D "okay"; + + pcie@0,0 { + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; --=20 2.34.1