From nobody Fri Dec 19 17:38:02 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57E6E241136; Thu, 17 Apr 2025 12:33:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893183; cv=none; b=ZeOz0i/0Gy2814aCfwQyordyeEG6IrZ3Oxl0HBtjoDcnuMcg7cg33vB4wYmf3whTJ6RYXfBAxCWstEXqJeuOxW7Okp1QNBuzuBWvyWMOnA9DefvF424mmUcVFxATQSNDCxrRIv02SNH9qXBhpWMEktlmviTzTCElaAspcAKKgjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893183; c=relaxed/simple; bh=dl8MaZU3leKzK1L1L7aXKIN/C5N56KFI2svmf2Kd6h8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hneqnJJcGAPTVyM/behSlt3xQ2wIkDcp/4b/6qA9O/m7/Pexc33hSaXQjO8e50fdQ6JaPuQ0Ow95hH+WD0QrVR39vLQL5wr9UZMSU75rQDXP5yIJqyklw7Vj9bwtb6e55XgKg3wyvt8j//pSFwvJqLHCWMRs5izDxS6SF03io0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mWYB+3/R; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mWYB+3/R" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWt3E012805 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:32:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744893175; bh=7ZBx7XBwzbuQd5f6/XHwF4XsTBPD9vUPd4Q7f5xrshI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mWYB+3/R1aG6Bqxgn6sglszE6ud3xH7aET7fM8GQRgZ0YLWOQRtro7zUZsOC+DaiW Gv2jo0s7WCTRMTaA6n536j1OhbWb6J3OGs7OyXSrPbq1iXy3a7AFWgUoH0dT07OW2M IaYeZ8FtDH+oYb2FyqlJvejiUMTXcGr+cdN55GK8= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWtaP058769 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:32:55 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:32:55 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:32:55 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HCWkMP038275; Thu, 17 Apr 2025 07:32:51 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , Subject: [PATCH v3 1/4] arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1" Date: Thu, 17 Apr 2025 18:02:43 +0530 Message-ID: <20250417123246.2733923-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417123246.2733923-1-s-vadapalli@ti.com> References: <20250417123246.2733923-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree nodes in the SoC file, enable them in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support= on J722S-EVM") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- v2 of this patch is at: https://lore.kernel.org/r/20250408103606.3679505-2-s-vadapalli@ti.com/ Changes since v2: - Collected Reviewed-by tags from Udit Kumar . Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 2127316f36a3..0bf2e1821662 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -843,6 +843,10 @@ &serdes_ln_ctrl { ; }; =20 +&serdes_wiz0 { + status =3D "okay"; +}; + &serdes0 { status =3D "okay"; serdes0_usb_link: phy@0 { @@ -854,6 +858,10 @@ serdes0_usb_link: phy@0 { }; }; =20 +&serdes_wiz1 { + status =3D "okay"; +}; + &serdes1 { status =3D "okay"; serdes1_pcie_link: phy@0 { --=20 2.34.1