From nobody Fri Dec 19 16:06:55 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57E6E241136; Thu, 17 Apr 2025 12:33:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893183; cv=none; b=ZeOz0i/0Gy2814aCfwQyordyeEG6IrZ3Oxl0HBtjoDcnuMcg7cg33vB4wYmf3whTJ6RYXfBAxCWstEXqJeuOxW7Okp1QNBuzuBWvyWMOnA9DefvF424mmUcVFxATQSNDCxrRIv02SNH9qXBhpWMEktlmviTzTCElaAspcAKKgjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893183; c=relaxed/simple; bh=dl8MaZU3leKzK1L1L7aXKIN/C5N56KFI2svmf2Kd6h8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hneqnJJcGAPTVyM/behSlt3xQ2wIkDcp/4b/6qA9O/m7/Pexc33hSaXQjO8e50fdQ6JaPuQ0Ow95hH+WD0QrVR39vLQL5wr9UZMSU75rQDXP5yIJqyklw7Vj9bwtb6e55XgKg3wyvt8j//pSFwvJqLHCWMRs5izDxS6SF03io0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mWYB+3/R; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mWYB+3/R" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWt3E012805 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:32:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744893175; bh=7ZBx7XBwzbuQd5f6/XHwF4XsTBPD9vUPd4Q7f5xrshI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mWYB+3/R1aG6Bqxgn6sglszE6ud3xH7aET7fM8GQRgZ0YLWOQRtro7zUZsOC+DaiW Gv2jo0s7WCTRMTaA6n536j1OhbWb6J3OGs7OyXSrPbq1iXy3a7AFWgUoH0dT07OW2M IaYeZ8FtDH+oYb2FyqlJvejiUMTXcGr+cdN55GK8= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWtaP058769 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:32:55 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:32:55 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:32:55 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HCWkMP038275; Thu, 17 Apr 2025 07:32:51 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , Subject: [PATCH v3 1/4] arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1" Date: Thu, 17 Apr 2025 18:02:43 +0530 Message-ID: <20250417123246.2733923-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417123246.2733923-1-s-vadapalli@ti.com> References: <20250417123246.2733923-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree nodes in the SoC file, enable them in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support= on J722S-EVM") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- v2 of this patch is at: https://lore.kernel.org/r/20250408103606.3679505-2-s-vadapalli@ti.com/ Changes since v2: - Collected Reviewed-by tags from Udit Kumar . Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 2127316f36a3..0bf2e1821662 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -843,6 +843,10 @@ &serdes_ln_ctrl { ; }; =20 +&serdes_wiz0 { + status =3D "okay"; +}; + &serdes0 { status =3D "okay"; serdes0_usb_link: phy@0 { @@ -854,6 +858,10 @@ serdes0_usb_link: phy@0 { }; }; =20 +&serdes_wiz1 { + status =3D "okay"; +}; + &serdes1 { status =3D "okay"; serdes1_pcie_link: phy@0 { --=20 2.34.1 From nobody Fri Dec 19 16:06:55 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AA5C288D6; Thu, 17 Apr 2025 12:33:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893188; cv=none; b=tk5Hxl2Hrrg7N+KLCMv+7rP/ts1ywOTjoL+EOPLp++Oe+JX1Dpij/BwpdF9kpnoIaYfDaslpa0Bc23O6EqwozRrny6IdQPpXPQeKQbbXm7RsbATu91tCdJS4NM7eZe3TaIATbPJbpVJKbdd3J3Le9n9s0K0/HySjUCZrbGDkvys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893188; c=relaxed/simple; bh=GoMth6nibPfoAH5NDcIaLKvXnV5TFt4dC0M7QQ35z34=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lOh3r/U9V7sesG3mTID23vfMQTGrSNMBpvkQOK8T7zTvHmO3DSfHu6qGQC6+sgZz933L7IZFTXv2l4yjXwXc1v5GIzYW/PorZBdjzIbQLGU/HhPVB2tTohHldHsxDLKOeU7BW/qXIG+eviB/1bC55lZ1xkpTyq6U8oOQ/padsMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=FLoWsdlu; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="FLoWsdlu" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWxfi691237 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:32:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744893179; bh=agOmMDGyX+AHfGFpR6U+k5uDlDebQriePJ9/mg+Opxk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FLoWsdlu6LDrDvSkmCFFjmaetgueMKhbcOTIuu4q8QjrA2ngt9IXwuC9KjHId5Gm8 2ngoIo/HiTCLIxo8BEF8dLARkAtp3e3iENEq5XCR+LLWnr1eXW6ovVmuFrSUtffd7M W6CjoXz6u0RIY0TlNoHKACF9uuVlMK5oSFid+2DU= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCWxpt094092 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:32:59 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:32:59 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:32:59 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HCWkMQ038275; Thu, 17 Apr 2025 07:32:55 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , Subject: [PATCH v3 2/4] arm64: dts: ti: k3-j722s-main: Disable "serdes_wiz0" and "serdes_wiz1" Date: Thu, 17 Apr 2025 18:02:44 +0530 Message-ID: <20250417123246.2733923-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417123246.2733923-1-s-vadapalli@ti.com> References: <20250417123246.2733923-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Since "serdes0" and "serdes1" which are the sub-nodes of "serdes_wiz0" and "serdes_wiz1" respectively, have been disabled in the SoC file already, and, given that these sub-nodes will only be enabled in a board file if the board utilizes any of the SERDES instances and the peripherals bound to them, we end up in a situation where the board file doesn't explicitly disable "serdes_wiz0" and "serdes_wiz1". As a consequence of this, the following errors show up when booting Linux: wiz bus@f0000:phy@f000000: probe with driver wiz failed with error -12 ... wiz bus@f0000:phy@f010000: probe with driver wiz failed with error -12 To not only fix the above, but also, in order to follow the convention of disabling device-tree nodes in the SoC file and enabling them in the board files for those boards which require them, disable "serdes_wiz0" and "serdes_wiz1" device-tree nodes. Fixes: 628e0a0118e6 ("arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe su= pport") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- v2 of this patch is at: https://lore.kernel.org/r/20250408103606.3679505-3-s-vadapalli@ti.com/ Changes since v2: - Collected Reviewed-by tags from Udit Kumar . Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 6850f50530f1..beda9e40e931 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -32,6 +32,8 @@ serdes_wiz0: phy@f000000 { assigned-clocks =3D <&k3_clks 279 1>; assigned-clock-parents =3D <&k3_clks 279 5>; =20 + status =3D "disabled"; + serdes0: serdes@f000000 { compatible =3D "ti,j721e-serdes-10g"; reg =3D <0x0f000000 0x00010000>; @@ -70,6 +72,8 @@ serdes_wiz1: phy@f010000 { assigned-clocks =3D <&k3_clks 280 1>; assigned-clock-parents =3D <&k3_clks 280 5>; =20 + status =3D "disabled"; + serdes1: serdes@f010000 { compatible =3D "ti,j721e-serdes-10g"; reg =3D <0x0f010000 0x00010000>; --=20 2.34.1 From nobody Fri Dec 19 16:06:55 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10692309AF; Thu, 17 Apr 2025 12:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893190; cv=none; b=r/rQC5hPBt6d7dB8CT6vnGZCjKclHkfYKE4HRO0DQiQQz5OxyGn3uBCfHOTXidzO+YmebrNfc7n79d/MmU07cufRPZeabYUmxu7omPFRr3fM4C2k7waSrZ/v64pHe/vo60r/3D3TtN32To7IiOOXTuBfbbz6vlFCLvGhBE6i0Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893190; c=relaxed/simple; bh=fiokmJMX81yTpZ8kVCSQGA34fNWnCGfiaroSj7xQ3AI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Mlweb4W9/m8xd0yn+XDPbhKfLuPGMUPvmgdfqefeoJmND8FKEQb/nmFrsZZyip2OUthFK/eiVMPvw8PdRfVDAr2UHuVofHAQeRhMxXY1orqaFhTyjbHm+gpFj2jvxL7631gTCXfvbyPtda8Dluzch7vrtS8FQUrD1bDIZh4KXhE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=FvbcK3Zh; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="FvbcK3Zh" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCX3Ql691249 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:33:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744893183; bh=YBl3TCu3gksd6v/dkukzfiaNZG7cMAnJ/y7g/B6EaEg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FvbcK3Zhgv+5kAV0xygXIadBex/l1m5RHWJVKNpggspuwgK5y/oRaenVZvRCpZIOA JXl5Uad3L0c8fbq0XooF1J2r+woMlaA8De9bYj0RmLVVNt0RJrWNLyLybh3B3nOc+E BGkkra4XTd+i+8EisG+F6FJ08/HjVdUNKT2NwznA= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCX3mt094189 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:33:03 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:33:03 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:33:03 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HCWkMR038275; Thu, 17 Apr 2025 07:32:59 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , Subject: [PATCH v3 3/4] arm64: dts: ti: k3-j722s-main: don't disable serdes0 and serdes1 Date: Thu, 17 Apr 2025 18:02:45 +0530 Message-ID: <20250417123246.2733923-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417123246.2733923-1-s-vadapalli@ti.com> References: <20250417123246.2733923-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Since serdes0 and serdes1 are the child nodes of serdes_wiz0 and serdes_wiz1 respectively, and, given that serdes_wiz0 and serdes_wiz1 are already disabled, it is not necessary to disable serdes0 and serdes1. Moreover, having serdes_wiz0/serdes_wiz1 enabled and serdes0/serdes1 disabled is not a working configuration. Hence, remove 'status =3D "disabled"' from the serdes0 and serdes1 nodes. Suggested-by: Udit Kumar Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- This patch doesn't have a v2 and has been newly introduced in this series. v1 of this patch is at: https://lore.kernel.org/r/20250412052712.927626-2-s-vadapalli@ti.com/ Changes since v1: - Collected Reviewed-by tags from Udit Kumar . Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index beda9e40e931..562dfbdf449d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -52,8 +52,6 @@ serdes0: serdes@f000000 { #address-cells =3D <1>; #size-cells =3D <0>; #clock-cells =3D <1>; - - status =3D "disabled"; /* Needs lane config */ }; }; =20 @@ -92,8 +90,6 @@ serdes1: serdes@f010000 { #address-cells =3D <1>; #size-cells =3D <0>; #clock-cells =3D <1>; - - status =3D "disabled"; /* Needs lane config */ }; }; =20 --=20 2.34.1 From nobody Fri Dec 19 16:06:55 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39D52475CB; Thu, 17 Apr 2025 12:33:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893194; cv=none; b=rkZ5OdHJtrpZbVyO2czLOSuBiVp0no7GJa3yKRYrTU9BM7MaoAjeaA5s5IBUmVvt0//AoOdBLLsdQCzk1tCbMdTUaSl9neyEDeBO93dP4+8wFwx5XWWfslrt2fsZqZGc99ttihGTfWcJeBYThq+8pbVi6BVNxkhpz0GjgsKAuqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744893194; c=relaxed/simple; bh=X6223YWHrMIEQso4u+WKnZ8K13FEUMYwm+Nrt+W0btc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r9rklBlqlxIzA3io0i4ZErws5SRRdgmJ0+pclDTKh+KiFdl/H9C4IqVWtm1YhLXtFd/5JdyuSd0aCJIOmNKFJOTslkXdfHkeHNOlGJJwdITbmrNt7s4lMgp8qzbdeDJTwtLn5LJsVkPVc5WHNyPGU2wRxVDv414qddsMPKW0yig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=rUjTaU6/; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rUjTaU6/" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCX720012825 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:33:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744893187; bh=Xekzjocdp1MXjxXlVQ4pboSffMwk3za4212Kt6FsTKs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rUjTaU6/Tlqmug8e6VhP/FwzKQhdunlEhqq/t3ZPkIFCfcZ/wVqPTkLs9XXgjSk+3 VQj34lDQlG5hTryikrKP7Xda0+NEr9AaA4AzoYxT2RbTQkWvbmzQmUYp3TNpo0ScYL Oyps/6g0mZ30mwj4yUBip4jNep7IwPQUMdoXOBe8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HCX77v094247 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:33:07 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:33:07 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:33:07 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HCWkMS038275; Thu, 17 Apr 2025 07:33:03 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j722s-evm: drop redundant status within serdes0/serdes1 Date: Thu, 17 Apr 2025 18:02:46 +0530 Message-ID: <20250417123246.2733923-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417123246.2733923-1-s-vadapalli@ti.com> References: <20250417123246.2733923-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Since serdes0 and serdes1 are now enabled by default within the SoC file, it is no longer necessary to enable them in the board file. Hence, remove the redundant 'status =3D "okay"' within the serdes0 and serdes1 device-tree nodes. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- This patch doesn't have a v2 and has been newly introduced in this series. v1 of this patch is at: https://lore.kernel.org/r/20250412052712.927626-3-s-vadapalli@ti.com/ Changes since v1: - Collected Reviewed-by tags from Udit Kumar . Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 0bf2e1821662..34b9d190800e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -848,7 +848,6 @@ &serdes_wiz0 { }; =20 &serdes0 { - status =3D "okay"; serdes0_usb_link: phy@0 { reg =3D <0>; cdns,num-lanes =3D <1>; @@ -863,7 +862,6 @@ &serdes_wiz1 { }; =20 &serdes1 { - status =3D "okay"; serdes1_pcie_link: phy@0 { reg =3D <0>; cdns,num-lanes =3D <1>; --=20 2.34.1