From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CA07241693 for ; Thu, 17 Apr 2025 12:24:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892651; cv=none; b=ebZ9cI7+tIzi3gW9edO7l9MIp+DYQKa40G3bK38awNOXBtdn2UhrQi2hMXz/X1dOkhaRUX+zG9ZgQ/d9tjm2rHDi2ZrXEKi0lutlm8x4zRHEzYCyZ9MiC6tH96kmNnSysyHLkbj1NGsgSKXDWaNmARwBpz/qyXP+zC97oVvJhGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892651; c=relaxed/simple; bh=aFqX3fLDtG8cy76aRcSSCxbszjtqQl817f+Kcc6ZMK0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i1tPkeylwrpOPa78cUYvSF7pU/IKERR5IQJpXDv4HIfJCgySCML8lzy3Hx6jJdblJsSt2mt6BeV7XifE2R4/neagffpUpc/CeMvp9RUoklTEHcbmn4b9jqziXSs/t8RB2CGvCexCMLSUkJzcJIqAGFIFGjKuqPxriA/slVd0C3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=UUaIr5Vv; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="UUaIr5Vv" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2240b4de12bso10086835ad.2 for ; Thu, 17 Apr 2025 05:24:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892649; x=1745497449; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MqV/L1fucoXh0zEq3ZbEkv0iZBTOf63rS7eOzOMDARE=; b=UUaIr5VvnqnpwxR3b4Zv8M4q8rfT3fUQA3CCrOcZX7gn8rcfGVmlM7/Zyw6bsU/G/f szDiK5M+YjiZoofXT3zdJn3IVDmvZOHmvsTeidxVrwM1eS7833q9ME/pa3F0hXzwCx8a 7GkyvMsrEOKxDb7hc58I+VRxeDxykDrkMYGHNYO6Y5eJDMmdgGi+JH5MEj6E2ukp7Jk9 Z+ng5rJ1MaACj7AwJjEu+Z6t2aetDcOyew9nnYYE12M4cp9cjj6/D0UqfcRWrLAu6VCV xWrx+qYTu3EuF5Zl2jt/OA3bwwt4ROg6Qc8UnV0toQTQtnSLBTPxrG9iKBOgsliJDDtU 8jtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892649; x=1745497449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MqV/L1fucoXh0zEq3ZbEkv0iZBTOf63rS7eOzOMDARE=; b=J+0oiy+TKpEVR/dPlXo2ql8VQ/4HBrQlNznCNiL5tXHfcujHcFZmYqe/Q9HkYqTZ+k hdGg1c1QbAEE+OtH1xizAVEQYrmJU4X33fJzqF/qBMVk7X0A1TyUv/7MTQ5M0Ulkf7dp Q2y5dJF7YrA4vTZ81n57V5xHIZhd1br5br8iFDRXsnOkG5Lr6+sYD5sfqRwdTmRH7VoM 5i4BAJ0jh1hfRkYp4cdgOJ1izeCchLNLZpJD4SpgFvarKWrFBTh27rBYAwPIYo+ra7kB OX1tkLqFNBHsmEO5G3Jo5tNVdZRuoacG27EMy0FA6BJCCEkVIfsE+LPSNpdbjH/7tlhC 6T3A== X-Forwarded-Encrypted: i=1; AJvYcCXcsS/mknBZ7OvwzlDo4AOzpyaaMkxfv4Fcx/CnKkXp2vxv0+bgdFYESUUrF7uhXQHpOVE5mqn610o+m40=@vger.kernel.org X-Gm-Message-State: AOJu0YyaQAPJPBcGAnCX6AfroFKRXE0c9IjH0VB21P+wWGAakEn6coyp DOPPZiyy4jNLc0fN8r26SSoLz/ewZQaTmoS8pO5XYUsxznv1DhZmLMga08+N/nU= X-Gm-Gg: ASbGncuwObqfEGz1H8nSi3DIPFXm+42md37ru8u9nHR41RLc8wEoEZnQZn8R9qC7tp+ FyVt2/4EsBLQC8ITr95MMc/hQeKZ9+YcwDb9Uu7i+FIqaFWePJmEeI9EP4Zupaw54AzaqlABzaW 5MuIXL15rWzyfdPcx7vDOAaWnJ0hBMF5D8b45g+NJQdEiYAoMZ+HbKDYbsViAn7bgddL4YZhBxe PYb8N9Tx9O7RxLovoetKBJNWbRc6TcbrfYRGT/+uX28ayMHbSJHd3nsz70k/lxawyE27WXohj6Y rPWrd6wI+4BS41GBMdTNe2RpA+bbzYu9DyLg2yL3Hg== X-Google-Smtp-Source: AGHT+IFVHOWJJRAXEzH6mdZNYusO/nzJmHfPymZgz+gveEEgUfllUOzI6Ji7vwcW5uJ8Q3EqmqJGfw== X-Received: by 2002:a17:902:e542:b0:21f:f3d:d533 with SMTP id d9443c01a7336-22c358c542fmr78901385ad.2.1744892648939; Thu, 17 Apr 2025 05:24:08 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:08 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones , Deepak Gupta Subject: [PATCH v5 01/13] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Date: Thu, 17 Apr 2025 14:19:48 +0200 Message-ID: <20250417122337.547969-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Firmware Features extension (FWFT) was added as part of the SBI 3.0 specification. Add SBI definitions to use this extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Samuel Holland Tested-by: Samuel Holland Reviewed-by: Deepak Gupta Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3d250824178b..bb077d0c912f 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, + SBI_EXT_FWFT =3D 0x46574654, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -402,6 +403,33 @@ enum sbi_ext_nacl_feature { #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 =20 +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FWFT_SET 0x0 +#define SBI_EXT_FWFT_GET 0x1 + +enum sbi_fwft_feature_t { + SBI_FWFT_MISALIGNED_EXC_DELEG =3D 0x0, + SBI_FWFT_LANDING_PAD =3D 0x1, + SBI_FWFT_SHADOW_STACK =3D 0x2, + SBI_FWFT_DOUBLE_TRAP =3D 0x3, + SBI_FWFT_PTE_AD_HW_UPDATING =3D 0x4, + SBI_FWFT_POINTER_MASKING_PMLEN =3D 0x5, + SBI_FWFT_LOCAL_RESERVED_START =3D 0x6, + SBI_FWFT_LOCAL_RESERVED_END =3D 0x3fffffff, + SBI_FWFT_LOCAL_PLATFORM_START =3D 0x40000000, + SBI_FWFT_LOCAL_PLATFORM_END =3D 0x7fffffff, + + SBI_FWFT_GLOBAL_RESERVED_START =3D 0x80000000, + SBI_FWFT_GLOBAL_RESERVED_END =3D 0xbfffffff, + SBI_FWFT_GLOBAL_PLATFORM_START =3D 0xc0000000, + SBI_FWFT_GLOBAL_PLATFORM_END =3D 0xffffffff, +}; + +#define SBI_FWFT_PLATFORM_FEATURE_BIT BIT(30) +#define SBI_FWFT_GLOBAL_FEATURE_BIT BIT(31) + +#define SBI_FWFT_SET_FLAG_LOCK BIT(0) + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 @@ -419,6 +447,11 @@ enum sbi_ext_nacl_feature { #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 #define SBI_ERR_NO_SHMEM -9 +#define SBI_ERR_INVALID_STATE -10 +#define SBI_ERR_BAD_RANGE -11 +#define SBI_ERR_TIMEOUT -12 +#define SBI_ERR_IO -13 +#define SBI_ERR_DENIED_LOCKED -14 =20 extern unsigned long sbi_spec_version; struct sbiret { --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67CA5233120 for ; Thu, 17 Apr 2025 12:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892660; cv=none; b=e2jvxDFaSPaH3x3JkLkPLs+b8tp0uxKqPdswxrd5rHAHYTZPc/+IyFXgyatgyNc5kN31b61X5v0BOxmPFS+jMnJhpI9LVaMQxtNd23r3ib18pQG9IFDLqGv0SzQWM71BdjgDzkQ8YZgEQxeezVGzJDOgO2S4s5AoB27OdBWGNhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892660; c=relaxed/simple; bh=I8q3a/r8sIPwl9ULO4heNHCAxh6RA5hJvMvMHg5vqgk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H/aXp/t0aYfcmyZ8VASaMIeCcBX5oV7hl36w17HQXOK+zPQBsMpV+H+faBAvWAXRk8sxEg5zWtPcqSht0P3shLoIoByGpstfjDNG3eEBIKg9OSCs2YdIk/agKUJAEhZqZk18NclEfIefnqaHuY6iIe/jwNH7XCTnewCSnZDCKHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=YW0Pekvc; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="YW0Pekvc" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-227cf12df27so5488475ad.0 for ; Thu, 17 Apr 2025 05:24:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892658; x=1745497458; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kJ5IZYf4f1NhGHvFycXXpF/34tAS76qwhFgvuPH97UQ=; b=YW0PekvcepDEL3CNBicFspmuytgnbXMVpYVkMaHix670fEShFT+lc/mMY0iZaPCPQ/ yuULSJXL6H9WfDpXS56vKkOXAN4jcZcLjPzuK9xue0TvhToXId5IztsN0w2bwF76Lwx3 QeEHZPVkkKogjpcIp4MybW89Vi1RQaz+2xvecAH19RpZWagG4Eq7HSoTomUxYB05Z3Pi 6rcLlbwTKsOadpEq4J4yLGQYSYWMa/0yWkEd/lqrQu8tyJaLiWXAjgcR+ACWhkQXIDQ8 p5zBgLCLZJZqGUbZPKgeUjC2pIMq27dMoJ1XtTQf6297sUp5umm3RoEEbl5L0XvNXeqr 5ynA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892658; x=1745497458; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kJ5IZYf4f1NhGHvFycXXpF/34tAS76qwhFgvuPH97UQ=; b=b8QQ+9I2xmjFM1igb4L9UErsW/355UEf4l3jeTdJWQTZnMYVURaFiJqr5RusVyjjvl Qhl1AEDNhXaOPLaxbD0ihgq4ZvVs5wy810eGC0l/5DfHCCo/9krA411ILlLamBwGvZK7 5fW0HEhZYrHZTXN2v2KdD4n78/+482v6YrUsGKpQ9dZ0lZNjIcPQZVE/2Nkc9Y/5k54x xKwo/Wd2w5Es1LcWMpGJCcEWws9vVwOgeuZMPpwRZsAXverKdkl0/yrhkECqYW6+E8Ci Zq/31mMsmoxGlFwOtnohQts+9W8ikJmUQB1PSNWOxuJrsRHl7DazoI8dkZNO42JH/wxl /igA== X-Forwarded-Encrypted: i=1; AJvYcCWbBC0G1aN2Myxup2D4vTFDZVcMJ17njjKUydvZLCRAi37s3/V3/+HmVbeRyq6DML30cFTWmTSqe1CIHJg=@vger.kernel.org X-Gm-Message-State: AOJu0Yy3XAGDBmf8IBAB0OrSazaAL/4uKoCARauVLjpAN0efLuZRKeWM UPS7/yp9gHEmbuQhsOCRbUIm1MqPVJ712sbxkUK+t3CGNEPQpML/pbb7jub3JAQ= X-Gm-Gg: ASbGnctnVDm7gYjrRQlQqo8RO6ec/ZK/7DGBO/YGPnWY9JyouX5bdfksbAyivGQyh+e Dop7yUVdneFbRwbHx7Xww7ntMQHJfs/8kn+3x/L/f2E9FIgy5an/s6r7d4di3G638ru2uYmpQ+l O4vZNeOda5SZYzd048gmqcPPeU1j1AAKHTCn+Wy3ehLa/Jg3xtDpF2cvWe/Ut5s27FwXXzAazqE pgKEMLbitpV9AhT9UeemMuxJBVzD+B1E6muqEEn3kKsv09zzUbLtoL+Y4dg+lTXqfi5peuHpdbW fVLysCUEIwI86MnvUg8BTLtrtVoWGZSVV2DlREKYbA== X-Google-Smtp-Source: AGHT+IE0XjCz5TtIm1U/KycHsULkn93MfV8ZJ4DCUOeKjh64BtT2X4MD7ZC1hijUVKkaUKvQHFj5ag== X-Received: by 2002:a17:902:f642:b0:215:9eac:1857 with SMTP id d9443c01a7336-22c4196f564mr40963855ad.5.1744892657640; Thu, 17 Apr 2025 05:24:17 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:16 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 02/13] riscv: sbi: add new SBI error mappings Date: Thu, 17 Apr 2025 14:19:49 +0200 Message-ID: <20250417122337.547969-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable A few new errors have been added with SBI V3.0, maps them as close as possible to errno values. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index bb077d0c912f..7ec249fea880 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -536,11 +536,21 @@ static inline int sbi_err_map_linux_errno(int err) case SBI_SUCCESS: return 0; case SBI_ERR_DENIED: + case SBI_ERR_DENIED_LOCKED: return -EPERM; case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_STATE: return -EINVAL; + case SBI_ERR_BAD_RANGE: + return -ERANGE; case SBI_ERR_INVALID_ADDRESS: return -EFAULT; + case SBI_ERR_NO_SHMEM: + return -ENOMEM; + case SBI_ERR_TIMEOUT: + return -ETIME; + case SBI_ERR_IO: + return -EIO; case SBI_ERR_NOT_SUPPORTED: case SBI_ERR_FAILURE: default: --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13D9B2459FC for ; Thu, 17 Apr 2025 12:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892668; cv=none; b=Ex+TJFPdio/0B0pjBi88jixw/ne5TgdyDsnszfRCXwSRlp40kD6jh8PW6jsOcDhqAaqDOF5xoLMm8RDzijCJkFLT6j5pSUquRLwqSFIX3414fzuZ9lUTVjdTbl53T0O7KSR44SsRtuYA2Vd3xnFSaz8Up1nmw+Ntb5AJk9Lb8n0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892668; c=relaxed/simple; bh=rwRlud77zZk3mXpiZR5trvliX9LoFQHKA4NpcmZaFMY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lOzTFtxwD/+Lyb+9Tb4FhD9Rt3RVx4Z9n2he6pnWkShadoSMIh1O/rRm+PJIXJge1xsZM3YD0Dy2LJXsg32aqdhYhLYz/9gEJQ1o/STJuN57OtvU+DsBalTiTJEfVpcbrx9iYUa38cR/hMCVeiKxtEvp7kbt/uP87FWbCnbrVts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Dr96eSTY; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Dr96eSTY" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-22928d629faso7144775ad.3 for ; Thu, 17 Apr 2025 05:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892666; x=1745497466; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aNrGkE8UCKSxhi8ZHI6AhhtBeoQ1iixkNI02GQVKF+0=; b=Dr96eSTY1vKUBiIiutyEoOwj2O1wLk8Lsa9lxrkkUcA4XXzdec7bawfqQLhecKi5+8 aGevVBPIhUHEk2yOjKLrz/wcvuFfVRw04oAOVDp1Y8Warde+0TlTgfRG2rJr38hP3rT8 Ba3ia3b6c1JWH2b2+R1KGCiaGVcefE1eNpCJRsqWuGvveEO9pq+YvmjpXfYL0gVayb5X lgl+s/3TaWVR/sk82J/Lfp8m6UrA7wq3j2yib0wCMq383OzsKdttR+PayrpIhtgliB2H VD2pv4UzkecJzTjGyHwdUQPYcbLmN/q/S1YAOO1QOaWyUVkhgmcC1GA0CB7pbfV6eq9n d91g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892666; x=1745497466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aNrGkE8UCKSxhi8ZHI6AhhtBeoQ1iixkNI02GQVKF+0=; b=STxU5W/e9GiuZCurW9swnJ/lcljL0MWb3+lHwGDNPBrUuMu9C4kBmHCgsgVlTL/IwC /bTObORwVge0x7VbZK8wtuCxINugVpZTjnKxqATmWPp1I1rLfBF610q2KeX1yDg/2G+h Q3AO9JdbvA5/9IN3Pa9lHNE8m975sfmfQN13FnHn+yEy2BIzsHScFp0yFb8HYlwF5TRU 8voPCxh0XygwSVVVhwRSXS39kHbxeaIBvNEYa4Qrs/E11IiWZV3GAiqLzAYmhTGdvik+ 0xdXiMJSsLTID8uOarz/6x7froDxC5QqL7AUPr++qnc+vxIbHKKmUjA+b3WRS1EWuQY1 dIKw== X-Forwarded-Encrypted: i=1; AJvYcCU9GBzwUORaguT8u7Ky6T4RkBZAUpZ3AX9qOHR7QIlUZ/gxLSzfjWKjnEQI5zH8DNQfXySgF9GALyRIkWw=@vger.kernel.org X-Gm-Message-State: AOJu0Yyc+mIgGnlImieUo7hAD9FpFsgJjoNSb/nE8hlcwsrr7npT5e9H ZGJBW5sIEPKl9tDRymO5oY3JcqfdLxzxrod7Twcj3Ec0EKU7RwhMV/MOPUE7wjI= X-Gm-Gg: ASbGnctpOpp7LlNlR4pb4U1QmzK7aJoh1heU7pAGAj/Ynaswh3J73DsqCdc3g2YHOLb qx9OoLMs7/zXjKVkBKQqPZpSVHg23zKbM/YGbbFjWYHdej25e4JXlHyFlZjrsOGwShX9Mtfh8vU eIFvQiC3+EKcJcyCawAZRDt1jjuyEbDRPZ6g/XUBKnIRXUaNOhkUZfzctR//pXxlEVi+tvBF0rx 1YSKT6eEQCeKsdWgGJPe4cJdg81JlteS9cv/w5VV6TYcG0tTDPQmMJGL8Mpbcnnw6oJwbVAdOrf jJ+WpqxGGKy48W/hSz0I0Qcc/TskGwnj2/webQ/DKw== X-Google-Smtp-Source: AGHT+IET2FSN43B29b1iFIUfRnJqfxIL6IKEzFKmLMBZtkj51fE5xgUwJd+gTUEP7A/af82ElzoqFg== X-Received: by 2002:a17:903:1cb:b0:224:721:ed9 with SMTP id d9443c01a7336-22c35981e16mr85524135ad.44.1744892666322; Thu, 17 Apr 2025 05:24:26 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:25 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 03/13] riscv: sbi: add FWFT extension interface Date: Thu, 17 Apr 2025 14:19:50 +0200 Message-ID: <20250417122337.547969-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This SBI extensions enables supervisor mode to control feature that are under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp DTE, etc). Add an interface to set local features for a specific cpu mask as well as for the online cpu mask. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 17 +++++++++++ arch/riscv/kernel/sbi.c | 57 ++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 7ec249fea880..c8eab315c80e 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -503,6 +503,23 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *= cpu_mask, unsigned long asid); long sbi_probe_extension(int ext); =20 +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags); +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags); +/** + * sbi_fwft_local_set() - Set a feature on all online cpus + * @feature: The feature to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +static inline int sbi_fwft_local_set(u32 feature, unsigned long value, + unsigned long flags) +{ + return sbi_fwft_local_set_cpumask(cpu_online_mask, feature, value, flags); +} + /* Check if current SBI specification version is 0.1 or not */ static inline int sbi_spec_is_0_1(void) { diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 1989b8cade1b..379981c2bb21 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -299,6 +299,63 @@ static int __sbi_rfence_v02(int fid, const struct cpum= ask *cpu_mask, return 0; } =20 +/** + * sbi_fwft_set() - Set a feature on the local hart + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) +{ + return -EOPNOTSUPP; +} + +struct fwft_set_req { + u32 feature; + unsigned long value; + unsigned long flags; + atomic_t error; +}; + +static void cpu_sbi_fwft_set(void *arg) +{ + struct fwft_set_req *req =3D arg; + int ret; + + ret =3D sbi_fwft_set(req->feature, req->value, req->flags); + if (ret) + atomic_set(&req->error, ret); +} + +/** + * sbi_fwft_local_set_cpumask() - Set a feature for the specified cpumask + * @mask: CPU mask of cpus that need the feature to be set + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags) +{ + struct fwft_set_req req =3D { + .feature =3D feature, + .value =3D value, + .flags =3D flags, + .error =3D ATOMIC_INIT(0), + }; + + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) + return -EINVAL; + + on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1); + + return atomic_read(&req.error); +} + /** * sbi_set_timer() - Program the timer for next timer event. * @stime_value: The value after which next timer event should fire. --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2FBE24500A for ; Thu, 17 Apr 2025 12:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892677; cv=none; b=k/+V+WIxcp4uM6dRLuHZUr02Z5w/u+zu4S3B0cqXHdmnRguzjpK7LHMnVBQt2KluzgNAU4TDCQLcmVrfVO0sNXooJSAURNEZVuSXYzDPjwlFePXjOfT9fxqzOWhH902nkS5IrUNrR+ANMmpiRWq6s5VYEPAp4lJhljyntVNRRn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892677; c=relaxed/simple; bh=qJu1m4hx4nbu+oDFlDHA2hR7AvuynQAz0skV827DhvM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RK8li1Q8t3mI4xHjJsFkHdbjWsNC7xDjtEYPu4KVBfwysgWVPsgw7FTvcCQPUQgiaqMDEQy/1KnP12vxoIgXWZsi6hV0t8OynU4Go/sTIqqbnllB7nrldKaibEL/IXZ6lUD176j6icLV+R84lEf/bzeBZxuUfQA8kgnt3XiYI3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Gvcv5E0q; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Gvcv5E0q" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-224191d92e4so7402725ad.3 for ; Thu, 17 Apr 2025 05:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892675; x=1745497475; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DkvRtqiwpGFu2F2LneoosRxgLPIUe40LOw9HI4KIxXc=; b=Gvcv5E0q7WqcEvNo6Eg5joSeG01Iyyd0lKPavaMmhHr3u+PWN0xV4mFwfqRmSAB30o qUA/7LCPqp9+QlScp8y/95J/eJVwK0D9OOeSI+nioht74bY6oFljLxmg5DfM30v+BIgc HMtT4jD8vCrKvRau9K9pGlwr4rM0LIkBcAnnTeei9YX/fLZVzAFVztfaej6wQrqlhMLr sNlD+LX94iVvxutP4h3nLBAFrgSwiCLj3JTa7dOt2qVfnjEjR+aIuwugOicZriRCSGac plf9mnYgKJMqhWn5eQHTdulbIo8C/gL8d9/wX8ZCjUPcHzDFbq/GCc2rGkQL+YL0hhEC iTYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892675; x=1745497475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DkvRtqiwpGFu2F2LneoosRxgLPIUe40LOw9HI4KIxXc=; b=m68AP+Pyio3HcXqoeJl9GquNiYPbNbPZ7lmqnls85nuIFMYvva0Yki/OK+YfIEec1h IkKp4SLKDcsN+w48q6bB8Ml9P1USdfrWXeCMpQSW04qgNyGqGb/0XzPyl8MlFkDOCfjV uoPpbAW6Tp1/xDxGH6kC6kK/pAVbQLQNSeb56qB/ZjNw4V/PBZ2HJcsCSomVjKIQDXKA 3K7GbqMMAkegBtwxhZ941sO+FE+uMZWbdIB2HzA7domc5hLenZALQQ5LdSWQk5olQqlD IxP/bVAs+KO1SZLgmqg+ywb0jsf30Szq2mY1ywVzjI23anbcFmVROdKT4b0AQ2TtZRc1 GGYg== X-Forwarded-Encrypted: i=1; AJvYcCX+TP7xI3piONoC1Winf/7fyDXRBY1KaULLKRmAgdkKibliK+SS1WtcTcCMC+HKSteSgIqkRFj9x6mEe9E=@vger.kernel.org X-Gm-Message-State: AOJu0Yx8qiEOghWsA/NFuDFwFGtiBdkNtA1Te8eByqkkaNBznpSCstvU gmiqpnTXFM9vnaUwEznVYWvoIZrP8PkRVxj+Pa+ZLd/0zz5wfkf1r7fQ78/SRh4= X-Gm-Gg: ASbGnctofRm/MANfGX2p8ZI7BG+Z6hzlMIpIIkX8ckrRtQXsnu2dq6XO/gVJhWou88H kua6fgsYwc8ERH0qbGUwHmEjKDTBYXOz4lXCzytd7gISdG/Nmp7EhUL/w8O2q3hTCE0MwB7abtQ E8qWAWWfUXPkmeK3gdKsbTy16wzFYG6KmTQSMBmz8SKrp2uNKkRj3R8sIXGZUu8pFS3fk92TZ6K vdLCkhsLwW4x3TzK537ogAW5C5cpuKDt4efP2orumT9adqfS/i1/ohwO64InXMyBtqzDtgmtQxv v3l1E+NvfWJFv7abOilyWehjbUgXgzzIh5N3VRKdDw== X-Google-Smtp-Source: AGHT+IFwoPNkZRHRLCRUuOqGDF2uiHAGyCvd3q8quDmBUyk1f/F/4WvIpLrbGYXfNhaC6uEF0f4feg== X-Received: by 2002:a17:903:2447:b0:227:eb61:34b8 with SMTP id d9443c01a7336-22c35916f13mr99932925ad.25.1744892675059; Thu, 17 Apr 2025 05:24:35 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:34 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 04/13] riscv: sbi: add SBI FWFT extension calls Date: Thu, 17 Apr 2025 14:19:51 +0200 Message-ID: <20250417122337.547969-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add FWFT extension calls. This will be ratified in SBI V3.0 hence, it is provided as a separate commit that can be left out if needed. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/sbi.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 379981c2bb21..7b062189b184 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -299,6 +299,8 @@ static int __sbi_rfence_v02(int fid, const struct cpuma= sk *cpu_mask, return 0; } =20 +static bool sbi_fwft_supported; + /** * sbi_fwft_set() - Set a feature on the local hart * @feature: The feature ID to be set @@ -309,7 +311,15 @@ static int __sbi_rfence_v02(int fid, const struct cpum= ask *cpu_mask, */ int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) { - return -EOPNOTSUPP; + struct sbiret ret; + + if (!sbi_fwft_supported) + return -EOPNOTSUPP; + + ret =3D sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, + feature, value, flags, 0, 0, 0); + + return sbi_err_map_linux_errno(ret.error); } =20 struct fwft_set_req { @@ -348,6 +358,9 @@ int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u= 32 feature, .error =3D ATOMIC_INIT(0), }; =20 + if (!sbi_fwft_supported) + return -EOPNOTSUPP; + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) return -EINVAL; =20 @@ -679,6 +692,11 @@ void __init sbi_init(void) pr_info("SBI DBCN extension detected\n"); sbi_debug_console_available =3D true; } + if ((sbi_spec_version >=3D sbi_mk_version(3, 0)) && + (sbi_probe_extension(SBI_EXT_FWFT) > 0)) { + pr_info("SBI FWFT extension detected\n"); + sbi_fwft_supported =3D true; + } } else { __sbi_set_timer =3D __sbi_set_timer_v01; __sbi_send_ipi =3D __sbi_send_ipi_v01; --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76AA424A062 for ; Thu, 17 Apr 2025 12:24:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892686; cv=none; b=ktgcZvV9zFJgoA+jomffczdx7a+g5K6g3UudXx7s9bex14KrNDgS2FPiJWGvadWZYzlUHmoSZ2VIrx9KWfXDeGDDnB8jY1QUBjBaf00A352ILbF9lrc7axKG2Id4ScE1QtCVmoarldmnmaWD3reU6oUTtN14Pn4x8Prn2off6Gs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892686; c=relaxed/simple; bh=rbdsRD0AuDfdqVGoo+Md0aUA1Wflf8NIwMFM/Sb6wIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QtKaNtsw+a94/m1DGXs3JRwnT++mrJU4sdN4C6xfFJEG2dsFbmHc50Ectd35a6vYcqMhpVs81X6AY5D4uKodh/1utW/o9f01kHWVFTHG+Db1Xp5bOxnhCz3UdrB+CfJHx5xgSj9g+mJ2PSFRIF8aqgCBJ1tUuIP0kZ0wtsj7ZWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=XAbYuEv6; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="XAbYuEv6" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-223fd89d036so8219885ad.1 for ; Thu, 17 Apr 2025 05:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892684; x=1745497484; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZffLnUvyDxY5lnr7nm4ZxhnqMm5pHoMLqJFCY6yvcnE=; b=XAbYuEv6VwYQ4ypK/XHXKi+ezIXrA5F/9jh+DBA5vjpeP7eUKLO7jmNLUMC/Tnqe6H XZUnXfCGY8QdDAYBkxL2Ir0msIfRcmgj4ZKqXi9o8jUucH2sHBP6PRleVVMKXEsqvFGJ 3wZLYwjpPGQ7LTxKbOp+MEnXXmeje/aiydcoxyXQ34Xmu9IL7h2hdW274QbjGIAUI9uM 70zKbaTYbqueWlORefbNKdmuOBAKCCJFLeqYIPRbtQYCs/JZWwBntf4mD52Y5FhCwpgu PwdPmi2mzG/qrSINDh9rQPor8mzNo4/+dd+tFECPuBRoneapMbddCmVHZhx6g0yClGyP ynLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892684; x=1745497484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZffLnUvyDxY5lnr7nm4ZxhnqMm5pHoMLqJFCY6yvcnE=; b=UtJuEEwW3y+67pMlNwEvz4OhvwyA+082D9m7xeS27CRd4lVliHx8gjeZTZIg8ezmhA IUUWWtSQn2t7q7ZJghkZHZ7EnscrbcwmF/h9o/5ArNb+nZJ25R7lS2fJW5Aot0E7gEiJ aJC0lMGwLOlWZAzd4TxRGnvMQyJUHPkLWST6SEn6JCYJueZodfNvPH34D4uftsfWv+xc RYjSBXhqqjQLAMNGK+uN9h8+mJuMkGzZwZPeH42npyqLZ40GcYmkDMFeFNGoe4p05cJG 9yVIn9BdEOdvwaF0q4vz5C6rAEqWfRGt0O4JEwt1o+uwocJrbL3TMJt+71h2B1CuosGa F8KQ== X-Forwarded-Encrypted: i=1; AJvYcCUC0rKxFk8iK3GPezM76c4LPryh0Kdc6tOh2Btav3MI+aSUxkm13voI/qiHHfHJ0NFMh7KHIzslZHt28Nc=@vger.kernel.org X-Gm-Message-State: AOJu0YyInzgOs0F+EuBW/vpwzCp2jY/rC2QkCS0knejmsyAoSYlg09p9 3FlVfzACsWlbFdAkZaORkOmZ+QXQhtecZi5d4OjZ/uljKzYKpuEsT4WGcU5cLvo= X-Gm-Gg: ASbGncvk+RDgjXh7K2PkyyIwurDUdWlgR39UFO/aJOpu/QrMkJDbbIlStWY1KWVPOZz aswRH04g5yWlEngctZg05l/2kQPebRbHlBwaJgox/4lXzgVsSH8VL+7BvwAm2TMrY+pQsMyf7RH OZJgMERfkuZ4WdEyPu6x805i/mgafKXkOFWxgXCh175Fg0oz79yPCL6wKprFU9FTBq9Ck1Rh6xR qer2pifRWA8WrErS4lRRLjz+7pC7iM5/34J2lFfjnEHFHXFMiKnyP3LH+d8Rk3k79rLdodfvVeW fibAvcJXzaCuuDwMoJac6KnGhnSAFmtu8oyyUPe0qQ== X-Google-Smtp-Source: AGHT+IGh/BYwkefJ9AAON/g15uIjE6Ad6rojhY99Eh6G81EOlK8D2lFOXm78WPt4vUtVQfXYtoHamQ== X-Received: by 2002:a17:903:2f83:b0:21f:2a2:3c8b with SMTP id d9443c01a7336-22c358c5d8fmr81179515ad.11.1744892683747; Thu, 17 Apr 2025 05:24:43 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:43 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 05/13] riscv: misaligned: request misaligned exception from SBI Date: Thu, 17 Apr 2025 14:19:52 +0200 Message-ID: <20250417122337.547969-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that the kernel can handle misaligned accesses in S-mode, request misaligned access exception delegation from SBI. This uses the FWFT SBI extension defined in SBI version 3.0. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 3 +- arch/riscv/kernel/traps_misaligned.c | 71 +++++++++++++++++++++- arch/riscv/kernel/unaligned_access_speed.c | 8 ++- 3 files changed, 77 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index f56b409361fb..dbe5970d4fe6 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -67,8 +67,9 @@ void __init riscv_user_isa_enable(void); _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _valida= te) =20 bool __init check_unaligned_access_emulated_all_cpus(void); +void unaligned_access_init(void); +int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) -void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed); void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); DECLARE_PER_CPU(long, misaligned_access_speed); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 97c674d7d34f..058a69c30181 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -16,6 +16,7 @@ #include #include #include +#include #include =20 #define INSN_MATCH_LB 0x3 @@ -629,7 +630,7 @@ bool __init check_vector_unaligned_access_emulated_all_= cpus(void) =20 static bool unaligned_ctl __read_mostly; =20 -void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed) +static void check_unaligned_access_emulated(struct work_struct *work __alw= ays_unused) { int cpu =3D smp_processor_id(); long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); @@ -640,6 +641,13 @@ void check_unaligned_access_emulated(struct work_struc= t *work __always_unused) __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=3Dr" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); +} + +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); + + check_unaligned_access_emulated(NULL); =20 /* * If unaligned_ctl is already set, this means that we detected that all @@ -648,9 +656,10 @@ void check_unaligned_access_emulated(struct work_struc= t *work __always_unused) */ if (unlikely(unaligned_ctl && (*mas_ptr !=3D RISCV_HWPROBE_MISALIGNED_SCA= LAR_EMULATED))) { pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)= \n"); - while (true) - cpu_relax(); + return -EINVAL; } + + return 0; } =20 bool __init check_unaligned_access_emulated_all_cpus(void) @@ -682,4 +691,60 @@ bool __init check_unaligned_access_emulated_all_cpus(v= oid) { return false; } +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + return 0; +} +#endif + +#ifdef CONFIG_RISCV_SBI + +static bool misaligned_traps_delegated; + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu) +{ + if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && + misaligned_traps_delegated) { + pr_crit("Misaligned trap delegation non homogeneous (expected delegated)= "); + return -EINVAL; + } + + return 0; +} + +void unaligned_access_init(void) +{ + int ret; + + ret =3D sbi_fwft_local_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0); + if (ret) + return; + + misaligned_traps_delegated =3D true; + pr_info("SBI misaligned access exception delegation ok\n"); + /* + * Note that we don't have to take any specific action here, if + * the delegation is successful, then + * check_unaligned_access_emulated() will verify that indeed the + * platform traps on misaligned accesses. + */ +} +#else +void unaligned_access_init(void) {} + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) +{ + return 0; +} #endif + +int cpu_online_unaligned_access_init(unsigned int cpu) +{ + int ret; + + ret =3D cpu_online_sbi_unaligned_setup(cpu); + if (ret) + return ret; + + return cpu_online_check_unaligned_access_emulated(cpu); +} diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 585d2dcf2dab..a64d51a8da47 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -236,6 +236,11 @@ arch_initcall_sync(lock_and_set_unaligned_access_stati= c_branch); =20 static int riscv_online_cpu(unsigned int cpu) { + int ret =3D cpu_online_unaligned_access_init(cpu); + + if (ret) + return ret; + /* We are already set since the last check */ if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_S= CALAR_UNKNOWN) { goto exit; @@ -248,7 +253,6 @@ static int riscv_online_cpu(unsigned int cpu) { static struct page *buf; =20 - check_unaligned_access_emulated(NULL); buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); if (!buf) { pr_warn("Allocation failure, not measuring misaligned performance\n"); @@ -439,6 +443,8 @@ static int __init check_unaligned_access_all_cpus(void) { int cpu; =20 + unaligned_access_init(); + if (unaligned_scalar_speed_param =3D=3D RISCV_HWPROBE_MISALIGNED_SCALAR_U= NKNOWN && !check_unaligned_access_emulated_all_cpus()) { check_unaligned_access_speed_all_cpus(); --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB4B24BBF9 for ; Thu, 17 Apr 2025 12:24:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892694; cv=none; b=ruOpVJ6N4EnES4p+or/jFnUgjA85Bi7xHRpf0CWdAQ+vvgW0l6RmAKEiYJiIom5BZCcQHKpInfU1qd4ki//al3ebXibykaSJ3SFbeEPmWBy4tm9SWf69ICZOvNsX6bPIKZz528f7/NKDupQsxZB9VDBB5PhV5IrBN74LVZJ9mX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892694; c=relaxed/simple; bh=bRiCyLVUVK7d4rz7Vi4ci6OEXpinPX3bNStrcUxvF1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jpJBnLl2eaDEWJotOEzcycH6gmIGxGius2FCBkPeDHwwFjQwMfbh08/fGrYcwXtznFQlvDgBHPgrexosNHUW69jCed2IG4CuoRvD3IPGL4hk1rQSaMWCT9nEuhhbo7NNJA8bFG4hIssCchMrOh+ZCSEwiXK2Vln4fY1I4O9ktTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qiwDCHH9; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qiwDCHH9" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-223fb0f619dso7937395ad.1 for ; Thu, 17 Apr 2025 05:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892692; x=1745497492; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UzbGeZkhDryHTbPMrJ1IX4plytmQ+QFf0x8BSly6zWo=; b=qiwDCHH9j/+kBo7QKWgWYzQx+FT/gH4a+/q5Mp2YLT9t+UpUxEmx3S+itJFsuY80ET 92gT9rLZ6TjvFfYborp51BSMQwzveu5TUv+wHnC4W7cpzK6jWefSAKdnbWlwobzcdWWw xOyifAv4Txz5EOUdFiAGhPRjisUcwIMcHTloxF7/wh58shFpGBGbSRevXIap9NTDTJMs LXAXLimStKZ+sqNy6FJ1x43C4Upx8UDCMbpdsT5QbpGMrKhOq1kn09wN++EN8U6iTdjj zIzmgy+3b5KFanLAr0e4ac5X7sf+ZnRZlTR2mO/wFhqkyYqLkuVvqgR53XzL7bw/lPWJ PyAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892692; x=1745497492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UzbGeZkhDryHTbPMrJ1IX4plytmQ+QFf0x8BSly6zWo=; b=GF6ScxSq4jyAcHjdg1SRm7k78VlITb5642hEYvrJ8Jqy5Vb5xtAZgPe2hbllzmvJWq JhciDTNLSvooqu43I1UwWDuF+yKWZtlGaD9ZrmFvTHWQJSUKkG7Wyr4hECMpr++gOjnl RayetS2ZE2J2vWwOvsWGfsXDJ68Nlowzr930arSBAPNjvFvyHX39sp4hpepPWvKx1QS6 dCCBP5Sioi5OPY1z0MF1+xsTQekzWnwedtDPjVgA35MR/3HrZWPkwSQyqcloEzDa8S7F 0y0sNCQEnOTzm70vtGpJKa7YtlQP1QMYxV80xsi5Z12QV6y6hyiRu4Hu66hpSHlbxyec cAJA== X-Forwarded-Encrypted: i=1; AJvYcCV/xYB87/jYcWVRvqs2+bhiqi3mSO1wXmdhYFiNhZZO0E1i6Okn22GU46m7NUwZ5FjxJbasVRRpwq9uHtE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9PQqPimqxo7ySfOcwI8jomzKbfnl28U9YnazBw2s5bU5atiT5 c0yr7EvawWHVwwHC3RxjtS4AKBsKsMbbKpkc96anwMBcTvJj5dRiomMFkdjnpbU= X-Gm-Gg: ASbGncsHZ96qXZhTm9ArBD6QySMcO/vo8NOfHxBAh0ueIoQywZu1ftYFUF6hQRjcOwi cvlTj9zMAIMC3T0oUMvhuarxFO4kYJ1USy8jwJvDot5kNhlgU/PJKoCGVsLufiBSMpmb/Q9o+Mq TPlO2KM09ibYnrdOIsNXHI/SEyq5m5Q+aXIb6ozKORGFJOoudsOTn9rONPcWCtyR9riE6t/pJe6 116RBmPx77t5FUHruAzwN3wlw/YK6nT2FWkOu4tJ9Cilkoe/wUKTEPN2w66TekWOMyw7ZncK08p DxyqKon1EVz6U2K2wf2ogiYZi9WikButCuF5FtWkqQ== X-Google-Smtp-Source: AGHT+IG6jlQ44pwh9wX1WCDRI6TvuxV3hUxEozeeET2dKmcHLpN+5Bivs6u3n/jRgCZSuvYV8jlCbA== X-Received: by 2002:a17:902:f642:b0:224:26fd:82e5 with SMTP id d9443c01a7336-22c359a248emr91338345ad.48.1744892692486; Thu, 17 Apr 2025 05:24:52 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:24:51 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 06/13] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Date: Thu, 17 Apr 2025 14:19:53 +0200 Message-ID: <20250417122337.547969-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable schedule_on_each_cpu() was used without any good reason while documented as very slow. This call was in the boot path, so better use on_each_cpu() for scalar misaligned checking. Vector misaligned check still needs to use schedule_on_each_cpu() since it requires irqs to be enabled but that's less of a problem since this code is ran in a kthread. Add a comment to explicit that. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 058a69c30181..fbac0cf1fd30 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -610,6 +610,10 @@ bool __init check_vector_unaligned_access_emulated_all= _cpus(void) { int cpu; =20 + /* + * While being documented as very slow, schedule_on_each_cpu() is used si= nce + * kernel_vector_begin() expects irqs to be enabled or it will panic() + */ schedule_on_each_cpu(check_vector_unaligned_access_emulated); =20 for_each_online_cpu(cpu) @@ -630,7 +634,7 @@ bool __init check_vector_unaligned_access_emulated_all_= cpus(void) =20 static bool unaligned_ctl __read_mostly; =20 -static void check_unaligned_access_emulated(struct work_struct *work __alw= ays_unused) +static void check_unaligned_access_emulated(void *arg __always_unused) { int cpu =3D smp_processor_id(); long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); @@ -671,7 +675,7 @@ bool __init check_unaligned_access_emulated_all_cpus(vo= id) * accesses emulated since tasks requesting such control can run on any * CPU. */ - schedule_on_each_cpu(check_unaligned_access_emulated); + on_each_cpu(check_unaligned_access_emulated, NULL, 1); =20 for_each_online_cpu(cpu) if (per_cpu(misaligned_access_speed, cpu) --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4D3323ED5B for ; Thu, 17 Apr 2025 12:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892703; cv=none; b=Gt30j55YkKHh0yFzGX/JHOBsVWREwRcq3S6V7REVDFAcp5rKMxjfvkVUaV5wBebjkKCnpEg1rn076IuOsZwFnJT0iyNVk2bodkKVGEhoccBVeupPfPRBX6riL2tlZp4m4fc0C0ZUxzM3gtseOwTIy1hDq3ut4DLwJFSoXNhWMvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892703; c=relaxed/simple; bh=L0SOEIAv8LuDbsk5R4W2vKNdRPBPIuIziKfqu3ZTv/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ExSY8kfAo0aoE5pvrNLQQtSooS+gFiOpqfG0akb4g/1VPtQmzq1bbYR3EDUnj4gNJcR4OR1+skSkdu8h0EqHpqbc2MJ0/vrajBGpUzVFVjp+Em7fONlzg5PU60KCc6Bj2YJ1p2El6prJ3n2owRlXt9aH0Q6+o3wbPly499BQPNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ibjRwoLy; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ibjRwoLy" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2241053582dso9949875ad.1 for ; Thu, 17 Apr 2025 05:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892701; x=1745497501; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nIScjDpjhLjkf06YMmBlHqg/pe/+cSuNoY3aF822M2E=; b=ibjRwoLyq3klgkP2O4tGwsQNbHrlVJMDwyj0gVRcROYqWJbK8lJpg3JzpmE8b5fDPu xm5xqp7mP3DliefOJeGF7mykkyO8wFmH5a1GFi3IAu8QbBc8Elx4p85UeGgP2qtsk4Fr 2cUOYOT7GBRbCJpLi+8Kel+Suo00Px9IfgFdbEBZq+0wlopQSY+KDHvcOkcvbCSsgNCT aaiapzTVUlDifizVC/BR97d+1UbnB5hgwdn6ug4H0y57KRldePSocZNPEEbgvqHfjAqR cAmGUIt08bs5abfwcQJJSI4gaEth6LMF8oTx2EC+eHXSRgCixztSfXkQEEWdocDbMypb pVyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892701; x=1745497501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nIScjDpjhLjkf06YMmBlHqg/pe/+cSuNoY3aF822M2E=; b=ZeSi9WXR3k2E4pb3ohp/Ciq5rFsGHID9a7I/6CIG5M/hH2dr+DokJkvLef3T7eF30O 1oxFoMCp9zRuf2xtvbGEl94XJmJCnKYj/yBNutxa40dTT1mm2u6LgaLbvEWqrHB4gaP7 STkQJdIRpQQlMCFZv+5ewlDTPvUAUqi0RqSPJjxoraguBLKW0BDdQg5pTyd3pzucCj40 HX1deeKpLsakbCbM3FAjqnlKsCQIGX9Kt7Cc1OLhaurdrrywMFJlcu/GBtStWIsM/kXV 8eThPheJmH1Vc6FoBr3deHXTfyw/M5GI5EKuLjwGkxFyjr6221ZvE8nV+h4WKWRLq7Sl ZacA== X-Forwarded-Encrypted: i=1; AJvYcCXzVf+4H1TWcv5Hp4MiB0Z0cM683MjrxiTKfyTVsfb9fOX0hPBsN+npSgfX+4dDyX9M0bNzD6+eSNm31WE=@vger.kernel.org X-Gm-Message-State: AOJu0YyiL6M8rFVLQnIdtFvvyoGlTUEqD4QEobRdgaKSrkw4h0UGdBs4 5JAVVnFALjvLa3iXsXuCuBacbMWn4f6/1fgA1+AUUr6BKNyIfjBwKcTtZoZrSjY= X-Gm-Gg: ASbGncvKtEYUqgPCowFdN01Tbu48boqeYwKxmjKpKotU3INBATueeFVvI234iWZ1bed YCkl0+99REK5d+vWnzsA/gaHwptXJtB5tB3w+VLiAOwgebJR5xBi3zYfaG99sjV2h5z4pnDs1a8 d8E4/WOiYur9o/jQM0INYhV+hE6Ji/G0qt06oIITjgVC3BncCHOG4Peb073hsyRL1HYaEPhJUOy /vikCu3sYS/loWQvge6c915l8l1Tt9+cFQy0hRZF59fszsJpO5DTj4p9tMZ+RCez5JAGuQmlVkN SqFjDOH6mx0fr8xQxJsqc/HeslOMH2dHPi+CFMPV3w== X-Google-Smtp-Source: AGHT+IF+QdSHgucK282rG6JIZxJMqqmRWlCOO1zcFo/iz9JeHV9jdYKxWAUM/FMJsou8iVRkgl5odw== X-Received: by 2002:a17:902:d48b:b0:22c:36d1:7a49 with SMTP id d9443c01a7336-22c36d17c11mr92045175ad.53.1744892701180; Thu, 17 Apr 2025 05:25:01 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:00 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 07/13] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Date: Thu, 17 Apr 2025 14:19:54 +0200 Message-ID: <20250417122337.547969-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable misaligned_access_speed is defined under CONFIG_RISCV_SCALAR_MISALIGNED but was used under CONFIG_RISCV_PROBE_UNALIGNED_ACCESS. Fix that by using the correct config option. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index fbac0cf1fd30..c99d3c05f356 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -362,7 +362,7 @@ static int handle_scalar_misaligned_load(struct pt_regs= *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_SCAL= AR_EMULATED; #endif =20 --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4F9D2459CC for ; Thu, 17 Apr 2025 12:25:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892713; cv=none; b=WpByuU0E3kImxp0ac81KgVX+s2V37YrCJufvGMs9ojjp5iZqeblY1nLiuhWc791Avj75VC6siMyBi4GHrsWVEi4IjCHfpkqAQuQlRDSdxXEmJBRFo1kp0CRHCEtS3FiLB6N1xujogi//r39STcZbAfmKCYpylCD/Epx8kBiCt8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892713; c=relaxed/simple; bh=Y2lqZNq6iLqWqOnSydPOH5JyZ2wkgBYP5IWsduUOFdg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AsxUL1OJhpY1kEMPwQup3y0oR8ZxDVWnGsRVzHlLOpGZgtM9B0fcO39Seck+j/cuCeQ+ljGL9kKvX9Ag0iVmzu84RxoPPrHcgKyMgQ6eqe1Dk4gruJ9K5s31wS4xHZx9u1H0v6xlMPSBFiSq3m050XIoKpmPEl7mri5oROjJc9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ki1fBIHL; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ki1fBIHL" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2295d78b45cso10722215ad.0 for ; Thu, 17 Apr 2025 05:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892710; x=1745497510; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QPTklWUDdxW6D5Ost9jmiUOVbTQmyFTBQdSARUhAxLU=; b=ki1fBIHL49ytpWv4z9SYrRoy95lBCJ0DSli9Jrt4gG3l5hVK5uTiAkQFL4ZG48ByAp 9+zreDoPqeBo2LtHMz/gYzfcOMDcyDiSoXoq0NjM1acWkLmAhz2t604Xv3t1ru8wLpy0 /2WTeZlYL+j/ZHKVu7iri2IDJOBRrs0e9opbK5XTkOO1kKnGKWn4XS0YixGIT5fawPMp fNRkn18JJ4UffAdcyFZEKFCATVNVbdXlV8Cp4Behmx7Yb/G4dJ5GJFHzCWS6XZffUgl6 7dQaGXcUsfgG2+sC0iTNazdcTnYU4lIaXuQ9ufuOSll/1mWEF8LIWdG/zVekZxubpNYE 5iqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892710; x=1745497510; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QPTklWUDdxW6D5Ost9jmiUOVbTQmyFTBQdSARUhAxLU=; b=NLDg1JJG6EFLfYL95RmaywADMKS5l2YUfajdgpQtjaPgSlHg/f+6lbQxuIp3pKm92w rkCIXf5RpyH+IJRGpQQD0QclI12Op7jBygXxA+sMdniKrdutbc/pixmrfOviDPmZ+tb5 OIIcSGu7IEfsRIUy7zKANv+lrVUdW5IIg16jEDk+ppad3gEOTIVuOLpoMrQvRyE5Nha9 PECVAVK6GEgr2CQo6do4VNCH3IiUOjvAIALORaIms76jeMmWGYdZJeYh841h+e+Ta+Jg p8imwNviuM6uECbXt73YQGVK0nuMxQpHzk3q1vZ/L6XjRAMSnN58KV5CFeWwJKygqu7V Ok9g== X-Forwarded-Encrypted: i=1; AJvYcCWS7l5KQSoWl8E0fy2BKyybTZiGehwEq3mTTtXsgeY+KJHei6zF9R6FUCgNWRIfP7fB+g+vtFaFyIJJsMI=@vger.kernel.org X-Gm-Message-State: AOJu0Yy5On+QewkS3CbVj6l/PosgmSsyrEy8wbqGjGLJ+uHGwbi3BKby yNqjYQTXrq3Nizisn2L4ibzpavQAke7457uy+Akqf46rY2b26X4oTJIBsBBrQDY= X-Gm-Gg: ASbGncumlyNKXFC3g0miOamosEt7Jc8ziyjFX7j4xS7KbttB7YqesVu8IYiRpMsPZ5s jBlr3RuwPjeKuuU97tZZtQ1lKhGBhcxP8UmmOu/gSdITjB6v1bharZw8p8hPyxxJJdOYwcScjEj ++DOET0CIs1IqAcEhMCMzZ8gQuuec5gRbfRa6irmalctLLtFFLSGzfBJTLBfc47NwiMlkOhswpw C674BmjXmYuGLG13q9cQ5gE7Vvhs2OWJkV3ftiRiSg/C2g2lKYipAT0iHAc4sadTQw8+5bMtqa9 Mp9AQUnZpB+5+H7QmtopZhNDouQvvTsIgJ3CAXXUBQ== X-Google-Smtp-Source: AGHT+IFHVZ6ZCfLmCo/4Wa4FBs9EaC8NbnVck/zV+hCmYDXn9aie+ex4Lrhj5kJpm3i3DZVuvfUSqQ== X-Received: by 2002:a17:903:2a85:b0:229:1717:8812 with SMTP id d9443c01a7336-22c357b1125mr88299155ad.0.1744892709956; Thu, 17 Apr 2025 05:25:09 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:09 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 08/13] riscv: misaligned: move emulated access uniformity check in a function Date: Thu, 17 Apr 2025 14:19:55 +0200 Message-ID: <20250417122337.547969-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Split the code that check for the uniformity of misaligned accesses performance on all cpus from check_unaligned_access_emulated_all_cpus() to its own function which will be used for delegation check. No functional changes intended. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index c99d3c05f356..a0007552e7a5 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -666,10 +666,20 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) return 0; } =20 -bool __init check_unaligned_access_emulated_all_cpus(void) +static bool all_cpus_unaligned_scalar_access_emulated(void) { int cpu; =20 + for_each_online_cpu(cpu) + if (per_cpu(misaligned_access_speed, cpu) !=3D + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) + return false; + + return true; +} + +bool __init check_unaligned_access_emulated_all_cpus(void) +{ /* * We can only support PR_UNALIGN controls if all CPUs have misaligned * accesses emulated since tasks requesting such control can run on any @@ -677,10 +687,8 @@ bool __init check_unaligned_access_emulated_all_cpus(v= oid) */ on_each_cpu(check_unaligned_access_emulated, NULL, 1); =20 - for_each_online_cpu(cpu) - if (per_cpu(misaligned_access_speed, cpu) - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) - return false; + if (!all_cpus_unaligned_scalar_access_emulated()) + return false; =20 unaligned_ctl =3D true; return true; --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4445024CEE5 for ; Thu, 17 Apr 2025 12:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892722; cv=none; b=tID9qBw3skXA9DC8FQKXoLY5sUc4fmQs9ksU0xOOyD4tBbrR8wq6gL6cLmE5C4EiMyRlq6MqW+hiUpfaWugPLvOmKyl+ZVb39lF8A9cLM8F8ZI5UynME+Rle8v40RTEq0Z97sf3wMUH1ahlepvewILqfdM1mkjQwq2slwyKS+GU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892722; c=relaxed/simple; bh=EovtyHw9idZFNwtsYlCnzb9BpVvdfog+V7fNy74G0ek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MBBYXpb2DUP0EY3eZGXGfDgtUEIRcFnYXlG5YSq+17jBoN326hsX2e9O5nMOPRY23tsh+8N7zrkOosdbfcN5raRu1vXjr2DiIlK+HolN3AGNthn7see0A4Dx4syzYJ7mGkcznY2DIy7tC3SfL+X+paFKpOEAZR0vK6HyNH4z/Jc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=YxAnZnFd; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="YxAnZnFd" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-22c33e4fdb8so7216745ad.2 for ; Thu, 17 Apr 2025 05:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892718; x=1745497518; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QZnuSlMP6ZuwANzL9lETdaARYZp01YtNV9fLw8GSKUw=; b=YxAnZnFdjVu5gHkkao1RamPbDun2+eJGZ96H+jcRzfY99EYkmBRdovrb/zuWmBuLGF /vm3UtI+rDHCd6jVWTThMHRmppDhiG2Uw73HbKc3uJnD0OEN7mJ/hfboLSwuBj/M1nvi 0VTcokaXVSoRcweOfmOhXdyS01tRWi+PHt8I1h6eJPLOajaTV/egiXaZzEOSzPmapj25 kg6yWyU27GGfh36Vl7z+YR3rMvYb+zbF/f/UJcEuRvXuhrZdRDN99ti7EAliF2m6egh6 48BhqxVEQEupVYxsHAaMU/x+xGxMG1uGpQilEj72yYRLMQJz3POhj+LljvNa3NnJoMTw SHCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892718; x=1745497518; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QZnuSlMP6ZuwANzL9lETdaARYZp01YtNV9fLw8GSKUw=; b=U2o4CNdmO4HvNrNJQTxxyUZqEmDTGscH37y18wuIPr2jeZaocDdyyhN38FAwHbgSqA fcp7utDyBgTU8uXkQysddLpPrET+nPqt2wk+sXMgJWADO62cWrsXzXOZx8Vcar9aiIla h7+kzO5sioZMVo/kDGmxJnYRvUM2nfF1mP/Bqev4dxfOUFSQYbi5mMW664PVXE42qgLn LMDDwHZOAhFmZbNxBoOiyFwkFd8vTmbmQ5Y1f0OXiG7UGIjFt+dBlM9KpI+yNgYQvfYe 0iFjbwo+YG4c4UUwuxjcKEAIRNmtY4wXyxlfGJGFE51dg1qsTEW/zKpTcaaxnXaXO2iJ xXYw== X-Forwarded-Encrypted: i=1; AJvYcCXYTvFqfPuPfN+jsPPd0M1dUu2G0W4MvWHnZ2VEud0jNz+CF0BwIqB1tnixam+5cXDcl2Qt6mdWsA6w80E=@vger.kernel.org X-Gm-Message-State: AOJu0YzaE/bc11FFaAHqn0VCEOyTJ4l0K9f0uTelqzVOTwfKiTCKgHiJ Xu47swCqCe0Xzf08zuD6DIcNzil02uwojYJbspLs6xZicjsAzjXoTg/LsxCX7UM= X-Gm-Gg: ASbGncutSDZoYH0ot3yJI4Rft6GvFqlDB6v1OQhpv7jXufsyzxIQOYyXWYrJ6OybJi9 Viw9a4vLy0YVvxvq/QGxLdvto9++Ke8pNxUMIrEB6CLhnUVQhO4fxqJZelgTWL5Q+m1JJWnE+gr BB9RveG22PV5R6TGG02BWt0ZAKqeUTp6lvhxC6wLSUXfRjK1yF6jWqt+RnOciOI8z2TbpnBsjup ++irE9yN3Ggqr9DrE/RLF5ep/JVNf7USfX/GC/p/vlGKOYroycuS2fZGkwohSAAif3Ogwg2S8BX OwjSitPFcIKBuff+cu26tciZgo3EG86wOu00nECYymWQBjpyZJNy X-Google-Smtp-Source: AGHT+IFn+UkDwIOY/e3sKBsC4N9k8AEuCmWtLw7UPdTMPKcDNDFZ5/adGOe7oxZT/yFghuiQ5DQrlA== X-Received: by 2002:a17:902:e808:b0:216:2bd7:1c2f with SMTP id d9443c01a7336-22c358db9abmr72649025ad.18.1744892718633; Thu, 17 Apr 2025 05:25:18 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:18 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 09/13] riscv: misaligned: add a function to check misalign trap delegability Date: Thu, 17 Apr 2025 14:19:56 +0200 Message-ID: <20250417122337.547969-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Checking for the delegability of the misaligned access trap is needed for the KVM FWFT extension implementation. Add a function to get the delegability of the misaligned trap exception. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 5 +++++ arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index dbe5970d4fe6..3a87f612035c 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -72,12 +72,17 @@ int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); +bool misaligned_traps_can_delegate(void); DECLARE_PER_CPU(long, misaligned_access_speed); #else static inline bool unaligned_ctl_available(void) { return false; } +static inline bool misaligned_traps_can_delegate(void) +{ + return false; +} #endif =20 bool __init check_vector_unaligned_access_emulated_all_cpus(void); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index a0007552e7a5..7ff1e21f619e 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -709,10 +709,10 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) } #endif =20 -#ifdef CONFIG_RISCV_SBI - static bool misaligned_traps_delegated; =20 +#ifdef CONFIG_RISCV_SBI + static int cpu_online_sbi_unaligned_setup(unsigned int cpu) { if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && @@ -748,6 +748,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned int = cpu __always_unused) { return 0; } + #endif =20 int cpu_online_unaligned_access_init(unsigned int cpu) @@ -760,3 +761,15 @@ int cpu_online_unaligned_access_init(unsigned int cpu) =20 return cpu_online_check_unaligned_access_emulated(cpu); } + +bool misaligned_traps_can_delegate(void) +{ + /* + * Either we successfully requested misaligned traps delegation for all + * CPUS or the SBI does not implemented FWFT extension but delegated the + * exception by default. + */ + return misaligned_traps_delegated || + all_cpus_unaligned_scalar_access_emulated(); +} +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 031AF247DF0 for ; Thu, 17 Apr 2025 12:25:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892730; cv=none; b=Hn60saLAIXzhm/AJ4me1cof/yRJdAMbcmYWA23br91aMSQ/68bnCUzoR7su7hzba63qkRhItchjuomROGn+CkX1gjOWiMfuFOXYlymCC/RjKuuBLx5mHUFd4/Si4K/XjEtznhIPjl0ASykOs4fwbpYGocInH5vAkCj2qp/nA0Bg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892730; c=relaxed/simple; bh=NXa9HEO5RKY1D2k9IbxsxMtK9lSmU2PJg0VdH4XU874=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g+r2OvUr3s7JFj/FjFytBW8PjLP9PNkQtDhGKgGQMecxC5E7d5lVzjEkAJePQ/3YasURzT3dGYPPfNgeRIrm090UwgF7ZZ5gTW1ngWomxlwmXU/donaLv1PclPvZGgwLIwqc5qggLIZ0pqV0JHLmIPUcp9c86GmFvL0fDtqxxp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ebL7KfEo; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ebL7KfEo" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-227d6b530d8so7156325ad.3 for ; Thu, 17 Apr 2025 05:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892727; x=1745497527; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/KHThPTp9HBECdAqxs4JY6wN99GqOifsmOPr7rqjaok=; b=ebL7KfEoLNqPqmyiWZAsOd3YNnrAxLi5iPwk0vZzO1HAU3PqZEJryOBOFQUSEVCx5D 6KkPS6/omiyR0cw0DrR0w6vrXo0ovV9xKUmPfHP5vjiMavkamcppOyMq7bswF6h8VZtg pxV/CglZ5tAXiNA16etMPHVOp4m3cL2smOraRDIxnAhAKz1ynOIm3uQ6RgE/FFFMxMIV zob7P1LzvABzUMIukDwahFh5UbXLPsZDjV9jmuE4UB6A3438EiK8S3aTsYIT+9tapbf+ 6gyLejP7c5HNtVFUvD+uBUmKS8FpY3//gbPpgZ2JOVDg8f/zsC1MkvFmxoz4vqjny5sn gR1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892727; x=1745497527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/KHThPTp9HBECdAqxs4JY6wN99GqOifsmOPr7rqjaok=; b=JXzsyTP04ZkNnjVgpocgO2AFVaCxUCrzD5MxgP4uqFbM7YE/AUQZIaHxn8eHe16wiB V9uehsqeOzp4rDoIY9+RMb5WDOluv9DF/v5oB921vGwSHUZS+CDfn5+AQLMnWASSKqk2 C8IrJHpXx7DHWZ2v8+3qO02EA621VmYnAj065bZgujy8TWtLFA2i8q1DDVgsBH/+ieGj IXCOe8kqPWUYkk/DSFMZX4DlQR6vxFKwSxl/fyEgGofvb/313NxxOakPaYn7qdjhEFzB cSBu0MXYg1sn8/w8sYJJEado1yXd1xrE/X7ZrOUJygLCUA7ZUOMRfMcFuEujZgD8yBzO bsFw== X-Forwarded-Encrypted: i=1; AJvYcCWu6WNN4zQ5oJdBwrte35DSBCPOWa9K9InGOl8rljNLNA+Vy8j6mba0fpWylGDTU+3WMC9yovmqTL5MN8I=@vger.kernel.org X-Gm-Message-State: AOJu0Yz96WRR2Gsd/HdxTuGDn994tTTwEcCM8mGruL2TqXPgfGjDQ67F XL/qmVwU2zFsYhDjxQRtN3FXqTtydfVImJo0HWtNKEw2GvQJ+4YcpLqymEjSBvk= X-Gm-Gg: ASbGncsPbrwxuc6LAGUp9U0rEkzuzQ3+iZWwI3T+jMjp4A9tVSOnSzatCYvXM7fHTlQ OModRSFdpDyZTsMZdASJWoB9dYumr/KdECHuk/S6kCS8joMcGuGlAk+3DsmO3CSwFenp8eQzoT2 AKcIQ/Dw72MnuQCtIY7HZlLyfs/NY48RZWMZAtM7juszqhy2sjRN3wVfAPNhtkGNTskRVjwa5Gq lDTb7TTBN5qXwOT4dQ/z6FzRB/j4K0xJeC9mKOB1hofwVz5BLRW0POK7pPoMiftCIMdNvmW1GuC TMLCYcxFytDm8Vl87sUB7/OX9N9412pY7bBCBG2jBQ== X-Google-Smtp-Source: AGHT+IEoqy/kqoORsS0UV+1ioB/JireEK12cMki3F6JIxzmrV6R0qu0Yn7V200b2nJAkaxmJUugsbg== X-Received: by 2002:a17:903:1b26:b0:224:13a4:d62e with SMTP id d9443c01a7336-22c3597ec4bmr109539965ad.35.1744892727277; Thu, 17 Apr 2025 05:25:27 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:26 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 10/13] RISC-V: KVM: add SBI extension init()/deinit() functions Date: Thu, 17 Apr 2025 14:19:57 +0200 Message-ID: <20250417122337.547969-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The FWFT SBI extension will need to dynamically allocate memory and do init time specific initialization. Add an init/deinit callbacks that allows to do so. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 9 +++++++++ arch/riscv/kvm/vcpu.c | 2 ++ arch/riscv/kvm/vcpu_sbi.c | 26 ++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 4ed6203cdd30..bcb90757b149 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -49,6 +49,14 @@ struct kvm_vcpu_sbi_extension { =20 /* Extension specific probe function */ unsigned long (*probe)(struct kvm_vcpu *vcpu); + + /* + * Init/deinit function called once during VCPU init/destroy. These + * might be use if the SBI extensions need to allocate or do specific + * init time only configuration. + */ + int (*init)(struct kvm_vcpu *vcpu); + void (*deinit)(struct kvm_vcpu *vcpu); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -69,6 +77,7 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ex= t( bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, unsigned long *reg_val); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 60d684c76c58..877bcc85c067 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -185,6 +185,8 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) =20 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_sbi_deinit(vcpu); + /* Cleanup VCPU AIA context */ kvm_riscv_vcpu_aia_deinit(vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index d1c83a77735e..3139f171c20f 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -508,5 +508,31 @@ void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu) scontext->ext_status[idx] =3D ext->default_disabled ? KVM_RISCV_SBI_EXT_STATUS_DISABLED : KVM_RISCV_SBI_EXT_STATUS_ENABLED; + + if (ext->init && ext->init(vcpu) !=3D 0) + scontext->ext_status[idx] =3D KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE; + } +} + +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int idx, i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + idx =3D entry->ext_idx; + + if (idx < 0 || idx >=3D ARRAY_SIZE(scontext->ext_status)) + continue; + + if (scontext->ext_status[idx] =3D=3D KVM_RISCV_SBI_EXT_STATUS_UNAVAILABL= E || + !ext->deinit) + continue; + + ext->deinit(vcpu); } } --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B198C248876 for ; Thu, 17 Apr 2025 12:25:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892738; cv=none; b=NM5/iuKIM748YZRjk08RXETfJX3zKhKuprn2rFNxt7h6loL8P3mPnh8PkVURt7k/5fLp5k/30t6WLMK0IgKKKaVU0aCJRMUjuudF9a5qcP0Bb8wHzfzKSRy9ML0c3Z2tiwACjUWg3OrReUku5aBAPH8xJXeLA1czvouDM2CYD5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892738; c=relaxed/simple; bh=H5I3SSDmXjwRUib3TL18xTg/rVQsrKqfiODBF/E5v6c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=G6oR3zGv5v7RaofrR1HDY4GYp1P3ghUosIxtvEARLOW/7scX57qvgHkY7N0gRBOm0sHDrIjYMum4nqEFZeWuZwVW9P+pNHU6BJf72gSTwKDVW11fB/lysS4n7HQR0cBe1zsbTqx8Oe+0E5ux++KS9s1116p1fHGLlyMubV9YAA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=XpBQMCuX; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="XpBQMCuX" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2295d78b433so7463325ad.2 for ; Thu, 17 Apr 2025 05:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892736; x=1745497536; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RIWI5J13lSlmUc75M0Yyv1OmkFoJoZE6o7hXZ4HO9lg=; b=XpBQMCuXAyDB11UWoArkfLcN7EhswpqfbfknbC1ohQpeyaijdj8NnI7eNKYdG9SdJ9 L5ieRIgVw3cebhF07DqstpRT60jXzn/bstssdCO5AwAI548ClCWIapyPKjIDNtn6424E jhByHaFEWxUltJn/l8wiawskYcErI32YJgpXwGwu/RC5a0qiWRHMrZ6hblXHkQHSxipe 2g1XpCBRtGxG0U6q8xeou9KN5H2OhqyNt8mXzn/qvQyqrhYkZei5yR+vJeQQXucf2ghL RaM2O2D7rVqCB3I7kXt3OBeZviQVJS//NPTdcvv0ipFcdrDHHYY1iwtG83FS0F4OixOL c7ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892736; x=1745497536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RIWI5J13lSlmUc75M0Yyv1OmkFoJoZE6o7hXZ4HO9lg=; b=i6JLCY2xFYg6FOVDPerwk5fEdRiGnlrIGLqGx0wAbflC83AeOAW568lGU4Ju2mAAJ+ xq5yJXP3pt101Mr4DRYligvQZt/G1hD7Bz8HOt0NuR1Cr6bCC1Fcga6gdGKX09suQ+Iw 3vFPbr6/kuol2N524Jg/d2kYFF7UF+UtlNoYZEgMBRPcF6ZaSJUYjm3U5LuYEaQnYkam iG1PmI+mVqxL8rSDL1+rsO9uNG0hG7118+w4GP3RLljUF9/Naaeu0ZJZ6S//8qj9zAQ9 uU6rQZCnN/WsEY2B9VN9F5yX8j02+f9oRkE5iwQhmlse44t/jQDqjK+ZiJvLzGSwZk2s j3uQ== X-Forwarded-Encrypted: i=1; AJvYcCVHsEsDVXH9Fp26Dgqkx8kqAuc7vOEX5AdOK69As4qFLHZqdO4lM3M+7CTMk6ZMRw6GZIU2baMFAs2udbk=@vger.kernel.org X-Gm-Message-State: AOJu0Yw7tnkD1cCvw5b2YKap4/I0EIZi05vRAIsLPNzNprJbVC9IlEbE M02R2kJWlwGfEbcxRsFlTlnCgEyw2Go85pPiO53tDFZ1xkG5bmb075zDBOKu6t4x4PVSb5fpRZV c X-Gm-Gg: ASbGncup4zhmIquzdha+zVinZLJUHTl3Zp7kjML4F9dbxiqvYUwB12TkOMfEm8QmWQx pXLu3COM5lMsZYCzHAYd4xUmq+9CjdhdI5CACNJCeayLmyaruq6/bWdMhNrMrqdyQiu9Y+zAPW9 VHXvXstuipd9xZXefKI4C97HmIbtQ3Bw7bDGtGa22yU/eHXJnWTvPJIhsZQ/fMsslc/+q190cVt rEXoiVZX8vDLtLf1hwKlHt55e8obsA8OglLi9R3W1hRQh0o2Bta/tHAo1VUY/NduCCkRUpQ7QHV /qDDhvJotsFEQ8LLDidwQ+vvarHzqTL0JGXM9AQl5Q== X-Google-Smtp-Source: AGHT+IH/XOfIZJN1QIMfxSpPHyEBOL2TQ9imzdZAMvoYmfc/2OhjJtEou81N2JqUbXrpk40zrfv2Kw== X-Received: by 2002:a17:903:1905:b0:224:10b9:357a with SMTP id d9443c01a7336-22c359743ffmr95085905ad.32.1744892735913; Thu, 17 Apr 2025 05:25:35 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:35 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 11/13] RISC-V: KVM: add SBI extension reset callback Date: Thu, 17 Apr 2025 14:19:58 +0200 Message-ID: <20250417122337.547969-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Currently, only the STA extension needed a reset function but that's going to be the case for FWFT as well. Add a reset callback that can be implemented by SBI extensions. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 1 - arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 ++ arch/riscv/kvm/vcpu.c | 2 +- arch/riscv/kvm/vcpu_sbi.c | 24 ++++++++++++++++++++++++ arch/riscv/kvm/vcpu_sbi_sta.c | 3 ++- 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 0e9c2fab6378..4fa02e082142 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -407,7 +407,6 @@ void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu); =20 -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu); =20 #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index bcb90757b149..cb68b3a57c8f 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -57,6 +57,7 @@ struct kvm_vcpu_sbi_extension { */ int (*init)(struct kvm_vcpu *vcpu); void (*deinit)(struct kvm_vcpu *vcpu); + void (*reset)(struct kvm_vcpu *vcpu); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -78,6 +79,7 @@ bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, i= nt idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu); =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, unsigned long *reg_val); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 877bcc85c067..542747e2c7f5 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -94,7 +94,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) vcpu->arch.hfence_tail =3D 0; memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); =20 - kvm_riscv_vcpu_sbi_sta_reset(vcpu); + kvm_riscv_vcpu_sbi_reset(vcpu); =20 /* Reset the guest CSRs for hotplug usecase */ if (loaded) diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 3139f171c20f..50be079b5528 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -536,3 +536,27 @@ void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu) ext->deinit(vcpu); } } + +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int idx, i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + idx =3D entry->ext_idx; + + if (idx < 0 || idx >=3D ARRAY_SIZE(scontext->ext_status)) + continue; + + if (scontext->ext_status[idx] !=3D KVM_RISCV_SBI_EXT_STATUS_ENABLED || + !ext->reset) + continue; + + ext->reset(vcpu); + } +} + diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index 5f35427114c1..cc6cb7c8f0e4 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -16,7 +16,7 @@ #include #include =20 -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) { vcpu->arch.sta.shmem =3D INVALID_GPA; vcpu->arch.sta.last_steal =3D 0; @@ -156,6 +156,7 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta = =3D { .extid_end =3D SBI_EXT_STA, .handler =3D kvm_sbi_ext_sta_handler, .probe =3D kvm_sbi_ext_sta_probe, + .reset =3D kvm_riscv_vcpu_sbi_sta_reset, }; =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72DD248885 for ; Thu, 17 Apr 2025 12:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892747; cv=none; b=hc4D8KgHaogdo+6qx4GQhpI4uAFXOcJCG+CVfzeg5iQjm0KVlkC6mBfUM9fsuCmcOLQsAEmUZ9OmOFZyCkg4R7Y6eEN35swdY4t1cKmDpXlf8QFmlz90WgDY8dPRqFC0TOhPliFlFFwnIfevnnq0ygFUvouDSdPvP/L8IEB2QaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892747; c=relaxed/simple; bh=1C7Djni+0IZk+aDQP5LiExVKCiwH2agzUNaeaAf13I4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=amU+p76szPeeUohzXvEkc+Jnm2dvOYW/ljNns/eGKsPFBAZ2jOzNxPXaCn84O2R/XUjF2zO7fX34nLCmlUCwWZ4dB6XsQTNjQVaTYtwr4nS5Ey0pAhXnUkRvyYVniRQ1eYCqxNYb9qCHTv+MJ8+Y/zEbYNEjDBxBm939KYOeM7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Psm7ABi9; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Psm7ABi9" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-224341bbc1dso6880025ad.3 for ; Thu, 17 Apr 2025 05:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892745; x=1745497545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pIsv+titG4x0ovEMDknM6ko4IiiOufEK1Ymj080VPx4=; b=Psm7ABi9Nc1PQUKo2YxC7/J+e/teQjKs6jeERPPuo5wMhrk0iCJgFLF2ER4j7S3e7C RWH+jyD8syaVXL/jUIXRZg3VN4DV4zYm2s4xsNM/xNlJUhzsK4vfnblTwE6we/wa6kVn ACAV0yu3bLN3myX1zjQgFKRPwIL1HCMOm+Qd53iMSvR/bBgGHTgp6wMKDNEbuUahiJcN skTcm4P3qZmEt8CnC4RpgQP2z7DFH0qWjiWGPC8aRI/NNUIO+ka26jCTM3BLRN4QOuuL MhtFjzzz0mv+RcRoCrw7XFWpcUWQXMD6S1jmmmrULHgM7hXc4crXy3+mLujMTEfywXP8 D9sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892745; x=1745497545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pIsv+titG4x0ovEMDknM6ko4IiiOufEK1Ymj080VPx4=; b=E4r5R8CPhaEOGPku4dLJSgFHJoeMux9G4V9hztEgv7PuEHDYq5O8xDZO67GBHBmEne xZNr/LEEcSgwVvmLNbNWUNoFpHKCd7Hrf0EA+PnGcIKqP4gfNiZq+jqr1nscP/HvX2DI TYx24ohJzYzX3Fqg5ICp3EHapC+6d3INA4CQAFJ+mPUPkA+xJbns1v5GhxqBJRqj/2+y FI2yIRsFQyXxxbtJHM9gFBuUp7yGz6xokVpqjL2xAuyJCmEL91N6kfxD1HgYvMnewHq3 aF4+snzxN81pnAD3rzM4O2rAFRt5qgUSa5UCkX63NoKpZQhsU1X0NNMb/45uv0R+jYTY S97g== X-Forwarded-Encrypted: i=1; AJvYcCWtdOguaLm7iOvOjZv06up2L0mHzOWuI/+8ns46c5H2nxnLZu+mFyUOEMOxHJlXeAco7A3AgdUMtUX41Z8=@vger.kernel.org X-Gm-Message-State: AOJu0YyNDVFMA7+tnykScysno2dJr0LYk5b2OoQOO+1kYj0bvOvFZkgA pIXli4JjYCz/jTwA9r55zsDyW7cM1zX2CFBPzI+DjUJ0TpCU0987uOVe8TsZdl8= X-Gm-Gg: ASbGncv5KyT0gasuYKkHiRKkz/TcbuDMFy3xospXE/DcK+drPI8eNJum1MYIKP+EMpB XAajA0gjg2WBOHKkdC85WpsiOXJoBiBiGAKthLu2Vtzl0dxBOdc4DdbON26PUoP/bDi8f/9zM0X K1nKW0CYbLfN6kqFrLJWdfqY2XSMSE2274gQdqg2SPN8kVm4tNitCbV2QrYuc5e7YFKvIyxqoDX y6wYiVthu5bu5SKnX6Sfj7oBKbfvxaqga28siXSeCfDmsQ1xmQTTVi75yV76EhTWHSVjAJCfNhR ANlDopefKgCAyv0159qITfRMkBgFmZJiiKzdND4IVg== X-Google-Smtp-Source: AGHT+IGDDihX5lWdOzC9ncwrK/tngZ3TXIjrRmj2gDvm4uw4i9VhaLXbViaOi5GeDmwgRF2C0Uq8jg== X-Received: by 2002:a17:902:dac2:b0:21f:4c8b:c4de with SMTP id d9443c01a7336-22c3596dbe6mr73195675ad.42.1744892744869; Thu, 17 Apr 2025 05:25:44 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:44 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v5 12/13] RISC-V: KVM: add support for FWFT SBI extension Date: Thu, 17 Apr 2025 14:19:59 +0200 Message-ID: <20250417122337.547969-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add basic infrastructure to support the FWFT extension in KVM. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 29 +++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 + arch/riscv/kvm/vcpu_sbi_fwft.c | 216 +++++++++++++++++++++ 7 files changed, 256 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h create mode 100644 arch/riscv/kvm/vcpu_sbi_fwft.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 4fa02e082142..c3f880763b9a 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -281,6 +282,9 @@ struct kvm_vcpu_arch { /* Performance monitoring context */ struct kvm_pmu pmu_context; =20 + /* Firmware feature SBI extension context */ + struct kvm_sbi_fwft fwft_context; + /* 'static' configurations which are set only once */ struct kvm_vcpu_config cfg; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index cb68b3a57c8f..ffd03fed0c06 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -98,6 +98,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_h= sm; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_susp; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/includ= e/asm/kvm_vcpu_sbi_fwft.h new file mode 100644 index 000000000000..9ba841355758 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#ifndef __KVM_VCPU_RISCV_FWFT_H +#define __KVM_VCPU_RISCV_FWFT_H + +#include + +struct kvm_sbi_fwft_feature; + +struct kvm_sbi_fwft_config { + const struct kvm_sbi_fwft_feature *feature; + bool supported; + unsigned long flags; +}; + +/* FWFT data structure per vcpu */ +struct kvm_sbi_fwft { + struct kvm_sbi_fwft_config *configs; +}; + +#define vcpu_to_fwft(vcpu) (&(vcpu)->arch.fwft_context) + +#endif /* !__KVM_VCPU_RISCV_FWFT_H */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 5f59fd226cc5..5ba77a3d9f6e 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -204,6 +204,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_STA, KVM_RISCV_SBI_EXT_SUSP, + KVM_RISCV_SBI_EXT_FWFT, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 4e0bba91d284..06e2d52a9b88 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -26,6 +26,7 @@ kvm-y +=3D vcpu_onereg.o kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o kvm-y +=3D vcpu_sbi.o kvm-y +=3D vcpu_sbi_base.o +kvm-y +=3D vcpu_sbi_fwft.o kvm-y +=3D vcpu_sbi_hsm.o kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_sbi_pmu.o kvm-y +=3D vcpu_sbi_replace.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 50be079b5528..0748810c0252 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -78,6 +78,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_STA, .ext_ptr =3D &vcpu_sbi_ext_sta, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_FWFT, + .ext_ptr =3D &vcpu_sbi_ext_fwft, + }, { .ext_idx =3D KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr =3D &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c new file mode 100644 index 000000000000..b0f66c7bf010 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#include +#include +#include +#include +#include +#include +#include + +struct kvm_sbi_fwft_feature { + /** + * @id: Feature ID + */ + enum sbi_fwft_feature_t id; + + /** + * @supported: Check if the feature is supported on the vcpu + * + * This callback is optional, if not provided the feature is assumed to + * be supported + */ + bool (*supported)(struct kvm_vcpu *vcpu); + + /** + * @set: Set the feature value + * + * Return SBI_SUCCESS on success or an SBI error (SBI_ERR_*) + * + * This callback is mandatory + */ + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long value); + + /** + * @get: Get the feature current value + * + * Return SBI_SUCCESS on success or an SBI error (SBI_ERR_*) + * + * This callback is mandatory + */ + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long *value); +}; + +static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { + SBI_FWFT_MISALIGNED_EXC_DELEG, + SBI_FWFT_LANDING_PAD, + SBI_FWFT_SHADOW_STACK, + SBI_FWFT_DOUBLE_TRAP, + SBI_FWFT_PTE_AD_HW_UPDATING, + SBI_FWFT_POINTER_MASKING_PMLEN, +}; + +static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(kvm_fwft_defined_features); i++) { + if (kvm_fwft_defined_features[i] =3D=3D feature) + return true; + } + + return false; +} + +static const struct kvm_sbi_fwft_feature features[] =3D { +}; + +static struct kvm_sbi_fwft_config * +kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) +{ + int i; + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + if (fwft->configs[i].feature->id =3D=3D feature) + return &fwft->configs[i]; + } + + return NULL; +} + +static int kvm_fwft_get_feature(struct kvm_vcpu *vcpu, u32 feature, + struct kvm_sbi_fwft_config **conf) +{ + struct kvm_sbi_fwft_config *tconf; + + tconf =3D kvm_sbi_fwft_get_config(vcpu, feature); + if (!tconf) { + if (kvm_fwft_is_defined_feature(feature)) + return SBI_ERR_NOT_SUPPORTED; + + return SBI_ERR_DENIED; + } + + if (!tconf->supported) + return SBI_ERR_NOT_SUPPORTED; + + *conf =3D tconf; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 feature, + unsigned long value, unsigned long flags) +{ + int ret; + struct kvm_sbi_fwft_config *conf; + + ret =3D kvm_fwft_get_feature(vcpu, feature, &conf); + if (ret) + return ret; + + if ((flags & ~SBI_FWFT_SET_FLAG_LOCK) !=3D 0) + return SBI_ERR_INVALID_PARAM; + + if (conf->flags & SBI_FWFT_SET_FLAG_LOCK) + return SBI_ERR_DENIED_LOCKED; + + conf->flags =3D flags; + + return conf->feature->set(vcpu, conf, value); +} + +static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, + unsigned long *value) +{ + int ret; + struct kvm_sbi_fwft_config *conf; + + ret =3D kvm_fwft_get_feature(vcpu, feature, &conf); + if (ret) + return ret; + + return conf->feature->get(vcpu, conf, value); +} + +static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_FWFT_SET: + ret =3D kvm_sbi_fwft_set(vcpu, cp->a0, cp->a1, cp->a2); + break; + case SBI_EXT_FWFT_GET: + ret =3D kvm_sbi_fwft_get(vcpu, cp->a0, &retdata->out_val); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + break; + } + + retdata->err_val =3D ret; + + return 0; +} + +static int kvm_sbi_ext_fwft_init(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int i; + + fwft->configs =3D kcalloc(ARRAY_SIZE(features), sizeof(struct kvm_sbi_fwf= t_config), + GFP_KERNEL); + if (!fwft->configs) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + feature =3D &features[i]; + conf =3D &fwft->configs[i]; + if (feature->supported) + conf->supported =3D feature->supported(vcpu); + else + conf->supported =3D true; + + conf->feature =3D feature; + } + + return 0; +} + +static void kvm_sbi_ext_fwft_deinit(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + kfree(fwft->configs); +} + +static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + for (i =3D 0; i < ARRAY_SIZE(features); i++) + fwft->configs[i].flags =3D 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { + .extid_start =3D SBI_EXT_FWFT, + .extid_end =3D SBI_EXT_FWFT, + .handler =3D kvm_sbi_ext_fwft_handler, + .init =3D kvm_sbi_ext_fwft_init, + .deinit =3D kvm_sbi_ext_fwft_deinit, + .reset =3D kvm_sbi_ext_fwft_reset, +}; --=20 2.49.0 From nobody Fri Dec 19 06:33:04 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E6F224EA91 for ; Thu, 17 Apr 2025 12:25:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892756; cv=none; b=DQmbWnKG/xq4JFyfkrlB6PDnhJV3jrbLgLjodTKqrq/wM9gGak6SAM9XOIWA1KimFSLyJOiL4ED6t6wQv0qG3QOZWaD3JuCeDtPTZZaMbcMwAig+rHQQ5eJLocYTECFjj5/wIqhjvL0zUHIZiwM0oe5+lyAx4lMJYjWJ/caP0hg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744892756; c=relaxed/simple; bh=vAB4aFxNwvgoT5WAIs3E1c62CtpY3OCKOBlBcYmIQ+g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SmF60AwG7wwzSI9doHNlFpspc9R/LispWRAfEMSpXhXS+msS+Uc7wPTCrw4wGl/4p3yjGyzI2hDB94/JOdJSxJQSkhGxKadkdIbPbth6iqqw2ng23BQx8WjICHGrUxgs06RzcNJTUF/952jFrm8RSj0KkW03ZZn7wAaMp/mWvzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=OyH1UzX4; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="OyH1UzX4" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-227d6b530d8so7159745ad.3 for ; Thu, 17 Apr 2025 05:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1744892754; x=1745497554; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uTkrNhYYE9bdipW/NOK/ur2NyEJBzn07+HWKIkSphrw=; b=OyH1UzX4sg8geFbiac98bC0cr9Lb7Jv0zTM9hMmVz7fLrDjIpaOLWZIy1MXScxZ6r6 +k4VREuV3ncP6pCsEmCli/Ks2qfWidQJgPGPzZZuH16KdW9z5IbEZeOG1XiJ/Vh9WbU8 r44iKvXansh5L8Jo8XAagGuhAm6EQxZcpqSTgagaiDpFTKjeH24ehcGonUlFO/+6GXg2 oz5IW+9PsUlKOSscJJxgpxnxlhtbYjL1feAPMSJOH7HgSPD1uabVhweoOHVNIVS/M81F 7a6Y1s5J+mJ8fnFM89DgJo9nYVyr6IXjPqhKUrf/mLDmIRVmkju+uE5ZY/JZaY5Z8oaz ZqPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744892754; x=1745497554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uTkrNhYYE9bdipW/NOK/ur2NyEJBzn07+HWKIkSphrw=; b=caJ7PDe3MFclxWcQo4lrD6X/+2PRPPCsUi064cfH7CjngemJxHZLCtf0rah9sSodzc Sb2r7jh5NRQmy6tReDudyxNONYNd9gUQGtSWxRV2+c2J7BiNrCbFLwPddsyMUVen3NOW CNp77y7JhSLAzqHChJYOCH/hyAxs5y4CAyIiHrhkJ294DLHkbyIZLfQTJsmRu0QrlTPm 9dD5/RW5/ZLlB0kLFjQDjM9RRlmJgOKSXnJBksZTS3MQ8NYPGX6mFrsDvrQBjbu64uDP MP6oxz+UkpQQrNqNucyLVGRH03J8EId81a63aRUXjGe+mYxEuIZnbuG0kwDaf8MbIgdz dNZA== X-Forwarded-Encrypted: i=1; AJvYcCUyIw+CMDEH/gbJ5gyk/uOB3O2zXuz3LlTWj3Kc+FI005Y5cq0xni3nkYeG4kUj7BnwWV2zHnyYX8MeVGM=@vger.kernel.org X-Gm-Message-State: AOJu0YwKsGvjggMpPHPdgzvZBkzEP/HZ1BxqXAzHbd/0dHYq7wKSFK5x JhOslWghZQRsG46WiabroVIt/s4qO8NpAhzay4YBbJVDvQq6D+NMTzreBpv0F9M= X-Gm-Gg: ASbGncs+goOr+ObygoG9qcGscclFLAo+K7TRgjCrJtsGp7VF+Um7nAAbOvHwIcux6+R 1hRPEqe2+vytimwlgHJDwu+aMGKuTXcNABfJGvsQAlZpLwpbJLRHL/MVsG5Bp+bg6lXSL6XBj1A k3vzeVRP5zDPdo1a1xG6RhAvPkElcZnW8BaGd7crJNOiz7SaU/u8nx6wsKHH9ETDUBzcnmpQdrQ 0/EMYD0nFgKl2BJ725HY0gLXGpzEBtVezXvgW1Xd09d0VVU0nQRrCNwNbA9iBITbTzXbpE0IiMi YGYdYVqA9G5EZnOXws6C5/w1AnGtYl+nr1grb3WV3A== X-Google-Smtp-Source: AGHT+IGDgb05pPnIfmQYcdZnqSyk1iwUEfpKUkpi5EKOyqIovfUBARsBsLViyCfGV2qgdXRRvN3wqQ== X-Received: by 2002:a17:902:e806:b0:223:5e6a:57ab with SMTP id d9443c01a7336-22c3597ee39mr83719155ad.39.1744892753939; Thu, 17 Apr 2025 05:25:53 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c3ee1a78dsm18489415ad.253.2025.04.17.05.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 05:25:53 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones , Deepak Gupta Subject: [PATCH v5 13/13] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Date: Thu, 17 Apr 2025 14:20:00 +0200 Message-ID: <20250417122337.547969-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com> References: <20250417122337.547969-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate misaligned load/store exceptions. Save and restore it during CPU load/put. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Deepak Gupta Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 36 ++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 542747e2c7f5..d98e379945c3 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -646,6 +646,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { void *nsh; struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 vcpu->cpu =3D -1; =20 @@ -671,6 +672,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D nacl_csr_read(nsh, CSR_VSTVAL); csr->hvip =3D nacl_csr_read(nsh, CSR_HVIP); csr->vsatp =3D nacl_csr_read(nsh, CSR_VSATP); + cfg->hedeleg =3D nacl_csr_read(nsh, CSR_HEDELEG); } else { csr->vsstatus =3D csr_read(CSR_VSSTATUS); csr->vsie =3D csr_read(CSR_VSIE); @@ -681,6 +683,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D csr_read(CSR_VSTVAL); csr->hvip =3D csr_read(CSR_HVIP); csr->vsatp =3D csr_read(CSR_VSATP); + cfg->hedeleg =3D csr_read(CSR_HEDELEG); } } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index b0f66c7bf010..237edaefa267 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -14,6 +14,8 @@ #include #include =20 +#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALI= GNED)) + struct kvm_sbi_fwft_feature { /** * @id: Feature ID @@ -68,7 +70,41 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_fe= ature_t feature) return false; } =20 +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *= vcpu) +{ + return misaligned_traps_can_delegate(); +} + +static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value =3D=3D 1) + csr_set(CSR_HEDELEG, MIS_DELEG); + else if (value =3D=3D 0) + csr_clear(CSR_HEDELEG, MIS_DELEG); + else + return SBI_ERR_INVALID_PARAM; + + return SBI_SUCCESS; +} + +static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) !=3D 0; + + return SBI_SUCCESS; +} + static const struct kvm_sbi_fwft_feature features[] =3D { + { + .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, + .set =3D kvm_sbi_fwft_set_misaligned_delegation, + .get =3D kvm_sbi_fwft_get_misaligned_delegation, + }, }; =20 static struct kvm_sbi_fwft_config * --=20 2.49.0