From nobody Tue Feb 10 00:00:32 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEE3424889B; Thu, 17 Apr 2025 12:04:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744891475; cv=none; b=gO3MZGQFmmojbyrxUrprYzbrPE01UNgPJRFLtMhKDvZ5G57zwVxtErMYKyRJAnhsx1qve59do9CVC6FIDAn5rlQqxOn7bg53UEe7CMlLQ6j+FT4SqtDOoaqc50dcXH50M9Pc/5cVOY3CMq2dKDIGEBlhjjlNO1IuvGpl0d9STAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744891475; c=relaxed/simple; bh=FFZHcrIEQ5bMT/STuVAA7yrMG5EaXyOGhbjfU4mkKWI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TMWmLyCnOv4vyd2a987pWiq8fn3Ed12zdQ6DTiM8UO11PWkLMGg1HNRYEOSzBM6ouQj6Lc8YtZ+2KaQFZgBKJoxs/WutLeHKEub9HTsCBMJNc4S+FryYXbHEKInkRHtT5FEGHgEC4AKyMTxFJZ1MP/VG/+Tu4+yzoEQjukYMMqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZxrchneU; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZxrchneU" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4TYU621233 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:04:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744891469; bh=6SpdcmNihc9zjX/cKvAUz7jFOlOl4KBhkhOWr2B3ok0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZxrchneUTipN7C1MbcGuClQOjhO1xAGJ5AoeoLvol6Yxt5K15n77xYcP8PCze7w1Z LlPjnxqIjXeBQd6WM7K24EUoOu1uhiiZI+nvFQnnD+vbusZP7zNtMyUZhxiNZn5MOG 0IcfG16Y2TbMdLHpNyVFRgOf5oUr1PxzGFQweZWk= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4T1s077851 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:04:29 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:04:28 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:04:28 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HC47VN004789; Thu, 17 Apr 2025 07:04:25 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1 Date: Thu, 17 Apr 2025 17:34:05 +0530 Message-ID: <20250417120407.2646929-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417120407.2646929-1-s-vadapalli@ti.com> References: <20250417120407.2646929-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe1 instance of PCIe in J721S2 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 92bf48fdbeba..da2fe83ddcf7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1394,7 +1394,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; + <0x41 0x00000000 0x00 0x1000>; reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1412,8 +1412,9 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb013>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bi= t Non-Prefetchable MEM (128 MB) */ + <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bi= t Prefetchable MEM (4 GB - (129 MB + 4 KB)) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; --=20 2.34.1