From nobody Sun Feb 8 16:45:21 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6289245039; Thu, 17 Apr 2025 12:04:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744891471; cv=none; b=PPQyojeLMQFSahEK87JJIleLpmoBHkR3zm/0Yefy7zpulYAy+kcO4dWANrzUeLH5vm0sXDjMfGqoyklZNIe0xRlu86GcxsXMs48ISkcjgcRFSd5VMYgP1g4ooH7NIyQ89nXUqWphrOQQ7uKzj1ys8e6Hr+mTGQt5lzvAVaAQPRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744891471; c=relaxed/simple; bh=hdh/cC5B5BjbJmW5jfYyNw12JwvmmMdkfFYBi1lG7Ps=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kO3lyZrDGv1ChBmw1hBdayJbytYBJl58urrJxWx4fsV4gfMCQxlx5rbLTkZ1S+KfnFc0Y+ybvIbWUE/Dg8T9nPuRwzsrAhkrm2LbDQ/fWw16pKLz5rJW+PtzVQgX+U0rvAIe6luhNR3O+QBvdCRkKcIu9pWjn+MZzaxSnwHDCMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=WsDyAgNf; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WsDyAgNf" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4IEU621229 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 07:04:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744891458; bh=WJ97kL1cYIsquQCKwHO92kMaPbc3jT3OXHsbn89VbeQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WsDyAgNfA7BZckp/WWN7/bRSAJxZIj5br7SPUkDs62eX0bd95TdIDh3SuHkbbat68 W65pr4Hyl+0THNU2V3nCgD7UAe1BIS9iFVNJ+87j5PIJTOd54NebPqCMaaIWkV3VVG fcCvzuI997A50BSS/rtakhffvaxljUvh643uup8M= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53HC4IGT083572 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 07:04:18 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 07:04:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 07:04:18 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53HC47VK004789; Thu, 17 Apr 2025 07:04:15 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Date: Thu, 17 Apr 2025 17:34:02 +0530 Message-ID: <20250417120407.2646929-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417120407.2646929-1-s-vadapalli@ti.com> References: <20250417120407.2646929-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Acked-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5ab510a0605f..e898dffdebbe 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb00f>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bi= t Non-Prefetchable MEM (128 MB) */ + <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bi= t Prefetchable MEM (4 GB - (129 MB + 4 KB)) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; --=20 2.34.1