From nobody Wed Dec 17 05:47:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98D2E1A314B; Thu, 17 Apr 2025 00:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744849607; cv=none; b=EzI9d5ILaMCjotvOWS6oZvVp3H4/pSa+3zVnc2irLhlPsG5rAKwc+ZX/nKyPb6r2H1DXmxtKJrkfSqO/Hv7pdnjhVDZOP4c8JWyjQnzPwef+V80XhAAx93pZKv/KwIwCDtzzwy3lSgIGrttMwj2/C1QTGNwridh0EPJdKrcz6HI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744849607; c=relaxed/simple; bh=kajy2/JMlSVJ/et6GDghuNi02jkWS35H2h+5DKrfDHI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K02EfS1nBMDaa4ZR/jYfTBKWdnd1Ld9RpKsQxHOJQImYgIxDHWLasuoR6prQ0JCKQigwsiTOyv7M/wSI5IUyY7r5POHOTF5TvOJqi/oHMMx4xdEDw111vDFQQ9dUeClzvUWeMqEALPuCyKIe8b/A2DjyGxddUt3I9Lswv0+2qOQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LdTs82RG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LdTs82RG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3764AC4CEEE; Thu, 17 Apr 2025 00:26:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744849607; bh=kajy2/JMlSVJ/et6GDghuNi02jkWS35H2h+5DKrfDHI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LdTs82RGRwYs0Tc+M7S8iwwJiccyIHzotUdLEBGtd6nDaFoKWxWcxEMDhQZwE0sF2 zPwksC3RLn0j2uUeBRCT74Z67LlX4bPWlmxEBUeqlFhV7XcOxYLprhwLCBHhazWtLi 40Lwrf9YhanP2BJM2/JqtIpSATlqc6BbXrcUtmkuBCH9qj2g25DtSker1llZnPqI5p uEwp15MWcAS3bmCkRx/QK56UfZ/cGfL4l1ttBViPUB9aOoCpokn8eyNriGWNUWnpSC gTlg1AOWynu2XOq0XrwC+ccDRJrs7HzHgM6cJMD7tO/j4BZnSMKdcLBVQd7sIeGzhe ogivutGZPU2tg== From: Mark Brown Date: Thu, 17 Apr 2025 01:25:21 +0100 Subject: [PATCH v5 17/28] KVM: arm64: Support SME identification registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250417-kvm-arm64-sme-v5-17-f469a2d5f574@kernel.org> References: <20250417-kvm-arm64-sme-v5-0-f469a2d5f574@kernel.org> In-Reply-To: <20250417-kvm-arm64-sme-v5-0-f469a2d5f574@kernel.org> To: Marc Zyngier , Oliver Upton , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan Cc: Dave Martin , Fuad Tabba , Mark Rutland , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5418; i=broonie@kernel.org; h=from:subject:message-id; bh=kajy2/JMlSVJ/et6GDghuNi02jkWS35H2h+5DKrfDHI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoAEp8Tk1JXoXy0dd8Noa27wLHoNhQeelxsnr2x6rL cAmmigWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaABKfAAKCRAk1otyXVSH0GCaB/ 9DwSFt/FqoTE5/y6Y6yf8iaYKKT+HIwxqWuzYOlhDvYh14vOco+k9CRN5EWPpRnLCGsoB6WGSiy1mK phXMm4o7mwDt870V91WYvRCBRYM+tkdhxT4O3AQ1tlRHcI2iiw4459qNJ6jJ4Ia2Vpnz+fU8BWfU9J dF0NKs8gQWYVLZn+EarthL7JSTIDvrWUeA4lqrRiTCuBfiIVBM/obNUoC7aM/86wvp9HPISngulJ3F WeHfp9ooTlOmKEADgBuInekwkYaaesg6HA3HOaLMDxdZCDxa6FhpRv97B35x/LY0Z4kteK0BAFWrcb OXCT/b93rmIh7WGtG+p1Ea35p76GLQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The primary register for identifying SME is ID_AA64PFR1_EL1.SME. This is hidden from guests unless SME is enabled by the VMM. When it is visible it is writable and can be used to control the availability of SME2. There is also a new register ID_AA64SMFR0_EL1 which we make writable, forcing it to all bits 0 if SME is disabled. This includes the field SMEver giving the SME version, userspace is responsible for ensuring the value is consistent with ID_AA64PFR1_EL1.SME. It also includes FA64, a separately enableable extension which provides the full FPSIMD and SVE instruction set including FFR in streaming mode. Userspace can control the availability of FA64 by writing to this field. The other features enumerated there only add new instructions, there are no architectural controls for these. There is a further identification register SMIDR_EL1 which provides a basic description of the SME microarchitecture, in a manner similar to MIDR_EL1 for the PE. It also describes support for priority management and a basic affinity description for shared SME units, plus some RES0 space. We do not support priority management and affinity is not meaningful for guests so we mask out everything except for the microarchitecture description. As for MIDR_EL1 and REVIDR_EL1 we expose the implementer and revision information to guests with the raw value from the CPU we are running on, this may present issues for asymmetric systems or for migration as it does for the existing registers. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++= ---- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 645c7c694cf2..d86396b1b1e7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -484,6 +484,7 @@ enum vcpu_sysreg { /* FP/SIMD/SVE */ SVCR, FPMR, + SMIDR_EL1, /* Streaming Mode Identification Register */ =20 /* 32bit specific registers. */ DACR32_EL2, /* Domain Access Control Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 84a745e392d4..96888554fef5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -774,6 +774,38 @@ static u64 reset_mpidr(struct kvm_vcpu *vcpu, const st= ruct sys_reg_desc *r) return mpidr; } =20 +static u64 reset_smidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u64 smidr =3D 0; + + if (!system_supports_sme()) + return smidr; + + smidr =3D read_sysreg_s(SYS_SMIDR_EL1); + + /* + * Mask out everything except for the implementer and revison, + * in particular priority management is not implemented. + */ + smidr &=3D SMIDR_EL1_IMPLEMENTER_MASK | SMIDR_EL1_REVISION_MASK; + + vcpu_write_sys_reg(vcpu, smidr, SMIDR_EL1); + + return smidr; +} + +static bool access_smidr(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + return write_to_read_only(vcpu, p, r); + + p->regval =3D vcpu_read_sys_reg(vcpu, r->reg); + + return true; +} + static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -1604,7 +1636,9 @@ static u64 __kvm_read_sanitised_id_reg(const struct k= vm_vcpu *vcpu, if (!kvm_has_mte(vcpu->kvm)) val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); =20 - val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); + if (!vcpu_has_sme(vcpu)) + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); @@ -1721,6 +1755,10 @@ static unsigned int id_visibility(const struct kvm_v= cpu *vcpu, if (!vcpu_has_sve(vcpu)) return REG_RAZ; break; + case SYS_ID_AA64SMFR0_EL1: + if (!vcpu_has_sme(vcpu)) + return REG_RAZ; + break; } =20 return 0; @@ -2845,7 +2883,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | - ID_AA64PFR1_EL1_SME | ID_AA64PFR1_EL1_RES0 | ID_AA64PFR1_EL1_MPAM_frac | ID_AA64PFR1_EL1_RAS_frac | @@ -2853,7 +2890,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), - ID_HIDDEN(ID_AA64SMFR0_EL1), + ID_WRITABLE(ID_AA64SMFR0_EL1, ~ID_AA64SMFR0_EL1_RES0), ID_UNALLOCATED(4,6), ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), =20 @@ -3052,7 +3089,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, .set_user =3D set_clidr, .val =3D ~CLIDR_EL1_RES0 }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, - { SYS_DESC(SYS_SMIDR_EL1), undef_access }, + { SYS_DESC(SYS_SMIDR_EL1), .access =3D access_smidr, .reset =3D reset_smi= dr, + .reg =3D SMIDR_EL1, .visibility =3D sme_visibility }, IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, ID_FILTERED(CTR_EL0, ctr_el0, --=20 2.39.5