From nobody Wed Dec 17 05:48:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A3022144B9; Thu, 17 Apr 2025 00:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744849600; cv=none; b=LkHpJn6hrlOd20WzWZOJpkb5BVD/2i4JkI67NQBkxGEGe5Cw7SyBmPgqmLNgw4I2nI8aLM0bAk09C+brfbXwbmbqDtJB5uXigdju0hhICnbwy6un2aJ5W4wxrQvwjD7P4d6bIWPYciupQdXWxASS+h9MGXyL1rYzWtbJgeXSHa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744849600; c=relaxed/simple; bh=EjHK+Xq+IbGu7Ta3fs6RVjmba+ozioK7IwUeQp54oGE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rzFXE4bNZY7vM4GwdS5s6ugw3OKKJc+Iv8yaxuraN0j6lYd+ppt4vdiS0almN9wGk/PnLwwLnfwdStgKFAaFf3EVfDEbBsu5RVVTOtKy1rl/lvb6UzdV5TGZRYiYDW6jusPobp9ndhjReeA5MhSJBn7epimAS8Bd/UBlyD9gISg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HgEMlAY4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HgEMlAY4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E646EC4CEE2; Thu, 17 Apr 2025 00:26:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744849600; bh=EjHK+Xq+IbGu7Ta3fs6RVjmba+ozioK7IwUeQp54oGE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HgEMlAY4GOXsPX4tHUuCAOI5mHLV9OtuIL5Mlv9jvwQMP9ORK2Z+tRr9aPchwnDOS E/Ra9H0INveIgrIxvGPRzJzdfnFwDomQg3pfQBGTpzD8qRm2x8X1JYSrdlcWOT65ig rAhHvOvpt0dEcK4RqGJRblwGZAGgKSAV1LbT2G+deEipPY31oQLx94aaL0ROgIB3cg 3fq9VuGcA1rg7CaEuXbM+xTS0Tc8R4Jo3nw6xNgJTwP8qQjGFEgYh4ClZkS1yIWl1s ezeXeUQ4P4+FUKBMa4Xi1Y8/pdxtl8TuHEiXgPh2ghItdWL74H7Oig84eV8B8j46v8 ae30LG5HeGvYg== From: Mark Brown Date: Thu, 17 Apr 2025 01:25:19 +0100 Subject: [PATCH v5 15/28] KVM: arm64: Support SME control registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250417-kvm-arm64-sme-v5-15-f469a2d5f574@kernel.org> References: <20250417-kvm-arm64-sme-v5-0-f469a2d5f574@kernel.org> In-Reply-To: <20250417-kvm-arm64-sme-v5-0-f469a2d5f574@kernel.org> To: Marc Zyngier , Oliver Upton , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan Cc: Dave Martin , Fuad Tabba , Mark Rutland , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4764; i=broonie@kernel.org; h=from:subject:message-id; bh=EjHK+Xq+IbGu7Ta3fs6RVjmba+ozioK7IwUeQp54oGE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoAEp6wHNYkZp95SjvgCDIyxYpztZRY032tQC32QXu Ykr1e5eJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaABKegAKCRAk1otyXVSH0ObzB/ 4rPpDfza+6+QcDVqs+YmqyDKvD90oSlCvOq1GbhMMmyS+tiIDD7dHsojHWB0i85S843Wa9BEArVdG/ 4LDypRTBf45TubAfVUhsYlKkGOfohJp4AZnCrmXFG9VLI3O7Bzcqv1IUjDtLb3G4wUDeoVipbDlsQ/ ZJyMCEx6NRmQj5PwM3I78vy7oLEyUUvTvAmdyLnmlPBTD8SpJg5D6FxgA++LCzbK3Tcvf510y+by8s E4cCFKf0HwzwRYr6MQ+czH8Fjyc1Qd93czrZCMGRk4tYZZMhWTlExj7qqjVhQyhQr65Cmj/G3D4goX d94NfkbWTX8fcWaGlQ44peaRrDcSwX X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME is configured by the system registers SMCR_EL1 and SMCR_EL2, add definitions and userspace access for them. These control the SME vector length in a manner similar to that for SVE and also have feature enable bits for SME2 and FA64. A subsequent patch will add management of them for guests as part of the general floating point context switch, as is done for the equivalent SVE registers. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/asm/vncr_mapping.h | 1 + arch/arm64/kvm/sys_regs.c | 37 +++++++++++++++++++++++++++++++= +++- 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8ac63de0a045..b15de8319a65 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -496,6 +496,7 @@ enum vcpu_sysreg { CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ ZCR_EL2, /* SVE Control Register (EL2) */ + SMCR_EL2, /* SME Control Register (EL2) */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ @@ -533,6 +534,7 @@ enum vcpu_sysreg { VNCR(ACTLR_EL1),/* Auxiliary Control Register */ VNCR(CPACR_EL1),/* Coprocessor Access Control */ VNCR(ZCR_EL1), /* SVE Control */ + VNCR(SMCR_EL1), /* SME Control */ VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ VNCR(TCR_EL1), /* Translation Control Register */ diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 4f9bbd4d6c26..74fc7400efbc 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -42,6 +42,7 @@ #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 #define VNCR_HAFGRTR_EL2 0x1E8 +#define VNCR_SMCR_EL1 0x1F0 #define VNCR_TTBR0_EL1 0x200 #define VNCR_TTBR1_EL1 0x210 #define VNCR_FAR_EL1 0x220 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0fc33134ac41..58ec44aac5c9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -143,6 +143,7 @@ static bool get_el2_to_el1_mapping(unsigned int reg, MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); + MAPPED_EL2_SYSREG(SMCR_EL2, SMCR_EL1, NULL ); MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); default: return false; @@ -2521,6 +2522,37 @@ static bool access_gic_elrsr(struct kvm_vcpu *vcpu, return true; } =20 +static unsigned int sme_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, sme_visibility); +} + +static bool access_smcr_el2(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + unsigned int vq; + u64 smcr; + + if (guest_hyp_sve_traps_enabled(vcpu)) { + kvm_inject_nested_sve_trap(vcpu); + return true; + } + + if (!p->is_write) { + p->regval =3D vcpu_read_sys_reg(vcpu, SMCR_EL2); + return true; + } + + smcr =3D p->regval; + vq =3D SYS_FIELD_GET(SMCR_ELx, LEN, smcr) + 1; + vq =3D min(vq, vcpu_sme_max_vq(vcpu)); + vcpu_write_sys_reg(vcpu, SYS_FIELD_PREP(SMCR_ELx, LEN, vq - 1), + SMCR_EL2); + return true; +} + static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2902,7 +2934,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility =3D sve= _visibility }, { SYS_DESC(SYS_TRFCR_EL1), undef_access }, { SYS_DESC(SYS_SMPRI_EL1), undef_access }, - { SYS_DESC(SYS_SMCR_EL1), undef_access }, + { SYS_DESC(SYS_SMCR_EL1), NULL, reset_val, SMCR_EL1, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, @@ -3256,6 +3288,9 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), =20 + EL2_REG_FILTERED(SMCR_EL2, access_smcr_el2, reset_val, 0, + sme_el2_visibility), + EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), --=20 2.39.5