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Thu, 17 Apr 2025 10:47:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53HAlnYJ019982 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Apr 2025 10:47:49 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Apr 2025 03:47:44 -0700 From: Luo Jie Date: Thu, 17 Apr 2025 18:47:13 +0800 Subject: [PATCH v3 6/6] arm64: mm: Convert the opencoded field modify Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250417-field_modify-v3-6-6f7992aafcb7@quicinc.com> References: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> In-Reply-To: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> To: Yury Norov , Rasmus Villemoes , Julia Lawall , "Nicolas Palix" , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/mm/context.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b2ac06246327..4fbac8e74149 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -361,8 +361,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_s= truct *mm) ttbr0 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); =20 /* Set ASID in TTBR1 since TCR.A1 is set */ - ttbr1 &=3D ~TTBR_ASID_MASK; - ttbr1 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + FIELD_MODIFY(TTBR_ASID_MASK, &ttbr1, asid); =20 cpu_set_reserved_ttbr0_nosync(); write_sysreg(ttbr1, ttbr1_el1); --=20 2.34.1