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Thu, 17 Apr 2025 10:47:45 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53HAliWc013807 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Apr 2025 10:47:44 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Apr 2025 03:47:40 -0700 From: Luo Jie Date: Thu, 17 Apr 2025 18:47:12 +0800 Subject: [PATCH v3 5/6] arm64: kvm: Convert the opencoded field modify Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250417-field_modify-v3-5-6f7992aafcb7@quicinc.com> References: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> In-Reply-To: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> To: Yury Norov , Rasmus Villemoes , Julia Lawall , "Nicolas Palix" , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-= mmio-v3.c index ae4c0593d114..946db5b3500f 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -123,10 +123,8 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *v= cpu, val &=3D ~GICD_CTLR_nASSGIreq; =20 /* Dist stays enabled? nASSGIreq is RO */ - if (was_enabled && dist->enabled) { - val &=3D ~GICD_CTLR_nASSGIreq; - val |=3D FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); - } + if (was_enabled && dist->enabled) + FIELD_MODIFY(GICD_CTLR_nASSGIreq, &val, is_hwsgi); =20 /* Switching HW SGIs? */ dist->nassgireq =3D val & GICD_CTLR_nASSGIreq; --=20 2.34.1