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Even though a helper xxx_replace_bits() is available, it is not well documented, and only reports errors at the run time, which will not be helpful to catch possible overflow errors due to incorrect parameter types used. Add the helper FIELD_MODIFY() to the FIELD_XXX family of bitfield macros. It is functionally similar as xxx_replace_bits(), and in addition adds the compile time type checking. FIELD_MODIFY(REG_FIELD_C, ®, c) is the wrapper of the code below. reg &=3D ~REG_FIELD_C; reg |=3D FIELD_PREP(REG_FIELD_C, c); Signed-off-by: Luo Jie --- include/linux/bitfield.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 63928f173223..2eaefa76f759 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -8,6 +8,7 @@ #define _LINUX_BITFIELD_H =20 #include +#include #include =20 /* @@ -38,8 +39,7 @@ * FIELD_PREP(REG_FIELD_D, 0x40); * * Modify: - * reg &=3D ~REG_FIELD_C; - * reg |=3D FIELD_PREP(REG_FIELD_C, c); + * FIELD_MODIFY(REG_FIELD_C, ®, c); */ =20 #define __bf_shf(x) (__builtin_ffsll(x) - 1) @@ -156,6 +156,23 @@ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) =20 +/** + * FIELD_MODIFY() - modify a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_reg_p: pointer to the memory that should be updated + * @_val: value to store in the bitfield + * + * FIELD_MODIFY() modifies the set of bits in @_reg_p specified by @_mask, + * by replacing them with the bitfield value passed in as @_val. + */ +#define FIELD_MODIFY(_mask, _reg_p, _val) \ + ({ \ + typecheck_pointer(_reg_p); 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Signed-off-by: Luo Jie --- scripts/coccinelle/misc/field_modify.cocci | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/scripts/coccinelle/misc/field_modify.cocci b/scripts/coccinell= e/misc/field_modify.cocci new file mode 100644 index 000000000000..9022c1b23291 --- /dev/null +++ b/scripts/coccinelle/misc/field_modify.cocci @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Replaced below code with the wrapper FIELD_MODIFY(MASK, ®, val) +/// - reg &=3D ~MASK; +/// - reg |=3D FIELD_PREP(MASK, val); +// +// Confidence: High +// Author: Luo Jie +// Copyright (C) 2025 Qualcomm Innovation Center, Inc. +// URL: https://coccinelle.gitlabpages.inria.fr/website +// Keywords: FIELD_PREP, FIELD_MODIFY +// Options: --include-headers + +virtual patch + +@depends on patch@ +identifier reg, val; +constant mask; +symbol FIELD_PREP, FIELD_MODIFY; +@@ + +- reg &=3D ~mask; +- reg |=3D FIELD_PREP(mask, val); ++ FIELD_MODIFY(mask, ®, val); --=20 2.34.1 From nobody Sun Dec 14 19:24:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A67F2309AD for ; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/include/asm/tlbflush.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlb= flush.h index eba1a98657f1..0d250ef4161c 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -112,8 +112,7 @@ static inline unsigned long get_trans_granule(void) level >=3D 0 && level <=3D 3) { \ u64 ttl =3D level & 3; \ ttl |=3D get_trans_granule() << 2; \ - arg &=3D ~TLBI_TTL_MASK; \ - arg |=3D FIELD_PREP(TLBI_TTL_MASK, ttl); \ + FIELD_MODIFY(TLBI_TTL_MASK, &arg, ttl); \ } \ \ __tlbi(op, arg); \ --=20 2.34.1 From nobody Sun Dec 14 19:24:22 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEDD2230988 for ; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/kvm/hyp/include/nvhe/memory.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/memory.h b/arch/arm64/kvm/hyp/= include/nvhe/memory.h index 34233d586060..b2af748964d0 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/memory.h +++ b/arch/arm64/kvm/hyp/include/nvhe/memory.h @@ -30,8 +30,7 @@ enum pkvm_page_state { static inline enum kvm_pgtable_prot pkvm_mkstate(enum kvm_pgtable_prot pro= t, enum pkvm_page_state state) { - prot &=3D ~PKVM_PAGE_STATE_PROT_MASK; - prot |=3D FIELD_PREP(PKVM_PAGE_STATE_PROT_MASK, state); + FIELD_MODIFY(PKVM_PAGE_STATE_PROT_MASK, &prot, state); return prot; } =20 --=20 2.34.1 From nobody Sun Dec 14 19:24:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E55EB22F38C for ; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-= mmio-v3.c index ae4c0593d114..946db5b3500f 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -123,10 +123,8 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *v= cpu, val &=3D ~GICD_CTLR_nASSGIreq; =20 /* Dist stays enabled? nASSGIreq is RO */ - if (was_enabled && dist->enabled) { - val &=3D ~GICD_CTLR_nASSGIreq; - val |=3D FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); - } + if (was_enabled && dist->enabled) + FIELD_MODIFY(GICD_CTLR_nASSGIreq, &val, is_hwsgi); =20 /* Switching HW SGIs? */ dist->nassgireq =3D val & GICD_CTLR_nASSGIreq; --=20 2.34.1 From nobody Sun Dec 14 19:24:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 586BE233732 for ; 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Thu, 17 Apr 2025 10:47:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53HAlnYJ019982 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Apr 2025 10:47:49 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Apr 2025 03:47:44 -0700 From: Luo Jie Date: Thu, 17 Apr 2025 18:47:13 +0800 Subject: [PATCH v3 6/6] arm64: mm: Convert the opencoded field modify Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250417-field_modify-v3-6-6f7992aafcb7@quicinc.com> References: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> In-Reply-To: <20250417-field_modify-v3-0-6f7992aafcb7@quicinc.com> To: Yury Norov , Rasmus Villemoes , Julia Lawall , "Nicolas Palix" , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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- reg |=3D FIELD_PREP(MASK, val); The semantic patch that makes this change is available in scripts/coccinelle/misc/field_modify.cocci. More information about semantic patching is available at https://coccinelle.gitlabpages.inria.fr/website Signed-off-by: Luo Jie --- arch/arm64/mm/context.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b2ac06246327..4fbac8e74149 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -361,8 +361,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_s= truct *mm) ttbr0 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); =20 /* Set ASID in TTBR1 since TCR.A1 is set */ - ttbr1 &=3D ~TTBR_ASID_MASK; - ttbr1 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + FIELD_MODIFY(TTBR_ASID_MASK, &ttbr1, asid); =20 cpu_set_reserved_ttbr0_nosync(); write_sysreg(ttbr1, ttbr1_el1); --=20 2.34.1