From nobody Tue Dec 16 08:56:14 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6F918FDD5 for ; Wed, 16 Apr 2025 14:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744814239; cv=none; b=qqhWZgKU759fvddiTTbxbFM200St0sTFhh4ML+DUH1XxaUb/DwbMZqFJSkHL6txvvbWpa8JdcNil011e+CNvIrVGbX1uMaLlySJRevWQbYRjK85aek/xSdIrgrHh00Fyqx8IAphWERFcnhXD2v7kgOMoKN5J9DQy7SQoBsAdxFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744814239; c=relaxed/simple; bh=8Kjdn5BbC4mwPz7a+XUvnbjE4mQYNVfpupBgbjpZxdw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c+gSpG3SCj9ZofO74eYk3RbuYXh60+BCc4o+aS9kaIrVeaPrQ6wrNdkaZGCEYwypX5MCTzUv0dSD7T+0pu4V7tJ43f0VaI45QH/vg3fJQPQJ9Y8btGFtbYs7iU3PzK/jfvGHbS1R4EfvzNjazkgm+Ir2wMXvZ54utXd/zCUvnAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=0OmFYpiI; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="0OmFYpiI" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4E0E8C9722; Wed, 16 Apr 2025 16:27:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1744813677; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=gai6Yh0IHeScDh3I4+epSp9DgjIHHr9iXOrYzQ4bXLY=; b=0OmFYpiIJP2WFDK2BvruxJ3L80n1q/S+di7uKdiDH/blcBTPEXVABwwxVuyJDPUSi1WdW7 J2Aud53DAQJQ5xTloqmdWE1K2w4245Bt6EPzFcoo64orttlgJEfbPr2+imGybH+LoQhRml 24DUSNp7UyZOVqkWVtKo5snWUF/GMP0BHRI5v+H0mu3t56V2+ETEnW9yaHBNrDERMAmcws +l6wdKX5Rv47Lc+WTgC9ASa9XW+J6ezdBVI0x/fH32AwqEmFbHjJqx/OuG/naLNUb4M2c8 mRAMWPHMWhicRFj2FGzcthpVKMDNfbJtbnMKYmBDsYKTnw54t4tdzsTRF6Gv5w== From: Frieder Schrempf To: Peng Fan , Pankaj Gupta , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Frank Li , Pengutronix Kernel Team Subject: [RFC PATCH 1/5] firmware: imx: ele: Add API functions for OCOTP fuse access Date: Wed, 16 Apr 2025 16:26:20 +0200 Message-ID: <20250416142715.1042363-2-frieder@fris.de> In-Reply-To: <20250416142715.1042363-1-frieder@fris.de> References: <20250416142715.1042363-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The ELE S400 API provides read and write access to the OCOTP fuse registers. This adds the necessary API functions imx_se_read_fuse() and imx_se_write_fuse() to be used by other drivers such as the OCOTP S400 NVMEM driver. This is ported from the downstream vendor kernel. Signed-off-by: Frieder Schrempf --- drivers/firmware/imx/ele_base_msg.c | 122 ++++++++++++++++++++++++++++ drivers/firmware/imx/ele_base_msg.h | 8 ++ include/linux/firmware/imx/se_api.h | 3 + 3 files changed, 133 insertions(+) diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele= _base_msg.c index bed1a0459d8d..0dfd4d2fef5a 100644 --- a/drivers/firmware/imx/ele_base_msg.c +++ b/drivers/firmware/imx/ele_base_msg.c @@ -311,3 +311,125 @@ int ele_debug_dump(struct se_if_priv *priv) =20 return ret; } + +static int ele_read_fuse(struct se_if_priv *priv, uint16_t fuse_id, u32 *v= alue) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int rx_msg_sz =3D ELE_READ_FUSE_RSP_MSG_SZ; + int ret =3D 0; + + if (!priv) + return -EINVAL; + + tx_msg =3D kzalloc(ELE_READ_FUSE_REQ_MSG_SZ, GFP_KERNEL); + if (!tx_msg) + return -ENOMEM; + + rx_msg =3D kzalloc(rx_msg_sz, GFP_KERNEL); + if (!rx_msg) + return -ENOMEM; + + ret =3D se_fill_cmd_msg_hdr(priv, (struct se_msg_hdr *)&tx_msg->header, + ELE_READ_FUSE_REQ, ELE_READ_FUSE_REQ_MSG_SZ, + true); + if (ret) + return ret; + + tx_msg->data[0] =3D fuse_id; + + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, + ELE_READ_FUSE_REQ_MSG_SZ, rx_msg, rx_msg_sz); + if (ret < 0) + return ret; + + ret =3D se_val_rsp_hdr_n_status(priv, rx_msg, ELE_READ_FUSE_REQ, + rx_msg_sz, true); + if (ret) + return ret; + + *value =3D rx_msg->data[1]; + + return 0; +} + +/** + * imx_se_read_fuse() - API to request SE-FW to read the fuse(s) value. + * @void *se_if_data: refs to data attached to the se interface. + * @uint16_t fuse_id: Fuse identifier to read. + * @u32 *value: unsigned integer array to store the fuse values. + * + * Secure enclave like EdgeLock Enclave, manages the fuse. This API + * requests the FW to read the fuses. FW responds with the read + * values. + * + * Context: + * + * Return value: + * 0, means success. + * < 0, means failure. + */ +int imx_se_read_fuse(void *se_if_data, uint16_t fuse_id, u32 *value) +{ + return ele_read_fuse((struct se_if_priv *)se_if_data, fuse_id, value); +} +EXPORT_SYMBOL_GPL(imx_se_read_fuse); + +static int ele_write_fuse(struct se_if_priv *priv, uint16_t fuse_id, u32 v= alue) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int ret =3D 0; + + if (!priv) + return -EINVAL; + + tx_msg =3D kzalloc(ELE_WRITE_FUSE_REQ_MSG_SZ, GFP_KERNEL); + if (!tx_msg) + return -ENOMEM; + + rx_msg =3D kzalloc(ELE_WRITE_FUSE_RSP_MSG_SZ, GFP_KERNEL); + if (!rx_msg) + return -ENOMEM; + + ret =3D se_fill_cmd_msg_hdr(priv, (struct se_msg_hdr *)&tx_msg->header, + ELE_WRITE_FUSE, ELE_WRITE_FUSE_REQ_MSG_SZ, + true); + if (ret) + return ret; + + tx_msg->data[0] =3D (32 << 16) | (fuse_id << 5); + tx_msg->data[1] =3D value; + + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, + ELE_WRITE_FUSE_REQ_MSG_SZ, rx_msg, + ELE_WRITE_FUSE_RSP_MSG_SZ); + if (ret < 0) + return ret; + + ret =3D se_val_rsp_hdr_n_status(priv, rx_msg, ELE_WRITE_FUSE, + ELE_WRITE_FUSE_RSP_MSG_SZ, true); + + return ret; +} + +/** + * imx_se_write_fuse() - API to request SE-FW to write to fuses. + * @void *se_if_data: refs to data attached to the se interface. + * @uint16_t fuse_id: Fuse identifier to write to. + * @u32 value: unsigned integer value that to be written to the fuse. + * + * Secure enclave like EdgeLock Enclave, manages the fuse. This API + * requests the FW to write the fuse with the given value. + * + * Context: + * + * Return value: + * 0, means success. + * < 0, means failure. + */ +int imx_se_write_fuse(void *se_if_data, uint16_t fuse_id, u32 value) +{ + return ele_write_fuse((struct se_if_priv *)se_if_data, fuse_id, value); +} +EXPORT_SYMBOL_GPL(imx_se_write_fuse); diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele= _base_msg.h index dd89412f485e..22f553cdbc33 100644 --- a/drivers/firmware/imx/ele_base_msg.h +++ b/drivers/firmware/imx/ele_base_msg.h @@ -19,6 +19,14 @@ #define ELE_GET_INFO_REQ_MSG_SZ 0x10 #define ELE_GET_INFO_RSP_MSG_SZ 0x08 =20 +#define ELE_WRITE_FUSE 0xD6 +#define ELE_WRITE_FUSE_REQ_MSG_SZ 12 +#define ELE_WRITE_FUSE_RSP_MSG_SZ 12 + +#define ELE_READ_FUSE_REQ 0x97 +#define ELE_READ_FUSE_REQ_MSG_SZ 0x08 +#define ELE_READ_FUSE_RSP_MSG_SZ 0x0C + #define MAX_UID_SIZE (16) #define DEV_GETINFO_ROM_PATCH_SHA_SZ (32) #define DEV_GETINFO_FW_SHA_SZ (32) diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/i= mx/se_api.h index b1c4c9115d7b..9503b9363593 100644 --- a/include/linux/firmware/imx/se_api.h +++ b/include/linux/firmware/imx/se_api.h @@ -11,4 +11,7 @@ #define SOC_ID_OF_IMX8ULP 0x084d #define SOC_ID_OF_IMX93 0x9300 =20 +int imx_se_write_fuse(void *se_if_data, uint16_t fuse_id, u32 value); +int imx_se_read_fuse(void *se_if_data, uint16_t fuse_id, u32 *value); + #endif /* __SE_API_H__ */ --=20 2.49.0 From nobody Tue Dec 16 08:56:14 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E76531A0BDB for ; Wed, 16 Apr 2025 14:28:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813690; cv=none; b=rdRETyGSGSTIr5/GPHjcIeLz//YhmlKPUNvTJBfLiSz1M3CrL9aey3gqJxychGTj2JHxQ286z6032kGPq6OhNv8vpLqBOgRXuQpElE1Q/8lzqmJCsoEoAQB6u8aQsFo/CotwtcXoe9fHwcDtQiJNhHfAEzbDDOnuu8vr2gKIabY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813690; c=relaxed/simple; bh=rXcuTuH5zOkxqgN3Sr8pNB2ilF9JDsHkZP4wKqUejug=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UXYAlmZOJ2NNFlSqL52bCaqsP7YMzrxEuY5Hv2sN5ru92VOIkyJb/uTYKHekRrVunzVsYb1AzSUcgSUBx5Nm60SmtdhNqKF70mII+3Plnz9pE/fsqiIBmRMwDXXuxnB+TSZhfSuHSSBIvv0QSaXFaDgK/tph/1djyNx98h/Z8R8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=wXQq+iyb; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="wXQq+iyb" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CDC16C9753; Wed, 16 Apr 2025 16:28:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1744813684; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=O1l+l222XM8iXeSUvqOsHX7K81Z2KEzLTb1gWi+aKXM=; b=wXQq+iybqgWTN/cdYoLAjSa60rYJTwJaebxrzGGlhoeNiIy89i7DG4q93zMvImYOCGPr3S 0NTfLx/SyCvZj8lPSj7NuDLphIS5+5b8UF09u612nZaxY8JXWLNbNXLPV8AX1lB9V7mTFu yVg7X0WyEB/EQMwbpYOko0tSXfslvxcGulrCEn1t4dLMZunsDlka5BD8dwLA2Ty4jpoxGr Fi4bE4n3hIs0u3PJhE4wOb1xA50gKqnsliRUUcz0wymwHGYsSB7KO9F++fZG9KG32osDOt 1DTpn5qa8N2/zZeyfXr9Xe4zgx+lqadtxtP9vuHwIQGlaFLYRBBhU5EYg0ZgOA== From: Frieder Schrempf To: Peng Fan , Pankaj Gupta , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Sascha Hauer , Shawn Guo , Srinivas Kandagatla Cc: Frieder Schrempf , Arnd Bergmann , Fabio Estevam , Geert Uytterhoeven , Greg Kroah-Hartman , Miquel Raynal , Pengutronix Kernel Team , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Yoshihiro Shimoda Subject: [RFC PATCH 2/5] nvmem: Add i.MX OCOTP fuse driver using ELE S400 API Date: Wed, 16 Apr 2025 16:26:21 +0200 Message-ID: <20250416142715.1042363-3-frieder@fris.de> In-Reply-To: <20250416142715.1042363-1-frieder@fris.de> References: <20250416142715.1042363-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The ELE S400 API is the only way to get full read and write access to all OCOTP fuse registers. The other possible way through the FSB is limited and currently provided by the imx-ocotp-ele driver (misnamed as it currently doesn't use the ELE API at all). This provides a separate driver that uses the ELE API to provide an NVMEM device for the OTP fuses. Signed-off-by: Frieder Schrempf --- drivers/nvmem/Kconfig | 11 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/imx-ocotp-s400.c | 195 +++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+) create mode 100644 drivers/nvmem/imx-ocotp-s400.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 8671b7c974b9..b7109637f47b 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -93,6 +93,17 @@ config NVMEM_IMX_OCOTP_ELE This is a driver for the On-Chip OTP Controller (OCOTP) available on i.MX SoCs which has ELE. =20 +config NVMEM_IMX_OCOTP_S400 + tristate "i.MX On-Chip OTP support via S400 API" + depends on ARCH_MXC || COMPILE_TEST + depends on IMX_SEC_ENCLAVE + help + This is a driver for the OCOTP fuses accessed through the S400 API + of the Secure Enclave firmware. + + This driver can also be built as a module. If so, the module + will be called nvmem-imx-ocotp-s400. + config NVMEM_IMX_OCOTP_SCU tristate "i.MX8 SCU On-Chip OTP Controller support" depends on IMX_SCU diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 5b77bbb6488b..96572fd7cd6e 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -22,6 +22,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) +=3D nvmem-imx-ocotp.o nvmem-imx-ocotp-y :=3D imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_ELE) +=3D nvmem-imx-ocotp-ele.o nvmem-imx-ocotp-ele-y :=3D imx-ocotp-ele.o +obj-$(CONFIG_NVMEM_IMX_OCOTP_S400) +=3D nvmem-imx-ocotp-s400.o +nvmem-imx-ocotp-s400-y :=3D imx-ocotp-s400.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) +=3D nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y :=3D imx-ocotp-scu.o obj-$(CONFIG_NVMEM_JZ4780_EFUSE) +=3D nvmem_jz4780_efuse.o diff --git a/drivers/nvmem/imx-ocotp-s400.c b/drivers/nvmem/imx-ocotp-s400.c new file mode 100644 index 000000000000..b14d3a88f52a --- /dev/null +++ b/drivers/nvmem/imx-ocotp-s400.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Kontron Electronics GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct imx_s400_fuse_hw { + const bool reverse_mac_address; + const struct nvmem_keepout *keepout; + unsigned int nkeepout; +}; + +struct imx_s400_fuse { + const struct imx_s400_fuse_hw *hw; + struct platform_device *se_dev; + struct nvmem_config config; + struct mutex lock; + void *se_data; +}; + +static int imx_s400_fuse_read(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct imx_s400_fuse *fuse =3D priv; + u32 i, word, num_words; + int ret; + + word =3D offset >> 2; + num_words =3D bytes >> 2; + + mutex_lock(&fuse->lock); + + for (i =3D word; i < (word + num_words); i++) { + ret =3D imx_se_read_fuse(fuse->se_data, i, ((u32 *)val) + i - word); + if (ret) { + mutex_unlock(&fuse->lock); + return ret; + } + } + + mutex_unlock(&fuse->lock); + return 0; +} + +static int imx_s400_fuse_post_process(void *priv, const char *id, int inde= x, + unsigned int offset, void *data, + size_t bytes) +{ + u8 *buf =3D data; + int i; + + if (id && !strcmp(id, "mac-address")) { + for (i =3D 0; i < bytes / 2; i++) + swap(buf[i], buf[bytes - i - 1]); + } + + return 0; +} + +static int imx_s400_fuse_write(void *priv, unsigned int offset, void *val,= size_t bytes) +{ + struct imx_s400_fuse *fuse =3D priv; + u32 word =3D offset >> 2; + u32 *buf =3D val; + int ret; + + /* allow only writing one complete OTP word at a time */ + if (bytes !=3D 4) + return -EINVAL; + + /* + * The S400 API returns an error when writing an all-zero value. As + * OTP fuse bits can not be switched from 1 to 0 anyway, skip these + * values. + */ + if (!*buf) + return 0; + + mutex_lock(&fuse->lock); + ret =3D imx_se_write_fuse(fuse->se_data, word, *buf); + mutex_unlock(&fuse->lock); + + return ret; +} + +static void imx_s400_fuse_fixup_cell_info(struct nvmem_device *nvmem, + struct nvmem_cell_info *cell) +{ + cell->read_post_process =3D imx_s400_fuse_post_process; +} + +static int imx_s400_fuse_probe(struct platform_device *pdev) +{ + struct imx_s400_fuse *fuse; + struct nvmem_device *nvmem; + struct device_node *np; + + fuse =3D devm_kzalloc(&pdev->dev, sizeof(*fuse), GFP_KERNEL); + if (!fuse) + return -ENOMEM; + + fuse->hw =3D of_device_get_match_data(&pdev->dev); + + fuse->config.dev =3D &pdev->dev; + fuse->config.name =3D "imx_s400_fuse"; + fuse->config.id =3D NVMEM_DEVID_AUTO; + fuse->config.owner =3D THIS_MODULE; + fuse->config.size =3D 2048; /* 64 Banks of 8 Words */ + fuse->config.word_size =3D 4; + fuse->config.add_legacy_fixed_of_cells =3D true; + fuse->config.reg_read =3D imx_s400_fuse_read; + fuse->config.reg_write =3D imx_s400_fuse_write; + fuse->config.priv =3D fuse; + fuse->config.keepout =3D fuse->hw->keepout; + fuse->config.nkeepout =3D fuse->hw->nkeepout; + + if (fuse->hw->reverse_mac_address) + fuse->config.fixup_dt_cell_info =3D &imx_s400_fuse_fixup_cell_info; + + dev_set_drvdata(&pdev->dev, fuse); + + mutex_init(&fuse->lock); + + nvmem =3D devm_nvmem_register(&pdev->dev, &fuse->config); + if (IS_ERR(nvmem)) + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem), "failed to register nvm= em device\n"); + + np =3D of_parse_phandle(pdev->dev.of_node, "secure-enclave", 0); + if (!np) + return dev_err_probe(&pdev->dev, -ENODEV, "missing or invalid secure-enc= lave handle\n"); +=09 + fuse->se_dev =3D of_find_device_by_node(np); + of_node_put(np); + if (!fuse->se_dev) + return dev_err_probe(&pdev->dev, -ENODEV, "failed to find secure-enclave= device\n"); + + get_device(&fuse->se_dev->dev); + fuse->se_data =3D platform_get_drvdata(fuse->se_dev); + if (!fuse->se_data) + return -EPROBE_DEFER; + + dev_info(&pdev->dev, "i.MX S400 OCOTP NVMEM device registered successfull= y\n"); + + return 0; +} + +static void imx_s400_fuse_remove(struct platform_device *pdev) +{ + struct imx_s400_fuse *fuse =3D platform_get_drvdata(pdev); + put_device(&fuse->se_dev->dev); +} + +static const struct nvmem_keepout imx93_s400_keepout[] =3D { + {.start =3D 208, .end =3D 252}, + {.start =3D 256, .end =3D 512}, + {.start =3D 576, .end =3D 728}, + {.start =3D 732, .end =3D 752}, + {.start =3D 756, .end =3D 1248}, +}; + +static const struct imx_s400_fuse_hw imx93_s400_fuse_hw =3D { + .reverse_mac_address =3D true, + .keepout =3D imx93_s400_keepout, + .nkeepout =3D ARRAY_SIZE(imx93_s400_keepout), +}; + +static const struct of_device_id imx_s400_fuse_match[] =3D { + { .compatible =3D "fsl,imx93-ocotp-s400", .data =3D &imx93_s400_fuse_hw, = }, + {}, +}; + +static struct platform_driver imx_s400_fuse_driver =3D { + .driver =3D { + .name =3D "fsl-ocotp-s400", + .of_match_table =3D imx_s400_fuse_match, + }, + .probe =3D imx_s400_fuse_probe, + .remove =3D imx_s400_fuse_remove, +}; +MODULE_DEVICE_TABLE(of, imx_s400_fuse_match); +module_platform_driver(imx_s400_fuse_driver); + +MODULE_AUTHOR("Frieder Schrempf "); +MODULE_DESCRIPTION("i.MX S400 OCOTP Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.49.0 From nobody Tue Dec 16 08:56:14 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 298021ADC67; Wed, 16 Apr 2025 14:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813690; cv=none; b=Imd0ETns+IXP3M7S4F+gAqdnnkN0w0XTmfSHkUlbzwQZKi44cPHNMLLfiStpzqtYOJxZ+a6tj/mma//BpHIfE1GmzFXWQyllrGQwMbu5kUK/1+W5kKwY+kRSn2dvdLMt06zihf+QzHCTef8+3c+JoEG+KEl27tSfKgYB21z1h3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813690; c=relaxed/simple; bh=l9TDtXY7OU7uL8aV7cw32/Pd7TSJScjkzY1TxJoUmj8=; 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c=relaxed/relaxed; d=fris.de; s=dkim; t=1744813686; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=FScWshifJvIijnD4Sqm8C1fnkngATgObzxPdFsDLYYg=; b=HHdz4cUV7+QsbsguIExtP7/+cPEszjbCZcBLkQepe1fJJGz8DZuC3jSn9x5WfCWCGNbab1 AaBkVZ7sDyjXXn8HKjZ+YOHa/nORFP0DPkvHqKF7/3Imycl/4jHdUo9Zh+sk5w0i51fiFD d1YgU1sPMDuITFRA2q6IGdy66mgIueKV/GGcRKgF6rEsbOVjhgosgQucv+H4Rjz046o2vt zgxgJlG+uywRUfYwGnBljn2Y66DPq9SLYDQC6xVWUN9cC9sk5Ow+8mdUEYMQlZDqA4BS+y zJ6T/nLcz/QoIS6N3w1XfGpuDkfdKIO6mICO0Kz09k+/GK7Zk5UBUQ0WxwtKLw== From: Frieder Schrempf To: Peng Fan , Pankaj Gupta , linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Frank Li , Haibo Chen , Pengutronix Kernel Team , Shengjiu Wang , Shenwei Wang , Xu Yang Subject: [RFC PATCH 3/5] arm64: dts: imx93: Add node for EdgeLock Enclave (ELE) firmware driver Date: Wed, 16 Apr 2025 16:26:22 +0200 Message-ID: <20250416142715.1042363-4-frieder@fris.de> In-Reply-To: <20250416142715.1042363-1-frieder@fris.de> References: <20250416142715.1042363-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This adds the node for the ELE firmware driver that provides the S400 API. Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/imx93.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts= /freescale/imx93.dtsi index 64cd0776b43d..122519648d1b 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -222,6 +222,12 @@ cm33: remoteproc-cm33 { status =3D "disabled"; }; =20 + hsm0: secure-enclave { + compatible =3D "fsl,imx93-se-ele-hsm"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&s4muap 0 0>, <&s4muap 1 0>; + }; + mqs1: mqs1 { compatible =3D "fsl,imx93-mqs"; gpr =3D <&aonmix_ns_gpr>; --=20 2.49.0 From nobody Tue Dec 16 08:56:14 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFEC51B4140; Wed, 16 Apr 2025 14:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813692; cv=none; b=cXzZnkaDsT5zVTtlKLk3c0QdLyQqJm+89YlVvV1fRcTMBvTft0PjKvtB1SrC89jCy8mtmBmvwRd49trWlVCg7MebwHnnBZM95cAWzCKnmiC5HYHr4MPfTF0ZJRSX5LnY62Jg37PaRQEF0pglNZCkakbJajAZtYQ84He2xgGhB8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813692; c=relaxed/simple; bh=vQAH1jkfZEcBipxTdFXayRe3MocIsI8jltVupOf83GU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FMEVKnfhA1zu8+yTOUC7KZagTjZoe+83NAQJzlUrn7KKgp4kOW5TW2FavNroQJu2MnCGFbkhN9wNTc+gnoA/2JMvwkhNC2K4w04D8fDo4TxHVD67TyZ+uPrGmqUYEKkmcGsYjtXqEi86/pfXqbEKEIl4d905cz2NhyNdG6caKg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=eBPNbebM; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="eBPNbebM" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5DD5BC9757; Wed, 16 Apr 2025 16:28:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1744813688; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=VTVKYFoj1jaoNBJBsD0WujEyvI4IfuhmvFWnnCOeCTc=; b=eBPNbebM8LiTuWnpVtxwPDJRYk42p+WSiauqDuj5Y+Eif0imNfb+yaCX/5KjrtAxvHr5AY zk+qQLX7726CBHMNzF4NvQkWjnWW1v1wO/w8VwZKlXhtSn8bYPq4RLt9jrWsFtFvg4ebNE JcB2Wcxy+mul3bMUfyaVQfFH11axnp5Q4A/YtXgHcZrmHIxkVnbzQpl7azmHjlUFOxOked zV7hOaNTMKmscW2RBgnDSiTUTXAvFp9d0UEo17yzYiaDgJ8FKP4mYSAqO2koJbQ+bbBjGI XUpWXWsHJfZnCIOhD9nhfMnRuSW2doQuBn60slbdhb1gsZ2RD8PLXKQ1ZSMWmw== From: Frieder Schrempf To: Peng Fan , Pankaj Gupta , linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Carlos Song , Fabio Estevam , Frank Li , Haibo Chen , Pengutronix Kernel Team , Shengjiu Wang , Shenwei Wang , Xu Yang Subject: [RFC PATCH 4/5] arm64: dts: imx93: Add node for OCOTP S400 NVMEM driver Date: Wed, 16 Apr 2025 16:26:23 +0200 Message-ID: <20250416142715.1042363-5-frieder@fris.de> In-Reply-To: <20250416142715.1042363-1-frieder@fris.de> References: <20250416142715.1042363-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This adds a node for the OCOTP NVMEM driver that uses the ELE S400 API to access the fuse registers. Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/imx93.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts= /freescale/imx93.dtsi index 122519648d1b..12463cf6c214 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -228,6 +228,11 @@ hsm0: secure-enclave { mboxes =3D <&s4muap 0 0>, <&s4muap 1 0>; }; =20 + ocotp-s400 { + compatible =3D "fsl,imx93-ocotp-s400"; + secure-enclave =3D <&hsm0>; + }; + mqs1: mqs1 { compatible =3D "fsl,imx93-mqs"; gpr =3D <&aonmix_ns_gpr>; --=20 2.49.0 From nobody Tue Dec 16 08:56:14 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5C581DA634; Wed, 16 Apr 2025 14:28:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813696; cv=none; b=ir0VmBrb5F4bR1zmspLps4EKijZUWJ6B1ryn4BHJIpaPkZD+6K7pab995OhnScYVTdnrpxiFC0yol8j0ukvv7rSJZeCc7padwkPDHl0pK7KysV5++HqYZQP8muorhVguoF4+vH0w0P8WLFJd+TQtTMwY9aZNwVQ+q4xtfF8IUNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744813696; c=relaxed/simple; bh=la3Rmm9G09d9FtjBHydDxxb5tUNi7/hoVZW8CizR1E4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EBDjzKMxPojsMIkSrrEo5LJxfqdHHO5PYIdVa0uTkOfCHdr2x5rh8FUqY2OEgrhn4fgzq8DPrbIcOvUVXM7pnehMF+Vb98BYrhLFKZ4zzaxANzJ5aDeMn6d0YYky8w+YaCAma6p94PleiLusFHLWD7cCcM60dEb/iJv3k/UE3hg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=nVBXtlnK; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="nVBXtlnK" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5AD33BFC16; Wed, 16 Apr 2025 16:28:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1744813692; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=y3BV7atvuABYEEZWYNR8lZWvJ+WfpKTMmG/5nr5RLwI=; b=nVBXtlnKXK6xffDLyhBxenOKFk6R8+v7xzt1syqAOVzQisPCCrAGZpOczv8GlhEWJXz2G6 Rf5lRlEBuZf3F6f2yQQoJBV/qUZ7YtmDzdOPifbQ6cctOkczxf8vpmQs8uNUUVx0UvOYH2 8+LRw3Hy+oq1ELpiq/AXmpv1ha5vNM0cMDINSTBvRaU1dkYTUoZ+qXAdHOLTe8yyBTtZAs +mMcLGVZwbVvucLN02Btg5zOh3+ihjx6Z93f8fMPUXYsUIAe8rk2IKIn5vdHq0AtQu7L4c 0eTUYMMVLEpz2NWyIPt/LuxsAz17rTZjNwmW/z8rYyibLBPIbCmpUmS0vz+KXw== From: Frieder Schrempf To: Peng Fan , Pankaj Gupta , linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [RFC PATCH 5/5] arm64: dts: imx93-kontron: Add DMA memory region for ELE firmware Date: Wed, 16 Apr 2025 16:26:24 +0200 Message-ID: <20250416142715.1042363-6-frieder@fris.de> In-Reply-To: <20250416142715.1042363-1-frieder@fris.de> References: <20250416142715.1042363-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The Edgelock Enclave firmware requires a small 1 MiB memory pool. Reserving this pool makes the ELE firmware driver probe and allows us to use the S400 API. Signed-off-by: Frieder Schrempf --- .../boot/dts/freescale/imx93-kontron-osm-s.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/= arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 119a16207059..44d98cf812bf 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -24,6 +24,18 @@ chosen { stdout-path =3D &lpuart1; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ele_reserved: memory@90000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x90000000 0 0x100000>; + no-map; + }; + }; + reg_usdhc2_vcc: regulator-usdhc2-vcc { compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; @@ -116,6 +128,10 @@ &gpio4 { "GPIO_B_0", "CARRIER_PWR_EN"; }; =20 +&hsm0 { + memory-region =3D <&ele_reserved>; +}; + &lpi2c1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_lpi2c1>; --=20 2.49.0