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Wed, 16 Apr 2025 05:06:27 -0700 From: Shubhi Garg To: , , , , , , CC: Subject: [PATCH 1/5] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ Date: Wed, 16 Apr 2025 12:06:15 +0000 Message-ID: <20250416120619.483793-2-shgarg@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250416120619.483793-1-shgarg@nvidia.com> References: <20250416120619.483793-1-shgarg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449F:EE_|DS4PR12MB9658:EE_ X-MS-Office365-Filtering-Correlation-Id: 3316848f-7591-4744-1777-08dd7cdf2a10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?E0Vng7H3CdPFNjK0l4nhw0FFe2rDlhjg3Vx9A3fnIMGM9jttOCzhcI4uP1E4?= =?us-ascii?Q?D/DEGctOOFzQMwU3RqxhNBPCEfx3K12rz5zAbZngA0sjHV0KhN3uC4pDSKsN?= =?us-ascii?Q?3l/Z3siPbs38UPTFIDOTCAhCVPKC6SV23WXwNbW7J1M8bYzh8iUMRv/NgVnn?= =?us-ascii?Q?r8QWtyYIvYjSax+vAMoGw30ha7Afy6VvCbA8fDfmlMPIPBUiPCkoW7vA8RE7?= =?us-ascii?Q?UBUAVjZ6XeG2uuEn2LgyBNZp0+xwYw+nL9NgSqJoX/6TjnZ2cwNMwDLkCJui?= =?us-ascii?Q?VBt9OiFMvqMsfiR5ZQvyk4zW6GTQVaVmgX1L0b6eMshi3hdhGdEBQEelAqDR?= =?us-ascii?Q?9XREt1xQU4paiHrGfEDif8ru2fiwTBaYPxbanWM0X/bQMS1c8qkyV3bcjRU7?= =?us-ascii?Q?uUlm0QxMMawD20K6EKIzxktqyxIlgJhFicrra6RubKylAKeSbyCAIhCcTJyD?= =?us-ascii?Q?eJ8Xg/JwdLo13xZ85nonPAtuT7+Eeisgjlp+m46QPPP1EUygWAnLmsqr0ecC?= =?us-ascii?Q?m7m1IQ5Z4QUTo6uNNFgBr7jkeBZaTf+GqDQjdgWJOEicssOCGwY0CPoqdtMf?= =?us-ascii?Q?UA2bGcE3w78NxX6RvK3qGL4LYPngAIneMcumuE8DCA7/RrWUMJBHiY4bKqHw?= =?us-ascii?Q?kgXL2CQW7zAhi6RojQBoaHpNLNDfgyuGEclUW6cdIRsTYMdqcKDjKnwu7bNY?= =?us-ascii?Q?UkLrhF1zSAtlGfmSE1qNhy/IDUuFLrcGPnvZtACB3KdtdliYe8eBgFwDhJGw?= =?us-ascii?Q?6B1iLMop+dAK6T3lUZ5Dd+aXytyhY/q0oJsidyBnd2nc/FqpGbm7daEMJ1jf?= =?us-ascii?Q?Lk+1v/hx0XaPnzfy5MXoygYaWQ/Z0BmsvOdVkZsc+p8dDfs8a37fBykzr3oo?= =?us-ascii?Q?nhX8ZB8yqtfcy6u8fR+/UhhGhhtYJZh9dV6iDTwA3ohbr0HFtfXsR3sqMBWd?= =?us-ascii?Q?T3dx/yEBe/UbPBEy7ja/i87He5cDB5kPeS6EZ8SkgWSdwP2/PKXDgXcm71Up?= =?us-ascii?Q?qaiMT71vRVQYRPYCw0mPPyM1xYV1l3YnyYSXddizoKSXQJ4k1HYhMm8qorGj?= =?us-ascii?Q?afj9bxhoJ4aeTApq88pZzR+/FBp+RQHnKiWujFRD7/57TED+YiLg+U/srymj?= =?us-ascii?Q?Ds4RjuH/xS6qIYS+ySJEkyLMFy7+qHrpsCfLascnZpN/HplObVzqaVVjvEEf?= =?us-ascii?Q?03hNEkj6R2x24l149uwdHD+8tmbHKvJOZH8UhY+eiOganeHzZGXc8d9D7BRL?= =?us-ascii?Q?m8M+vhuCcMROKxyEW5wDdd/AN60xPZvt94qz+sNPiNYwNltQkqiZ8bWfhlaW?= =?us-ascii?Q?M5w7YI2uxol08CJj1a91YJm2hskQgNhFXaKLDs161I2B0B4MYJ1zrYZkYsJP?= =?us-ascii?Q?n+VjkOH96zfevg8D9LvyxVEq1CPt0wxf+NqhB/3yEumVekbv+AWbxN0krBO1?= =?us-ascii?Q?aS2OUmDRkGbMmJ1hi8M8wFrltOzTe+zRh9d44bEUprWqzzNQHN+YcmaF2lwi?= =?us-ascii?Q?r4jRoFwxHGVDCPinq2apmYdpy2pBw4ys8zry?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 12:06:47.9696 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3316848f-7591-4744-1777-08dd7cdf2a10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9658 Content-Type: text/plain; charset="utf-8" Add bindings for NVIDIA VRS (Voltage Regulator Specification) power sequencer device. NVIDIA VRS PSEQ controls ON/OFF and suspend/resume power sequencing of system power rails on Tegra234 SoC. This device also provides 32kHz RTC support with backup battery for system timing. Signed-off-by: Shubhi Garg --- .../bindings/mfd/nvidia,vrs-pseq.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.y= aml diff --git a/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml b/D= ocumentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml new file mode 100644 index 000000000000..d4c5984930e9 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIAT= ES. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nvidia,vrs-pseq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Voltage Regulator Specification Power Sequencer + +maintainers: + - Shubhi Garg + +description: + NVIDIA Voltage Regulator Specification Power Sequencer device controls O= N/OFF + and suspend/resume power sequencing of system power rails for NVIDIA + SoCs. It provides 32kHz RTC clock support with backup battery for + system timing. + +properties: + compatible: + const: nvidia,vrs-pseq + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger typ= e. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vrs@3c { + compatible =3D "nvidia,vrs-pseq"; + reg =3D <0x3c>; + interrupt-parent =3D <&pmc>; + interrupts =3D <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + }; --=20 2.25.1 From nobody Wed Dec 17 05:50:14 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F82323FC42; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 12:06:52.2821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa2f942b-ff52-496e-2103-08dd7cdf2ca2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9279 Content-Type: text/plain; charset="utf-8" Add NVIDIA VRS Power Sequencer device tree node for Tegra234 P3701 and P3767 platforms. Signed-off-by: Shubhi Garg --- arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 11 +++++++++++ arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 17 +++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra234-p3701.dtsi index 9086a0d010e5..d3c1f13b2b99 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi @@ -170,6 +170,17 @@ bpmp { i2c { status =3D "okay"; =20 + vrs@3c { + compatible =3D "nvidia,vrs-pseq"; + reg =3D <0x3c>; + interrupt-parent =3D <&pmc>; + /* VRS Wake ID is 24 */ + interrupts =3D <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "okay"; + }; + thermal-sensor@4c { compatible =3D "ti,tmp451"; status =3D "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra234-p3767.dtsi index 84db7132e8fc..93a787c57eba 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -121,6 +121,23 @@ pmc@c360000 { }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 12:06:48.1948 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ebf51c9-672b-489c-13c6-08dd7cdf2a30 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8226 Content-Type: text/plain; charset="utf-8" Add support for NVIDIA VRS (Voltage Regulator Specification) power sequencer device driver. This driver manages ON/OFF and suspend/resume power sequencing of system power rails for NVIDIA Tegra234 SoC. It also provides 32kHz RTC clock support with backup battery for system timing. Signed-off-by: Shubhi Garg --- drivers/mfd/Kconfig | 12 ++ drivers/mfd/Makefile | 1 + drivers/mfd/nvidia-vrs-pseq.c | 279 ++++++++++++++++++++++++++++ include/linux/mfd/nvidia-vrs-pseq.h | 127 +++++++++++++ 4 files changed, 419 insertions(+) create mode 100644 drivers/mfd/nvidia-vrs-pseq.c create mode 100644 include/linux/mfd/nvidia-vrs-pseq.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 22b936310039..b7357ff398f2 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1396,6 +1396,18 @@ config MFD_SC27XX_PMIC This driver provides common support for accessing the SC27xx PMICs, and it also adds the irq_chip parts for handling the PMIC chip events. =20 +config MFD_NVVRS_PSEQ + tristate "NVIDIA Voltage Regulator Specification Power Sequencer" + depends on I2C=3Dy + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ + help + Say Y here to add support for NVIDIA Voltage Regulator Specification + Power Sequencer. NVVRS_PSEQ supports ON/OFF, suspend/resume sequence of + system power rails. It provides 32kHz RTC clock support with backup + battery for system timing. + config RZ_MTU3 tristate "Renesas RZ/G2L MTU3a core driver" depends on (ARCH_RZG2L && OF) || COMPILE_TEST diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 948cbdf42a18..93bb2c34e341 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -182,6 +182,7 @@ obj-$(CONFIG_MFD_MT6360) +=3D mt6360-core.o obj-$(CONFIG_MFD_MT6370) +=3D mt6370.o mt6397-objs :=3D mt6397-core.o mt6397-irq.o mt6358-irq.o obj-$(CONFIG_MFD_MT6397) +=3D mt6397.o +obj-$(CONFIG_MFD_NVVRS_PSEQ) +=3D nvidia-vrs-pseq.o =20 obj-$(CONFIG_RZ_MTU3) +=3D rz-mtu3.o obj-$(CONFIG_ABX500_CORE) +=3D abx500-core.o diff --git a/drivers/mfd/nvidia-vrs-pseq.c b/drivers/mfd/nvidia-vrs-pseq.c new file mode 100644 index 000000000000..c93730168dcb --- /dev/null +++ b/drivers/mfd/nvidia-vrs-pseq.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. +// NVIDIA VRS Power Sequencer driver. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct resource rtc_resources[] =3D { + DEFINE_RES_IRQ(NVVRS_PSEQ_INT_SRC1_RTC), +}; + +static const struct regmap_irq nvvrs_pseq_irqs[] =3D { + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_RSTIRQ, 0, NVVRS_PSEQ_INT_SRC1_RSTIRQ_= MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_OSC, 0, NVVRS_PSEQ_INT_SRC1_OSC_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_EN, 0, NVVRS_PSEQ_INT_SRC1_EN_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_RTC, 0, NVVRS_PSEQ_INT_SRC1_RTC_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_PEC, 0, NVVRS_PSEQ_INT_SRC1_PEC_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_WDT, 0, NVVRS_PSEQ_INT_SRC1_WDT_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_EM_PD, 0, NVVRS_PSEQ_INT_SRC1_EM_PD_MA= SK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC1_INTERNAL, 0, NVVRS_PSEQ_INT_SRC1_INTER= NAL_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_PBSP, 1, NVVRS_PSEQ_INT_SRC2_PBSP_MASK= ), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_ECC_DED, 1, NVVRS_PSEQ_INT_SRC2_ECC_DE= D_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_TSD, 1, NVVRS_PSEQ_INT_SRC2_TSD_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_LDO, 1, NVVRS_PSEQ_INT_SRC2_LDO_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_BIST, 1, NVVRS_PSEQ_INT_SRC2_BIST_MASK= ), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_RT_CRC, 1, NVVRS_PSEQ_INT_SRC2_RT_CRC_= MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_SRC2_VENDOR, 1, NVVRS_PSEQ_INT_SRC2_VENDOR_= MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR0, 2, NVVRS_PSEQ_INT_VENDOR0_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR1, 2, NVVRS_PSEQ_INT_VENDOR1_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR2, 2, NVVRS_PSEQ_INT_VENDOR2_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR3, 2, NVVRS_PSEQ_INT_VENDOR3_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR4, 2, NVVRS_PSEQ_INT_VENDOR4_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR5, 2, NVVRS_PSEQ_INT_VENDOR5_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR6, 2, NVVRS_PSEQ_INT_VENDOR6_MASK), + REGMAP_IRQ_REG(NVVRS_PSEQ_INT_VENDOR7, 2, NVVRS_PSEQ_INT_VENDOR7_MASK), +}; + +static const struct mfd_cell nvvrs_pseq_children[] =3D { + { + .name =3D "nvvrs-pseq-rtc", + .resources =3D rtc_resources, + .num_resources =3D ARRAY_SIZE(rtc_resources), + }, +}; + +static const struct regmap_range nvvrs_pseq_readable_ranges[] =3D { + regmap_reg_range(NVVRS_PSEQ_REG_VENDOR_ID, NVVRS_PSEQ_REG_MODEL_REV), + regmap_reg_range(NVVRS_PSEQ_REG_INT_SRC1, NVVRS_PSEQ_REG_LAST_RST), + regmap_reg_range(NVVRS_PSEQ_REG_EN_ALT_F, NVVRS_PSEQ_REG_IEN_VENDOR), + regmap_reg_range(NVVRS_PSEQ_REG_RTC_T3, NVVRS_PSEQ_REG_RTC_A0), + regmap_reg_range(NVVRS_PSEQ_REG_WDT_CFG, NVVRS_PSEQ_REG_WDTKEY), +}; + +static const struct regmap_access_table nvvrs_pseq_readable_table =3D { + .yes_ranges =3D nvvrs_pseq_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(nvvrs_pseq_readable_ranges), +}; + +static const struct regmap_range nvvrs_pseq_writable_ranges[] =3D { + regmap_reg_range(NVVRS_PSEQ_REG_INT_SRC1, NVVRS_PSEQ_REG_INT_VENDOR), + regmap_reg_range(NVVRS_PSEQ_REG_GP_OUT, NVVRS_PSEQ_REG_IEN_VENDOR), + regmap_reg_range(NVVRS_PSEQ_REG_RTC_T3, NVVRS_PSEQ_REG_RTC_A0), + regmap_reg_range(NVVRS_PSEQ_REG_WDT_CFG, NVVRS_PSEQ_REG_WDTKEY), +}; + +static const struct regmap_access_table nvvrs_pseq_writable_table =3D { + .yes_ranges =3D nvvrs_pseq_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(nvvrs_pseq_writable_ranges), +}; + +static const struct regmap_config nvvrs_pseq_regmap_config =3D { + .name =3D "nvvrs-pseq", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D NVVRS_PSEQ_REG_WDTKEY + 1, + .cache_type =3D REGCACHE_RBTREE, + .rd_table =3D &nvvrs_pseq_readable_table, + .wr_table =3D &nvvrs_pseq_writable_table, +}; + +static int nvvrs_pseq_irq_clear(void *irq_drv_data) +{ + struct nvvrs_pseq_chip *chip =3D (struct nvvrs_pseq_chip *)irq_drv_data; + struct i2c_client *client =3D chip->client; + u8 reg, val; + unsigned int i; + int ret =3D 0; + + /* Write 1 to clear the interrupt bit in the Interrupt + * Source Register, writing 0 has no effect, writing 1 to a bit + * which is already at 0 has no effect + */ + + for (i =3D 0; i < chip->irq_chip->num_regs; i++) { + reg =3D (u8)(chip->irq_chip->status_base + i); + ret =3D i2c_smbus_read_byte_data(client, reg); + if (ret < 0) { + dev_err(chip->dev, "Failed to read interrupt register: 0x%02x, ret=3D%d= \n", + reg, ret); + return ret; + } else if (ret > 0) { + val =3D (u8)ret; + dev_dbg(chip->dev, "Clearing interrupts! Interrupt status reg 0x%02x = =3D 0x%02x\n", + reg, val); + + /* Clear interrupt */ + ret =3D i2c_smbus_write_byte_data(client, reg, val); + if (ret < 0) { + dev_err(chip->dev, "Failed to write interrupt register: 0x%02x, ret=3D= %d\n", + reg, ret); + return ret; + } + } + } + + return 0; +} + +static const struct regmap_irq_chip nvvrs_pseq_irq_chip =3D { + .name =3D "nvvrs-pseq-irq", + .irqs =3D nvvrs_pseq_irqs, + .num_irqs =3D ARRAY_SIZE(nvvrs_pseq_irqs), + .num_regs =3D 3, + .status_base =3D NVVRS_PSEQ_REG_INT_SRC1, + .handle_post_irq =3D nvvrs_pseq_irq_clear, +}; + +static int nvvrs_pseq_vendor_info(struct nvvrs_pseq_chip *chip) +{ + struct i2c_client *client =3D chip->client; + u8 vendor_id, model_rev; + int ret; + + ret =3D i2c_smbus_read_byte_data(client, NVVRS_PSEQ_REG_VENDOR_ID); + if (ret < 0) { + dev_err(chip->dev, "Failed to read Vendor ID: %d\n", ret); + return ret; + } + + vendor_id =3D (u8)ret; + + ret =3D i2c_smbus_read_byte_data(client, NVVRS_PSEQ_REG_MODEL_REV); + if (ret < 0) { + dev_err(chip->dev, "Failed to read Model Rev: %d\n", ret); + return ret; + } + + model_rev =3D (u8)ret; + + if (model_rev < 0x40) { + dev_err(chip->dev, "Chip revision 0x%02x is not supported!\n", + model_rev); + return -ENODEV; + } + + dev_info(chip->dev, "NVVRS Vendor ID: 0x%02x, Model Rev: 0x%02x\n", + vendor_id, model_rev); + + return 0; +} + +static int nvvrs_pseq_probe(struct i2c_client *client) +{ + const struct regmap_config *rmap_config; + struct nvvrs_pseq_chip *nvvrs_chip; + const struct mfd_cell *mfd_cells; + int n_mfd_cells; + int ret; + + nvvrs_chip =3D devm_kzalloc(&client->dev, sizeof(*nvvrs_chip), GFP_KERNEL= ); + if (!nvvrs_chip) + return -ENOMEM; + + /* Set PEC flag for SMBUS transfer with PEC enabled */ + client->flags |=3D I2C_CLIENT_PEC; + + i2c_set_clientdata(client, nvvrs_chip); + nvvrs_chip->client =3D client; + nvvrs_chip->dev =3D &client->dev; + nvvrs_chip->chip_irq =3D client->irq; + mfd_cells =3D nvvrs_pseq_children; + n_mfd_cells =3D ARRAY_SIZE(nvvrs_pseq_children); + rmap_config =3D &nvvrs_pseq_regmap_config; + nvvrs_chip->irq_chip =3D &nvvrs_pseq_irq_chip; + + nvvrs_chip->rmap =3D devm_regmap_init_i2c(client, rmap_config); + if (IS_ERR(nvvrs_chip->rmap)) { + ret =3D PTR_ERR(nvvrs_chip->rmap); + dev_err(nvvrs_chip->dev, "Failed to initialise regmap: %d\n", ret); + return ret; + } + + ret =3D nvvrs_pseq_vendor_info(nvvrs_chip); + if (ret < 0) + return ret; + + nvvrs_chip->irq_drv_data =3D nvvrs_chip; + ret =3D devm_regmap_add_irq_chip(nvvrs_chip->dev, nvvrs_chip->rmap, clien= t->irq, + IRQF_ONESHOT | IRQF_SHARED, 0, + &nvvrs_pseq_irq_chip, + &nvvrs_chip->irq_data); + if (ret < 0) { + dev_err(nvvrs_chip->dev, "Failed to add regmap irq: %d\n", ret); + return ret; + } + + ret =3D devm_mfd_add_devices(nvvrs_chip->dev, PLATFORM_DEVID_NONE, + mfd_cells, n_mfd_cells, NULL, 0, + regmap_irq_get_domain(nvvrs_chip->irq_data)); + if (ret < 0) { + dev_err(nvvrs_chip->dev, "Failed to add MFD children: %d\n", ret); + return ret; + } + + dev_info(nvvrs_chip->dev, "NVVRS PSEQ probe successful"); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int nvvrs_pseq_i2c_suspend(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + + /* + * IRQ must be disabled during suspend because if it happens + * while suspended it will be handled before resuming I2C. + * + * When device is woken up from suspend (e.g. by RTC wake alarm), + * an interrupt occurs before resuming I2C bus controller. + * Interrupt handler tries to read registers but this read + * will fail because I2C is still suspended. + */ + disable_irq(client->irq); + + return 0; +} + +static int nvvrs_pseq_i2c_resume(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + + enable_irq(client->irq); + return 0; +} +#endif + +static const struct dev_pm_ops nvvrs_pseq_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(nvvrs_pseq_i2c_suspend, nvvrs_pseq_i2c_resume) +}; + +static const struct of_device_id nvvrs_dt_match[] =3D { + { .compatible =3D "nvidia,vrs-pseq" }, + {} +}; +MODULE_DEVICE_TABLE(of, nvvrs_dt_match); + +static struct i2c_driver nvvrs_pseq_driver =3D { + .driver =3D { + .name =3D "nvvrs_pseq", + .pm =3D &nvvrs_pseq_pm_ops, + .of_match_table =3D of_match_ptr(nvvrs_dt_match), + }, + .probe =3D nvvrs_pseq_probe, +}; + +module_i2c_driver(nvvrs_pseq_driver); + +MODULE_AUTHOR("Shubhi Garg "); +MODULE_DESCRIPTION("NVIDIA Voltage Regulator Specification Power Sequencer= Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/nvidia-vrs-pseq.h b/include/linux/mfd/nvidia= -vrs-pseq.h new file mode 100644 index 000000000000..7e6f3aa940e7 --- /dev/null +++ b/include/linux/mfd/nvidia-vrs-pseq.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved + +#ifndef _MFD_NVIDIA_VRS_PSEQ_H_ +#define _MFD_NVIDIA_VRS_PSEQ_H_ + +#include + +/* Vendor ID */ +#define NVVRS_PSEQ_REG_VENDOR_ID 0x00 +#define NVVRS_PSEQ_REG_MODEL_REV 0x01 + +/* Interrupts and Status registers */ +#define NVVRS_PSEQ_REG_INT_SRC1 0x10 +#define NVVRS_PSEQ_REG_INT_SRC2 0x11 +#define NVVRS_PSEQ_REG_INT_VENDOR 0x12 +#define NVVRS_PSEQ_REG_CTL_STAT 0x13 +#define NVVRS_PSEQ_REG_EN_STDR1 0x14 +#define NVVRS_PSEQ_REG_EN_STDR2 0x15 +#define NVVRS_PSEQ_REG_EN_STRD1 0x16 +#define NVVRS_PSEQ_REG_EN_STRD2 0x17 +#define NVVRS_PSEQ_REG_WDT_STAT 0x18 +#define NVVRS_PSEQ_REG_TEST_STAT 0x19 +#define NVVRS_PSEQ_REG_LAST_RST 0x1A + +/* Configuration Registers */ +#define NVVRS_PSEQ_REG_EN_ALT_F 0x20 +#define NVVRS_PSEQ_REG_AF_IN_OUT 0x21 +#define NVVRS_PSEQ_REG_EN_CFG1 0x22 +#define NVVRS_PSEQ_REG_EN_CFG2 0x23 +#define NVVRS_PSEQ_REG_CLK_CFG 0x24 +#define NVVRS_PSEQ_REG_GP_OUT 0x25 +#define NVVRS_PSEQ_REG_DEB_IN 0x26 +#define NVVRS_PSEQ_REG_LP_TTSHLD 0x27 +#define NVVRS_PSEQ_REG_CTL_1 0x28 +#define NVVRS_PSEQ_REG_CTL_2 0x29 +#define NVVRS_PSEQ_REG_TEST_CFG 0x2A +#define NVVRS_PSEQ_REG_IEN_VENDOR 0x2B + +/* RTC */ +#define NVVRS_PSEQ_REG_RTC_T3 0x70 +#define NVVRS_PSEQ_REG_RTC_T2 0x71 +#define NVVRS_PSEQ_REG_RTC_T1 0x72 +#define NVVRS_PSEQ_REG_RTC_T0 0x73 +#define NVVRS_PSEQ_REG_RTC_A3 0x74 +#define NVVRS_PSEQ_REG_RTC_A2 0x75 +#define NVVRS_PSEQ_REG_RTC_A1 0x76 +#define NVVRS_PSEQ_REG_RTC_A0 0x77 + +/* WDT */ +#define NVVRS_PSEQ_REG_WDT_CFG 0x80 +#define NVVRS_PSEQ_REG_WDT_CLOSE 0x81 +#define NVVRS_PSEQ_REG_WDT_OPEN 0x82 +#define NVVRS_PSEQ_REG_WDTKEY 0x83 + +/* Interrupt Mask */ +#define NVVRS_PSEQ_INT_SRC1_RSTIRQ_MASK BIT(0) +#define NVVRS_PSEQ_INT_SRC1_OSC_MASK BIT(1) +#define NVVRS_PSEQ_INT_SRC1_EN_MASK BIT(2) +#define NVVRS_PSEQ_INT_SRC1_RTC_MASK BIT(3) +#define NVVRS_PSEQ_INT_SRC1_PEC_MASK BIT(4) +#define NVVRS_PSEQ_INT_SRC1_WDT_MASK BIT(5) +#define NVVRS_PSEQ_INT_SRC1_EM_PD_MASK BIT(6) +#define NVVRS_PSEQ_INT_SRC1_INTERNAL_MASK BIT(7) +#define NVVRS_PSEQ_INT_SRC2_PBSP_MASK BIT(0) +#define NVVRS_PSEQ_INT_SRC2_ECC_DED_MASK BIT(1) +#define NVVRS_PSEQ_INT_SRC2_TSD_MASK BIT(2) +#define NVVRS_PSEQ_INT_SRC2_LDO_MASK BIT(3) +#define NVVRS_PSEQ_INT_SRC2_BIST_MASK BIT(4) +#define NVVRS_PSEQ_INT_SRC2_RT_CRC_MASK BIT(5) +#define NVVRS_PSEQ_INT_SRC2_VENDOR_MASK BIT(7) +#define NVVRS_PSEQ_INT_VENDOR0_MASK BIT(0) +#define NVVRS_PSEQ_INT_VENDOR1_MASK BIT(1) +#define NVVRS_PSEQ_INT_VENDOR2_MASK BIT(2) +#define NVVRS_PSEQ_INT_VENDOR3_MASK BIT(3) +#define NVVRS_PSEQ_INT_VENDOR4_MASK BIT(4) +#define NVVRS_PSEQ_INT_VENDOR5_MASK BIT(5) +#define NVVRS_PSEQ_INT_VENDOR6_MASK BIT(6) +#define NVVRS_PSEQ_INT_VENDOR7_MASK BIT(7) + +/* Controller Register Mask */ +#define NVVRS_PSEQ_REG_CTL_1_FORCE_SHDN (BIT(0) | BIT(1)) +#define NVVRS_PSEQ_REG_CTL_1_FORCE_ACT BIT(2) +#define NVVRS_PSEQ_REG_CTL_1_FORCE_INT BIT(3) +#define NVVRS_PSEQ_REG_CTL_2_EN_PEC BIT(0) +#define NVVRS_PSEQ_REG_CTL_2_REQ_PEC BIT(1) +#define NVVRS_PSEQ_REG_CTL_2_RTC_PU BIT(2) +#define NVVRS_PSEQ_REG_CTL_2_RTC_WAKE BIT(3) +#define NVVRS_PSEQ_REG_CTL_2_RST_DLY 0xF0 + +enum { + NVVRS_PSEQ_INT_SRC1_RSTIRQ, /* Reset or Interrupt Pin Fault */ + NVVRS_PSEQ_INT_SRC1_OSC, /* Crystal Oscillator Fault */ + NVVRS_PSEQ_INT_SRC1_EN, /* Enable Output Pin Fault */ + NVVRS_PSEQ_INT_SRC1_RTC, /* RTC Alarm */ + NVVRS_PSEQ_INT_SRC1_PEC, /* Packet Error Checking */ + NVVRS_PSEQ_INT_SRC1_WDT, /* Watchdog Violation */ + NVVRS_PSEQ_INT_SRC1_EM_PD, /* Emergency Power Down */ + NVVRS_PSEQ_INT_SRC1_INTERNAL, /* Internal Fault*/ + NVVRS_PSEQ_INT_SRC2_PBSP, /* PWR_BTN Short Pulse Detection */ + NVVRS_PSEQ_INT_SRC2_ECC_DED, /* ECC Double-Error Detection */ + NVVRS_PSEQ_INT_SRC2_TSD, /* Thermal Shutdown */ + NVVRS_PSEQ_INT_SRC2_LDO, /* LDO Fault */ + NVVRS_PSEQ_INT_SRC2_BIST, /* Built-In Self Test Fault */ + NVVRS_PSEQ_INT_SRC2_RT_CRC, /* Runtime Register CRC Fault */ + NVVRS_PSEQ_INT_SRC2_VENDOR, /* Vendor Specific Internal Fault */ + NVVRS_PSEQ_INT_VENDOR0, /* Vendor Internal Fault Bit 0 */ + NVVRS_PSEQ_INT_VENDOR1, /* Vendor Internal Fault Bit 1 */ + NVVRS_PSEQ_INT_VENDOR2, /* Vendor Internal Fault Bit 2 */ + NVVRS_PSEQ_INT_VENDOR3, /* Vendor Internal Fault Bit 3 */ + NVVRS_PSEQ_INT_VENDOR4, /* Vendor Internal Fault Bit 4 */ + NVVRS_PSEQ_INT_VENDOR5, /* Vendor Internal Fault Bit 5 */ + NVVRS_PSEQ_INT_VENDOR6, /* Vendor Internal Fault Bit 6 */ + NVVRS_PSEQ_INT_VENDOR7, /* Vendor Internal Fault Bit 7 */ +}; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 12:06:57.1394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5838f0e9-6a9c-4585-8622-08dd7cdf2f82 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFC9877909A Content-Type: text/plain; charset="utf-8" Add support for NVIDIA VRS (Voltage Regulator Specification) Power Sequencer RTC device driver. This RTC can be used to get/set system time, retain system time across boot, wake system from suspend and shutdown state. Signed-off-by: Shubhi Garg --- drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-nvidia-vrs-pseq.c | 559 ++++++++++++++++++++++++++++++ 3 files changed, 570 insertions(+) create mode 100644 drivers/rtc/rtc-nvidia-vrs-pseq.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 838bdc138ffe..3b6dc27a50af 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -406,6 +406,16 @@ config RTC_DRV_MAX77686 This driver can also be built as a module. If so, the module will be called rtc-max77686. =20 +config RTC_DRV_NVVRS_PSEQ + tristate "NVIDIA VRS Power Sequencer RTC device" + depends on MFD_NVVRS_PSEQ + help + If you say yes here you will get support for the battery backed RTC dev= ice + of NVIDIA VRS Power Sequencer. The RTC is connected via I2C interface a= nd + supports alarm functionality. + This driver can also be built as a module. If so, the module will be ca= lled + rtc-nvidia-vrs-pseq. + config RTC_DRV_NCT3018Y tristate "Nuvoton NCT3018Y" depends on OF diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 31473b3276d9..543c5a9fe851 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -119,6 +119,7 @@ obj-$(CONFIG_RTC_DRV_MXC_V2) +=3D rtc-mxc_v2.o obj-$(CONFIG_RTC_DRV_GAMECUBE) +=3D rtc-gamecube.o obj-$(CONFIG_RTC_DRV_NCT3018Y) +=3D rtc-nct3018y.o obj-$(CONFIG_RTC_DRV_NTXEC) +=3D rtc-ntxec.o +obj-$(CONFIG_RTC_DRV_NVVRS_PSEQ)+=3D rtc-nvidia-vrs-pseq.o obj-$(CONFIG_RTC_DRV_OMAP) +=3D rtc-omap.o obj-$(CONFIG_RTC_DRV_OPAL) +=3D rtc-opal.o obj-$(CONFIG_RTC_DRV_OPTEE) +=3D rtc-optee.o diff --git a/drivers/rtc/rtc-nvidia-vrs-pseq.c b/drivers/rtc/rtc-nvidia-vrs= -pseq.c new file mode 100644 index 000000000000..1a4194e4edf4 --- /dev/null +++ b/drivers/rtc/rtc-nvidia-vrs-pseq.c @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + * + * RTC driver for NVIDIA Voltage Regulator Power Sequencer + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ALARM_RESET_VAL 0xFFFFFFFF /* Alarm reset/disable value */ +#define NVVRS_INT_RTC_INDEX 0 /* Only one RTC interrupt register */ +#define REG_LEN_IN_BYTES 4 + +struct nvvrs_rtc_info { + struct device *dev; + struct i2c_client *client; + struct rtc_device *rtc_dev; + struct regmap *regmap; + struct regmap_irq_chip_data *rtc_irq_data; + /* Mutex to protect RTC operations */ + struct mutex lock; + unsigned int rtc_irq; + /* Registers offset to I2C addresses map */ + const u8 *map; + /* RTC IRQ CHIP */ + const struct regmap_irq_chip *rtc_irq_chip; +}; + +/* RTC Registers offsets */ +enum nvvrs_rtc_reg_offset { + RTC_T3 =3D 0, + RTC_T2, + RTC_T1, + RTC_T0, + RTC_A3, + RTC_A2, + RTC_A1, + RTC_A0, + CTL1_REG, + CTL2_REG, + RTC_END, +}; + +static const struct regmap_irq nvvrs_rtc_irq[] =3D { + REGMAP_IRQ_REG(NVVRS_INT_RTC_INDEX, 0, NVVRS_PSEQ_INT_SRC1_RTC_MASK), +}; + +static const struct regmap_irq_chip nvvrs_rtc_irq_chip =3D { + .name =3D "nvvrs-rtc", + .status_base =3D NVVRS_PSEQ_REG_INT_SRC1, + .num_regs =3D 1, + .irqs =3D nvvrs_rtc_irq, + .num_irqs =3D ARRAY_SIZE(nvvrs_rtc_irq), +}; + +static const u8 rtc_map[RTC_END] =3D { + [RTC_T3] =3D NVVRS_PSEQ_REG_RTC_T3, + [RTC_T2] =3D NVVRS_PSEQ_REG_RTC_T2, + [RTC_T1] =3D NVVRS_PSEQ_REG_RTC_T1, + [RTC_T0] =3D NVVRS_PSEQ_REG_RTC_T0, + [RTC_A3] =3D NVVRS_PSEQ_REG_RTC_A3, + [RTC_A2] =3D NVVRS_PSEQ_REG_RTC_A2, + [RTC_A1] =3D NVVRS_PSEQ_REG_RTC_A1, + [RTC_A0] =3D NVVRS_PSEQ_REG_RTC_A0, + [CTL1_REG] =3D NVVRS_PSEQ_REG_CTL_1, + [CTL2_REG] =3D NVVRS_PSEQ_REG_CTL_2, +}; + +static int nvvrs_update_bits(struct nvvrs_rtc_info *info, u8 reg, + u8 mask, u8 value) +{ + int ret; + u8 val; + + ret =3D i2c_smbus_read_byte_data(info->client, reg); + if (ret < 0) { + dev_err(info->dev, "Failed to read reg:0x%02x ret:(%d)\n", + reg, ret); + return ret; + } + val =3D (u8)ret; + val &=3D ~mask; + val |=3D (value & mask); + + ret =3D i2c_smbus_write_byte_data(info->client, reg, val); + if (ret < 0) + dev_err(info->dev, "Failed to write reg:0x%02x val:0x%02x ret:(%d)\n", + reg, val, ret); + + return ret; +} + +static int nvvrs_rtc_update_alarm_reg(struct i2c_client *client, + struct nvvrs_rtc_info *info, u8 *time) +{ + int ret; + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_A3], time[3]); + if (ret < 0) { + dev_err(info->dev, "Failed to write alarm reg: 0x%02x ret:(%d)\n", + info->map[RTC_A3], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_A2], time[2]); + if (ret < 0) { + dev_err(info->dev, "Failed to write alarm reg: 0x%02x ret:(%d)\n", + info->map[RTC_A2], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_A1], time[1]); + if (ret < 0) { + dev_err(info->dev, "Failed to write alarm reg: 0x%02x ret:(%d)\n", + info->map[RTC_A1], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_A0], time[0]); + if (ret < 0) { + dev_err(info->dev, "Failed to write alarm reg: 0x%02x ret:(%d)\n", + info->map[RTC_A0], ret); + goto out; + } + +out: + return ret; +} + +static int nvvrs_rtc_enable_alarm(struct nvvrs_rtc_info *info) +{ + int ret; + + /* Set RTC_WAKE bit for autonomous wake from sleep */ + ret =3D nvvrs_update_bits(info, info->map[CTL2_REG], + NVVRS_PSEQ_REG_CTL_2_RTC_WAKE, + NVVRS_PSEQ_REG_CTL_2_RTC_WAKE); + if (ret < 0) { + dev_err(info->dev, "Failed to set RTC_WAKE bit (%d)\n", ret); + return ret; + } + + /* Set RTC_PU bit for autonomous wake from shutdown */ + ret =3D nvvrs_update_bits(info, info->map[CTL2_REG], + NVVRS_PSEQ_REG_CTL_2_RTC_PU, + NVVRS_PSEQ_REG_CTL_2_RTC_PU); + if (ret < 0) { + dev_err(info->dev, "Failed to set RTC_PU bit (%d)\n", ret); + return ret; + } + + return ret; +} + +static int nvvrs_rtc_disable_alarm(struct nvvrs_rtc_info *info) +{ + struct i2c_client *client =3D info->client; + u8 val[REG_LEN_IN_BYTES]; + int ret; + + /* Clear RTC_WAKE bit */ + ret =3D nvvrs_update_bits(info, info->map[CTL2_REG], + NVVRS_PSEQ_REG_CTL_2_RTC_WAKE, 0); + if (ret < 0) { + dev_err(info->dev, "Failed to clear RTC_WAKE bit (%d)\n", ret); + goto out; + } + + /* Clear RTC_PU bit */ + ret =3D nvvrs_update_bits(info, info->map[CTL2_REG], + NVVRS_PSEQ_REG_CTL_2_RTC_PU, 0); + if (ret < 0) { + dev_err(info->dev, "Failed to clear RTC_PU bit (%d)\n", ret); + goto out; + } + + /* Write ALARM_RESET_VAL in RTC Alarm register to disable alarm */ + val[0] =3D 0xff; + val[1] =3D 0xff; + val[2] =3D 0xff; + val[3] =3D 0xff; + + ret =3D nvvrs_rtc_update_alarm_reg(client, info, val); + if (ret < 0) { + dev_err(info->dev, "Failed to disable Alarm (%d)\n", ret); + goto out; + } +out: + return ret; +} + +static irqreturn_t nvvrs_rtc_irq_handler(int irq, void *data) +{ + struct nvvrs_rtc_info *info =3D data; + + dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq); + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +static int nvvrs_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + struct i2c_client *client =3D info->client; + time64_t secs =3D 0; + int ret; + u8 val; + + mutex_lock(&info->lock); + + /* Multi-byte transfers are not supported with PEC enabled */ + /* Read MSB first to avoid coherency issues */ + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_T3]); + if (ret < 0) { + dev_err(info->dev, "Failed to read time reg:0x%02x ret:(%d)\n", + info->map[RTC_T3], ret); + goto out; + } + val =3D (u8)ret; + secs |=3D (time64_t)val << 24; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_T2]); + if (ret < 0) { + dev_err(info->dev, "Failed to read time reg:0x%02x ret:(%d)\n", + info->map[RTC_T2], ret); + goto out; + } + val =3D (u8)ret; + secs |=3D (time64_t)val << 16; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_T1]); + if (ret < 0) { + dev_err(info->dev, "Failed to read time reg:0x%02x ret:(%d)\n", + info->map[RTC_T1], ret); + goto out; + } + val =3D (u8)ret; + secs |=3D (time64_t)val << 8; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_T0]); + if (ret < 0) { + dev_err(info->dev, "Failed to read time reg:0x%02x ret:(%d)\n", + info->map[RTC_T0], ret); + goto out; + } + val =3D (u8)ret; + secs |=3D val; + + rtc_time64_to_tm(secs, tm); +out: + mutex_unlock(&info->lock); + return ret; +} + +static int nvvrs_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + struct i2c_client *client =3D info->client; + u8 time[REG_LEN_IN_BYTES]; + time64_t secs; + int ret; + + mutex_lock(&info->lock); + + secs =3D rtc_tm_to_time64(tm); + time[0] =3D secs & 0xff; + time[1] =3D (secs >> 8) & 0xff; + time[2] =3D (secs >> 16) & 0xff; + time[3] =3D (secs >> 24) & 0xff; + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_T3], time[3]); + if (ret < 0) { + dev_err(info->dev, "Failed to write time reg: 0x%02x ret:(%d)\n", + info->map[RTC_T3], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_T2], time[2]); + if (ret < 0) { + dev_err(info->dev, "Failed to write time reg: 0x%02x ret:(%d)\n", + info->map[RTC_T2], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_T1], time[1]); + if (ret < 0) { + dev_err(info->dev, "Failed to write time reg: 0x%02x ret:(%d)\n", + info->map[RTC_T1], ret); + goto out; + } + + ret =3D i2c_smbus_write_byte_data(client, info->map[RTC_T0], time[0]); + if (ret < 0) { + dev_err(info->dev, "Failed to write time reg: 0x%02x ret:(%d)\n", + info->map[RTC_T0], ret); + goto out; + } + +out: + mutex_unlock(&info->lock); + return ret; +} + +static int nvvrs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alr= m) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + struct i2c_client *client =3D info->client; + time64_t alarm_val =3D 0; + int ret; + u8 val; + + mutex_lock(&info->lock); + + /* Multi-byte transfers are not supported with PEC enabled */ + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_A3]); + if (ret < 0) { + dev_err(info->dev, "Failed to read alarm reg:0x%02x ret:(%d)\n", + info->map[RTC_A3], ret); + goto out; + } + val =3D (u8)ret; + alarm_val |=3D (time64_t)val << 24; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_A2]); + if (ret < 0) { + dev_err(info->dev, "Failed to read alarm reg:0x%02x ret:(%d)\n", + info->map[RTC_A2], ret); + goto out; + } + val =3D (u8)ret; + alarm_val |=3D (time64_t)val << 16; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_A1]); + if (ret < 0) { + dev_err(info->dev, "Failed to read alarm reg:0x%02x ret:(%d)\n", + info->map[RTC_A1], ret); + goto out; + } + val =3D (u8)ret; + alarm_val |=3D (time64_t)val << 8; + + ret =3D i2c_smbus_read_byte_data(client, info->map[RTC_A0]); + if (ret < 0) { + dev_err(info->dev, "Failed to read alarm reg:0x%02x ret:(%d)\n", + info->map[RTC_A0], ret); + goto out; + } + val =3D (u8)ret; + alarm_val |=3D val; + + if (alarm_val =3D=3D ALARM_RESET_VAL) + alrm->enabled =3D 0; + else + alrm->enabled =3D 1; + + rtc_time64_to_tm(alarm_val, &alrm->time); +out: + mutex_unlock(&info->lock); + return ret; +} + +static int nvvrs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + struct i2c_client *client =3D info->client; + u8 time[REG_LEN_IN_BYTES]; + time64_t secs; + int ret; + + mutex_lock(&info->lock); + + ret =3D nvvrs_rtc_enable_alarm(info); + if (ret < 0) { + dev_err(info->dev, "Failed to enable alarm! (%d)\n", ret); + goto out; + } + + secs =3D rtc_tm_to_time64(&alrm->time); + time[0] =3D secs & 0xff; + time[1] =3D (secs >> 8) & 0xff; + time[2] =3D (secs >> 16) & 0xff; + time[3] =3D (secs >> 24) & 0xff; + + ret =3D nvvrs_rtc_update_alarm_reg(client, info, time); + + alrm->enabled =3D 1; +out: + mutex_unlock(&info->lock); + return ret; +} + +static int nvvrs_rtc_alarm_irq_enable(struct device *dev, unsigned int ena= bled) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + int ret =3D 0; + + mutex_lock(&info->lock); + if (enabled) + ret =3D nvvrs_rtc_enable_alarm(info); + else + ret =3D nvvrs_rtc_disable_alarm(info); + + mutex_unlock(&info->lock); + return ret; +} + +static const struct rtc_class_ops nvvrs_rtc_ops =3D { + .read_time =3D nvvrs_rtc_read_time, + .set_time =3D nvvrs_rtc_set_time, + .read_alarm =3D nvvrs_rtc_read_alarm, + .set_alarm =3D nvvrs_rtc_set_alarm, + .alarm_irq_enable =3D nvvrs_rtc_alarm_irq_enable, +}; + +static int nvvrs_rtc_probe(struct platform_device *pdev) +{ + struct nvvrs_rtc_info *info; + struct device *parent; + struct i2c_client *client; + int ret; + + info =3D devm_kzalloc(&pdev->dev, sizeof(struct nvvrs_rtc_info), GFP_KERN= EL); + if (!info) + return -ENOMEM; + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to get irq\n"); + return ret; + } + info->rtc_irq =3D ret; + + mutex_init(&info->lock); + info->dev =3D &pdev->dev; + parent =3D info->dev->parent; + client =3D to_i2c_client(parent); + client->flags |=3D I2C_CLIENT_PEC; + i2c_set_clientdata(client, info); + info->client =3D client; + info->map =3D rtc_map; + info->rtc_irq_chip =3D &nvvrs_rtc_irq_chip; + platform_set_drvdata(pdev, info); + + /* Initialize regmap */ + info->regmap =3D dev_get_regmap(parent, NULL); + if (!info->regmap) { + dev_err(info->dev, "Failed to get RTC regmap\n"); + return -ENODEV; + } + + /* RTC as a wakeup source */ + device_init_wakeup(info->dev, 1); + + /* Register RTC device */ + info->rtc_dev =3D devm_rtc_device_register(info->dev, "nvvrs-rtc", + &nvvrs_rtc_ops, THIS_MODULE); + + if (IS_ERR(info->rtc_dev)) { + ret =3D PTR_ERR(info->rtc_dev); + dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); + return ret; + } + + ret =3D request_threaded_irq(info->rtc_irq, NULL, nvvrs_rtc_irq_handler, = 0, + "rtc-alarm", info); + if (ret < 0) + dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", + info->rtc_irq, ret); + + return ret; +} + +static void nvvrs_rtc_remove(struct platform_device *pdev) +{ + struct nvvrs_rtc_info *info =3D platform_get_drvdata(pdev); + + free_irq(info->rtc_irq, info); +} + +#ifdef CONFIG_PM_SLEEP +static int nvvrs_rtc_suspend(struct device *dev) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + int ret =3D 0; + + if (device_may_wakeup(dev)) { + /* Set RTC_WAKE bit for auto wake system from suspend state */ + ret =3D nvvrs_update_bits(info, info->map[CTL2_REG], + NVVRS_PSEQ_REG_CTL_2_RTC_WAKE, + NVVRS_PSEQ_REG_CTL_2_RTC_WAKE); + if (ret < 0) { + dev_err(info->dev, "Failed to set RTC_WAKE bit (%d)\n", ret); + return ret; + } + + ret =3D enable_irq_wake(info->rtc_irq); + } + + return ret; +} + +static int nvvrs_rtc_resume(struct device *dev) +{ + struct nvvrs_rtc_info *info =3D dev_get_drvdata(dev); + int ret; + + if (device_may_wakeup(dev)) { + /* Clear FORCE_ACT bit */ + ret =3D nvvrs_update_bits(info, info->map[CTL1_REG], + NVVRS_PSEQ_REG_CTL_1_FORCE_ACT, 0); + if (ret < 0) { + dev_err(info->dev, "Failed to clear FORCE_ACT bit (%d)\n", ret); + return ret; + } + + return disable_irq_wake(info->rtc_irq); + } + + return 0; +} + +#endif +static SIMPLE_DEV_PM_OPS(nvvrs_rtc_pm_ops, nvvrs_rtc_suspend, nvvrs_rtc_re= sume); + +static const struct platform_device_id nvvrs_rtc_id[] =3D { + { "nvvrs-pseq-rtc", }, + { }, +}; +MODULE_DEVICE_TABLE(platform, nvvrs_rtc_id); + +static struct platform_driver nvvrs_rtc_driver =3D { + .driver =3D { + .name =3D "nvvrs-pseq-rtc", + .pm =3D &nvvrs_rtc_pm_ops, + }, + .probe =3D nvvrs_rtc_probe, + .remove =3D nvvrs_rtc_remove, + .id_table =3D nvvrs_rtc_id, +}; + +module_platform_driver(nvvrs_rtc_driver); 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Wed, 16 Apr 2025 05:06:39 -0700 From: Shubhi Garg To: , , , , , , CC: Subject: [PATCH 5/5] arm64: defconfig: enable NVIDIA VRS PSEQ Date: Wed, 16 Apr 2025 12:06:19 +0000 Message-ID: <20250416120619.483793-6-shgarg@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250416120619.483793-1-shgarg@nvidia.com> References: <20250416120619.483793-1-shgarg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|SJ0PR12MB6880:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e726afd-42b1-4ae1-1244-08dd7cdf339a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DTCS3qAnkRXy7+VxNHiOxhhIifk4Kg3nc+ZeZ3aL8db2n8AC/qLE8Gb1tbMR?= =?us-ascii?Q?Qc+/pKE2sZe+YhQPHqtqJRa1Dyt5+FaGvHvsvUebv7Qnw0DW3kd0JnzWsNpu?= =?us-ascii?Q?3m3JgBerbmc3HtUDtVWxvYdulGuE7GYEfyNkGcZN02ijuUHs8mDcsHLkV60U?= =?us-ascii?Q?e5IptgjWekJL5+GRKRrzV41ZhPMxhs4wCcjwit537EbvtpMIbYrKMVO9qnU0?= =?us-ascii?Q?1eJjiXdZCb6l4nyPTrDKGv0jHDpy18u+QFevcftoEcxY9tqIE1rMfuAKnoAx?= =?us-ascii?Q?GDoZilrmFUo3j7Zt5VO+rXqs+aKD6eG3MjNjBnKVHR4IKgEcKOoapAmXyPHN?= =?us-ascii?Q?BmiodGu+FMz5jknPVh/nCuEDpii06B0TlyA8gv3Y8dHsSbuElTH1LaKBOD9e?= =?us-ascii?Q?4w+dKhKu6LymjQLuf6TxDQDXQ5wi7d5qtI32x6YQRTzaxBMiqN4AsCDajdyc?= =?us-ascii?Q?Wd6PRj/tIxUeydsq7eFplsFnjeOHj0Vr1lp9R/D5CEHXWmrGs/LoZ/DjUsIB?= =?us-ascii?Q?I0ESAoup8ueaD3/QZ6ZDLzBLpZjKk0JTRezmlpynz2MtFG+2Ylcyr4ILg7Yb?= =?us-ascii?Q?J0u1MOpvvrdBlmj38GKlrxVwPCz8u+2lSI6mdMDhptkJ7k8PDpwsThfgqvQN?= =?us-ascii?Q?urJkLA2V98GtrBnA8io2b71YS+zUv+mX+kQVmtm9C08mIayaM3P7VvVf7iZ7?= =?us-ascii?Q?YqrsI/+Bx4E+dthWq4Dy6DfNKpdb6m4IpPsJWtkdCoY58eXIKRbLix646s7X?= =?us-ascii?Q?aAXYvBlDCGpZi8Nr8wU/G5YU7wc5cyRXd5NrxG5n+viFcWZDWtMI1X645bZX?= =?us-ascii?Q?8zWVJ4g6kqdh+Ga/TX35b0Kitu/+P7fxfXlhWp/MEG/+5XfzvBN1X9z6FYLI?= =?us-ascii?Q?ncDC2/gp51Y2oPgXcqH3AP9WAlhylqkYPH5/4z3ShgUik+UIagdirxgIJ5J+?= =?us-ascii?Q?ovpN3FTef3DVusRL+mF0JrjmAln0AcSGwKKhHk5TCkb/4oieHonpRwZHVHTr?= =?us-ascii?Q?f8LFIAoeABaIY7n9WzyHhwNHMg6vguqF9nwHgUcz7t/kHlQCoqvV3AgnI4Sp?= =?us-ascii?Q?VJEXTTcd6qZFTYpvt5rVOoAJDBV+NHLx1oIEgPG3mbPWxqDkBmotFOqsdu0l?= =?us-ascii?Q?Lx6uaTKNao+2VuuAbmSnO7ANb87h7qzixd4B2RJdRbFFSnpml4r0uGSpAqb6?= =?us-ascii?Q?OO6HklpsiqNvb7iFJlk/e5rne0KJP02buL4akpW7EiUVhuDDd15Z6RvD+b0B?= =?us-ascii?Q?LUWa5TepF6yVRhvGap6WyNQuI20p4Kp8pO8g6FTFsvDUetD4/30Ax8vuK8EU?= =?us-ascii?Q?IER+23jv7Nrnce7P8Virpg8vnqSlKTvuaFIkYckuoN48Gjd1GmKx0S8Iz33a?= =?us-ascii?Q?gDQOzQ+ddlLEtSuP7DJr3rLlTuOuVOYAXuEPtRLoNDAq4SLIE5m5tbQC07k+?= =?us-ascii?Q?lbCdhu63q0Nt835jEyE3gmzfy+E378NlZKfbTXKNPbOB43tMw1AJvOahbzJl?= =?us-ascii?Q?84P8RJuL36/qF6A+WxTmwJN7KU5P7/rlUIlo?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 12:07:03.9733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e726afd-42b1-4ae1-1244-08dd7cdf339a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6880 Content-Type: text/plain; charset="utf-8" Enable NVIDIA VRS (Voltage Regulator Specification) power sequencer device modules. NVIDIA VRS PSEQ controls ON/OFF and suspend/resume power sequencing of system power rails on Tegra234 SoC. This device also provides 32kHz RTC support with backup battery for system timing. Signed-off-by: Shubhi Garg --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c85e5da152f..9c6cba664a43 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -780,6 +780,8 @@ CONFIG_MFD_TPS6594_I2C=3Dm CONFIG_MFD_ROHM_BD718XX=3Dy CONFIG_MFD_WCD934X=3Dm CONFIG_MFD_KHADAS_MCU=3Dm +CONFIG_MFD_NVVRS_PSEQ=3Dm +CONFIG_RTC_DRV_NVVRS_PSEQ=3Dm CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy CONFIG_REGULATOR_AXP20X=3Dy CONFIG_REGULATOR_BD718XX=3Dy --=20 2.25.1