From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E5E1176ADB for ; Wed, 16 Apr 2025 02:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769848; cv=none; b=n1+SSKCz2qI6fSZ8Pe4DoMlgTKoJcbejfGY2zRhqFSvFuFBg7EtjtOf49iQQuJjuFfSceOTf19uB9vfwbuy8T65dUWrXwRrD3BVL4AGYqKzGiXq3ffEtWrKBHZiSePQEWE/zpnn4ELOBM3shTWb+wHaS7DLI1ovMwnGjVuaq45M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769848; c=relaxed/simple; bh=nV/OqN0un+Vool+cdkjFxTTv90dhqfXW6E22DcGvy5I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vAbsSIW/y306k9bivJJYdsuLVhl33mbXs6W5NvQyPR110LY2zkslJ5frqmSEbLEht+UCgCiAuWzRnxUrbwNYF40OtAMrrYw/nUn6THgKtFpjqadliEiyNrmNgGD2cHBKbeZR9lUKyx7XoN8ntUOuvC+ZU0O2WOahX5VhDWXHPs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bpV6O0lp; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bpV6O0lp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769847; x=1776305847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nV/OqN0un+Vool+cdkjFxTTv90dhqfXW6E22DcGvy5I=; b=bpV6O0lpHIv/aIPXosFc9SHq39egAbt6HWyq7ygPId/ftA2Ek1PpEGV5 wJgE4SEhDy9NcZnxYtNxCR0h4gmFYuyVZr3iuIYFKd60iw3bBwKJKoPCq 1IjQ/F5vl2UtH1GF279SE84VXplg71Kmj6l7Bv1nDhbmbiGE3wG+BBVdv vQ8OgBUn95NT2zmnwdeujWTjcUZ5kvcAKw2mGxZopDIhUhp+ZX+KY4OiX rl5Z4Gwazrh+K5UIS8/6fYCzXUZgsGomLjKVXtu2aOky+EpgsLIeJyqDT zM4RQZRHhou8kdQ9TWuItbLrIBDuuzWXLt0qjWJY9FCN8F/IFhcljsAp2 g==; X-CSE-ConnectionGUID: vNjYyg0YTm+kYQhlIWt64g== X-CSE-MsgGUID: Jt+NZry1RXabtBfDPVDGmQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998144" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998144" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:27 -0700 X-CSE-ConnectionGUID: hbGvIGAtSxuF7VjWdOOWXA== X-CSE-MsgGUID: pSVkcqJkQcewwXIqt5PGfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260395" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:27 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Sohil Mehta Subject: [PATCH 01/10] x86/cpufeatures: Add X86_FEATURE_APX Date: Tue, 15 Apr 2025 19:16:51 -0700 Message-ID: <20250416021720.12305-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Advanced Performance Extensions (APX) introduce a new set of general-purpose registers, managed as an extended state component via the xstate management facility. Before enabling this new xstate, define a feature flag to clarify the dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level 7 with EDX=3D1. Since this CPUID leaf is not yet allocated, place the flag in a scattered feature word. While this feature is intended only for userspace, exposing it via /proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2) mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the feature availability. Finally, clarify that APX depends on XSAVE. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- Changes from the last posting: https://lore.kernel.org/lkml/20250320234301.8342-6-chang.seok.bae@intel.com/ * Rebase onto v6.15-rc1; resolve conflict with commit: 968e9bc4cef8 ("x86: move ZMM exclusion list into CPU feature flag") * Organize APX entries orderly (Sohil). Then, include his review tag --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6c2c152d8a67..eb73f3f0ec70 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -481,6 +481,7 @@ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ #define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to = downclocking */ +#define X86_FEATURE_APX (21*32 + 9) /* Advanced Performance Extensions */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index a2fbea0be535..72f4fb66ac20 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -28,6 +28,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_PKU, X86_FEATURE_XSAVE }, { X86_FEATURE_MPX, X86_FEATURE_XSAVE }, { X86_FEATURE_XGETBV1, X86_FEATURE_XSAVE }, + { X86_FEATURE_APX, X86_FEATURE_XSAVE }, { X86_FEATURE_CMOV, X86_FEATURE_FXSR }, { X86_FEATURE_MMX, X86_FEATURE_FXSR }, { X86_FEATURE_MMXEXT, X86_FEATURE_MMX }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..ffb80b5ad97f 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, + { X86_FEATURE_APX, CPUID_EDX, 21, 0x00000007, 1 }, { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 }, { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06A332139B1 for ; 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a="48998152" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998152" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:29 -0700 X-CSE-ConnectionGUID: kZI5kAEiQTiHSSW3pQkU9Q== X-CSE-MsgGUID: 0on8AxneT1ufiz5RpXls2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260404" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:29 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Sohil Mehta Subject: [PATCH 02/10] x86/fpu/apx: Define APX state component Date: Tue, 15 Apr 2025 19:16:52 -0700 Message-ID: <20250416021720.12305-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Advanced Performance Extensions (APX) is associated with a new state component number 19. To support saving and restoring of the corresponding registers via the XSAVE mechanism, introduce the component definition along with the necessary sanity checks. Define the new component number, state name, and those register data type. Then, extend the size checker to validate the register data type and explicitly list the APX feature flag as a dependency for the new component in xsave_cpuid_features[]. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- Changes from the last posting: https://lore.kernel.org/lkml/20250320234301.8342-7-chang.seok.bae@intel.com/ * Move the check to be grouped with other XCHECK_SZ() entries (Sohil) * Massage the changelog (Sohil) * Add Sohil's tag --- arch/x86/include/asm/fpu/types.h | 9 +++++++++ arch/x86/kernel/fpu/xstate.c | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index de16862bf230..97310df3ea13 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -125,6 +125,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILE_CFG, XFEATURE_XTILE_DATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; @@ -145,6 +146,7 @@ enum xfeature { #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG) #define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA) +#define XFEATURE_MASK_APX (1 << XFEATURE_APX) =20 #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \ @@ -303,6 +305,13 @@ struct xtile_data { struct reg_1024_byte tmm; } __packed; =20 +/* + * State component 19: 8B extended general purpose register. + */ +struct apx_state { + u64 egpr[16]; +} __packed; + /* * State component 10 is supervisor state used for context-switching the * PASID state. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index a288597065fd..dfd07af10037 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -63,6 +63,7 @@ static const char *xfeature_names[] =3D "unknown xstate feature", "AMX Tile config", "AMX Tile data", + "APX registers", "unknown xstate feature", }; =20 @@ -81,6 +82,7 @@ static unsigned short xsave_cpuid_features[] __initdata = =3D { [XFEATURE_CET_USER] =3D X86_FEATURE_SHSTK, [XFEATURE_XTILE_CFG] =3D X86_FEATURE_AMX_TILE, [XFEATURE_XTILE_DATA] =3D X86_FEATURE_AMX_TILE, + [XFEATURE_APX] =3D X86_FEATURE_APX, }; =20 static unsigned int xstate_offsets[XFEATURE_MAX] __ro_after_init =3D @@ -569,6 +571,7 @@ static bool __init check_xstate_against_struct(int nr) case XFEATURE_PASID: return XCHECK_SZ(sz, nr, struct ia32_pasid_state); case XFEATURE_XTILE_CFG: return XCHECK_SZ(sz, nr, struct xtile_cfg); case XFEATURE_CET_USER: return XCHECK_SZ(sz, nr, struct cet_user_state); + case XFEATURE_APX: return XCHECK_SZ(sz, nr, struct apx_state); case XFEATURE_XTILE_DATA: check_xtile_data_against_struct(sz); return tru= e; default: XSTATE_WARN_ON(1, "No structure for xstate: %d\n", nr); --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACCB3227E8A for ; Wed, 16 Apr 2025 02:17:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769853; cv=none; b=rJ+xgqOdY+NLVb4fnJog4ukLoBzrQRBs8dXi6qYZghEpWVD4b0eAB7UYPIGqKJbjF+C7k5KTSj6wTW30nQN+ak9AD1Q6vvFlskKC8GbEqtCl5gwQSbBAjuu2NNvDj+PPm0NBYvUamjhMcyGQcO2h0ZdNcQ5DbgZu/S11wyoF3LU= ARC-Message-Signature: i=1; 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d="scan'208";a="130260410" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:31 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Sohil Mehta Subject: [PATCH 03/10] x86/fpu/apx: Disallow conflicting MPX presence Date: Tue, 15 Apr 2025 19:16:53 -0700 Message-ID: <20250416021720.12305-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable XSTATE components are architecturally independent. There is no rule requiring their offsets in the non-compacted format to be strictly ascending or mutually non-overlapping. However, in practice, such overlaps have not occurred -- until now. APX is introduced as xstate component 19, following AMX. In the non-compacted XSAVE format, its offset overlaps with the space previously occupied by the now-deprecated MPX feature: 45fc24e89b7c ("x86/mpx: remove MPX from arch/x86") To prevent conflicts, the kernel must ensure the CPU never expose both features at the same time. If so, it indicates unreliable hardware. In such cases, XSAVE should be disabled entirely as a precautionary measure. Add a sanity check to detect this condition and disable XSAVE if an invalid hardware configuration is identified. Note: MPX state components remain enabled on legacy systems solely for KVM guest support. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- Changes from the last posting: https://lore.kernel.org/lkml/20250320234301.8342-8-chang.seok.bae@intel.com/ * Add background in the changelog (Sohil/Dave) * Clarify XSAVE disablement (Sohil). * Collect review tag The related warning message will be moved to the XSAVE-disabling function in patch 6, per Dave=E2=80=99s suggestion. --- arch/x86/kernel/fpu/xstate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index dfd07af10037..14f5c1bb2080 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -814,6 +814,17 @@ void __init fpu__init_system_xstate(unsigned int legac= y_size) goto out_disable; } =20 + if (fpu_kernel_cfg.max_features & XFEATURE_MASK_APX && + fpu_kernel_cfg.max_features & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_= BNDCSR)) { + /* + * This is a problematic CPU configuration where two + * conflicting state components are both enumerated. + */ + pr_err("x86/fpu: Both APX/MPX present in the CPU's xstate features: 0x%l= lx, disabling XSAVE.\n", + fpu_kernel_cfg.max_features); + goto out_disable; + } + fpu_kernel_cfg.independent_features =3D fpu_kernel_cfg.max_features & XFEATURE_MASK_INDEPENDENT; =20 --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2F272288FE for ; Wed, 16 Apr 2025 02:17:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769856; cv=none; b=HkY7824lFPXhKDyU1I60Ayp7JaBP+/PDIXLKBwX3kuljlcOHbIzbcCrOWPsTIKrq+aRk4H9ii43B0aYFgzZFctgpG0izcSHt59OshN7w82sRIjm5doiVAE7w3WTPv8XXGikdBWbmwNzwUAqEbxVo/yCgeA+5xQYlK04u70g6XSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769856; c=relaxed/simple; bh=On84tfyqcGMRbTcYvCw2fn0MGiUEhtXhyKLIokAHRcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jvjJOQRhzDvib4aj3LYEZ9jF+WUre/sRRe/A2CmHtNLlLGvrA3nKkMZBRMpd3pwAt97cqpnyYjVMlCmB3kFlV3P/CfzlmBgnOoACIB/ulNtI9U8oLqM9d9ycMiOAnOP8u2NPiLPlO77BX14Lsv56UpsNDQINicLnwskrcicA0Gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E8qMqx5z; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E8qMqx5z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769855; x=1776305855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=On84tfyqcGMRbTcYvCw2fn0MGiUEhtXhyKLIokAHRcA=; b=E8qMqx5zctDmNY9PgRcX8KfAR4h3SECyBgTwRq7NSrZRObvMiZAC07Ni B18cWRS73p8cmf5RXWJHri6MWhBEe6aTFXSlS6M71qDnv0RRroh8LueYr wu0MWOkMS/aeHr4xmhIWJCMg0moaHcbDBJ+SuBau62rJsVjAam9jM5BSy +59OVdOabEfOA4rPgxC/444xvTkJYMmdsVVfke/PraE2MQh9QSQq5tCSs 5le5m77sLocWBCkD8H6W02Zqu5Ff3xMwj9x2Us2CT3DgwDVAyjyPRzCiR NtF+Jv9DIFeh2D4XLnYwUmxsbb6Um9h9J3PLUn5UT7eqEItppx4sKTu4d g==; X-CSE-ConnectionGUID: SRfMvZfaRKSncYsbm1P8lw== X-CSE-MsgGUID: EJIpUd3mS9K2i8/ZAeKDHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998164" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998164" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:34 -0700 X-CSE-ConnectionGUID: qDy9A4tJTACkp35mwEyWCQ== X-CSE-MsgGUID: 35t2Z186QzqogGrKpMTn7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260442" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:34 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Sohil Mehta Subject: [PATCH 04/10] x86/fpu/apx: Enable APX state support Date: Tue, 15 Apr 2025 19:16:54 -0700 Message-ID: <20250416021720.12305-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With securing APX against conflicting MPX, it is now ready to be enabled. Include APX in the enabled xfeature set. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- Changes from the last posting: https://lore.kernel.org/lkml/20250320234301.8342-9-chang.seok.bae@intel.com/ * Include review tag --- arch/x86/include/asm/fpu/xstate.h | 3 ++- arch/x86/kernel/fpu/xstate.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index 7f39fe7980c5..b308a76afbb7 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -32,7 +32,8 @@ XFEATURE_MASK_PKRU | \ XFEATURE_MASK_BNDREGS | \ XFEATURE_MASK_BNDCSR | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * Features which are restored when returning to user space. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 14f5c1bb2080..2ac1fc182273 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -371,7 +371,8 @@ static __init void os_xrstor_booting(struct xregs_state= *xstate) XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_PASID | \ XFEATURE_MASK_CET_USER | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * setup the xstate image representing the init state --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B053227E8A for ; Wed, 16 Apr 2025 02:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769858; cv=none; b=CUOkUGtWOaf81PT0aZK8Y0tTcZ7rEVyrjP8PwY/G12jUW/syuhlA/HzozpfogIELFO5yivJpH84N1Rjj3Y9gSNKWzEe5C/27QHoWPdY5bezK64CA1PikRrN4ZVGwE51RyfJM5RWzA19Kog4mteZxTZG0Hp27Uu8ayFkhgo2pA0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769858; c=relaxed/simple; bh=ScAZXyKuUgPSJ0stUQtkTYeOuDfusDGAaF+sfu5F3Hg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=loDHXTZ+Dc5zhtVjfhM15PtJlDFb+8tICrf3Fitb0HbQghHLgk+RBvVvUwWfflk7FWUjH18MtOIIheJLrv4AdfUSHCqQqeJwayL5KDt723s8ch/UidkwO5HAEIzODHjeZWXgmj+cRmoYquqSeac0AfzjZXm1GN/Z3Syb/fHs3b0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=e59OOKxS; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e59OOKxS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769856; x=1776305856; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ScAZXyKuUgPSJ0stUQtkTYeOuDfusDGAaF+sfu5F3Hg=; b=e59OOKxSK21fLOwurBJzCCyZ00i9d200KazvO4YP0d3dAgkg0zYP1SDp xeZRg6A2/ha2oZjktHZKyuVb3sIVhmM53vOEtRXThRCclIIbmbc7S6R8h +KQ7t4682xsPvEN3Lc58H9aDHcTCddrBv+mCw4b9Sud0SZ0vkKn9NkWls bYUVL0EdLh7Ogq64anJbKRZfJbVRAAZdzGov3Z9QYsc29QGyvpU6bwBGy 6UsgrYRAt+vXwlI+Npslvv+6m4hHMKnYfTS850pJSaJ/vIR7P3qjx9Jut 5M1oFGbks7C2EXhSoMdOk54ho/r8aUqpp1PaLcI+1uV2qdlslKg7YXo6o w==; X-CSE-ConnectionGUID: 2Fbj7BcHRiGygdLKoHT8aQ== X-CSE-MsgGUID: M5VUoWzmT6G0Xz2WJsYqoQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998170" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998170" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:36 -0700 X-CSE-ConnectionGUID: HC7QmSjAQzmXF+suzlxdtw== X-CSE-MsgGUID: WzjaX65xQvmUtHYsz+wdyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260459" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:36 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Sohil Mehta Subject: [PATCH 05/10] selftests/x86/apx: Add APX test Date: Tue, 15 Apr 2025 19:16:55 -0700 Message-ID: <20250416021720.12305-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The extended general-purpose registers for APX may contain random data, which is currently assumed by the xstate testing framework. This allows the testing of the new userspace feature using the common test code. Invoke the test entry function from apx.c after enumerating the state component and adding it to the support list Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- Changes from the last posting: https://lore.kernel.org/lkml/20250320234301.8342-10-chang.seok.bae@intel.co= m/ * Add review tag Some might view this standalone test as potentially converging with other tests. I encountered similar situation when posting the selftest rework: https://lore.kernel.org/lkml/20250226010731.2456-10-chang.seok.bae@intel.= com/ Maybe it's worthwhile to clarify the consideration again here: Alternatively, this invocation could be placed directly in xstate.c::main(). However, the current test file naming convention, which clearly specifies the tested area, seems reasonable. Adding apx.c considerably aligns with that convention. --- tools/testing/selftests/x86/Makefile | 3 ++- tools/testing/selftests/x86/apx.c | 10 ++++++++++ tools/testing/selftests/x86/xstate.c | 3 ++- tools/testing/selftests/x86/xstate.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/x86/apx.c diff --git a/tools/testing/selftests/x86/Makefile b/tools/testing/selftests= /x86/Makefile index 28422c32cc8f..f703fcfe9f7c 100644 --- a/tools/testing/selftests/x86/Makefile +++ b/tools/testing/selftests/x86/Makefile @@ -19,7 +19,7 @@ TARGETS_C_32BIT_ONLY :=3D entry_from_vm86 test_syscall_vd= so unwind_vdso \ test_FCMOV test_FCOMI test_FISTTP \ vdso_restorer TARGETS_C_64BIT_ONLY :=3D fsgsbase sysret_rip syscall_numbering \ - corrupt_xstate_header amx lam test_shadow_stack avx + corrupt_xstate_header amx lam test_shadow_stack avx apx # Some selftests require 32bit support enabled also on 64bit systems TARGETS_C_32BIT_NEEDED :=3D ldt_gdt ptrace_syscall =20 @@ -136,3 +136,4 @@ $(OUTPUT)/nx_stack_64: CFLAGS +=3D -Wl,-z,noexecstack $(OUTPUT)/avx_64: CFLAGS +=3D -mno-avx -mno-avx512f $(OUTPUT)/amx_64: EXTRA_FILES +=3D xstate.c $(OUTPUT)/avx_64: EXTRA_FILES +=3D xstate.c +$(OUTPUT)/apx_64: EXTRA_FILES +=3D xstate.c diff --git a/tools/testing/selftests/x86/apx.c b/tools/testing/selftests/x8= 6/apx.c new file mode 100644 index 000000000000..d9c8d41b8c5a --- /dev/null +++ b/tools/testing/selftests/x86/apx.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define _GNU_SOURCE + +#include "xstate.h" + +int main(void) +{ + test_xstate(XFEATURE_APX); +} diff --git a/tools/testing/selftests/x86/xstate.c b/tools/testing/selftests= /x86/xstate.c index 23c1d6c964ea..97fe4bd8bc77 100644 --- a/tools/testing/selftests/x86/xstate.c +++ b/tools/testing/selftests/x86/xstate.c @@ -31,7 +31,8 @@ (1 << XFEATURE_OPMASK) | \ (1 << XFEATURE_ZMM_Hi256) | \ (1 << XFEATURE_Hi16_ZMM) | \ - (1 << XFEATURE_XTILEDATA)) + (1 << XFEATURE_XTILEDATA) | \ + (1 << XFEATURE_APX)) =20 static inline uint64_t xgetbv(uint32_t index) { diff --git a/tools/testing/selftests/x86/xstate.h b/tools/testing/selftests= /x86/xstate.h index 42af36ec852f..e91e3092b5d2 100644 --- a/tools/testing/selftests/x86/xstate.h +++ b/tools/testing/selftests/x86/xstate.h @@ -33,6 +33,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILECFG, XFEATURE_XTILEDATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; @@ -59,6 +60,7 @@ static const char *xfeature_names[] =3D "unknown xstate feature", "AMX Tile config", "AMX Tile data", + "APX registers", "unknown xstate feature", }; =20 --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91B56228CB2 for ; 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a="48998176" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998176" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:39 -0700 X-CSE-ConnectionGUID: nQUw0VpKQlWthNa96zxqLA== X-CSE-MsgGUID: fJRfMVgvQcOPoT1Oyl3X3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260470" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:39 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 06/10] x86/fpu: Log XSAVE disablement consistently Date: Tue, 15 Apr 2025 19:16:56 -0700 Message-ID: <20250416021720.12305-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Not all paths that lead to fpu__init_disable_system_xstate() currently emit a message indicating that XSAVE has been disabled. Move the print statement into the function to ensure the message in all cases. Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae Link: https://lore.kernel.org/lkml/d6d19e39-2749-4d45-aeab-a209a0ecba17@int= el.com --- New patch for following up patch 3. --- arch/x86/kernel/fpu/xstate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 2ac1fc182273..8b14c9d3a1df 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -751,6 +751,8 @@ static int __init init_xstate_size(void) */ static void __init fpu__init_disable_system_xstate(unsigned int legacy_siz= e) { + pr_info("x86/fpu: XSAVE disabled\n"); + fpu_kernel_cfg.max_features =3D 0; cr4_clear_bits(X86_CR4_OSXSAVE); setup_clear_cpu_cap(X86_FEATURE_XSAVE); @@ -821,7 +823,7 @@ void __init fpu__init_system_xstate(unsigned int legacy= _size) * This is a problematic CPU configuration where two * conflicting state components are both enumerated. */ - pr_err("x86/fpu: Both APX/MPX present in the CPU's xstate features: 0x%l= lx, disabling XSAVE.\n", + pr_err("x86/fpu: Both APX/MPX present in the CPU's xstate features: 0x%l= lx.\n", fpu_kernel_cfg.max_features); goto out_disable; } @@ -900,7 +902,7 @@ void __init fpu__init_system_xstate(unsigned int legacy= _size) init_fpstate.xfeatures =3D fpu_kernel_cfg.default_features; =20 if (init_fpstate.size > sizeof(init_fpstate.regs)) { - pr_warn("x86/fpu: init_fpstate buffer too small (%zu < %d), disabling XS= AVE\n", + pr_warn("x86/fpu: init_fpstate buffer too small (%zu < %d)\n", sizeof(init_fpstate.regs), init_fpstate.size); goto out_disable; } @@ -912,7 +914,7 @@ void __init fpu__init_system_xstate(unsigned int legacy= _size) * xfeatures mask. */ if (xfeatures !=3D fpu_kernel_cfg.max_features) { - pr_err("x86/fpu: xfeatures modified from 0x%016llx to 0x%016llx during i= nit, disabling XSAVE\n", + pr_err("x86/fpu: xfeatures modified from 0x%016llx to 0x%016llx during i= nit\n", xfeatures, fpu_kernel_cfg.max_features); goto out_disable; } --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D7C322A4C2 for ; Wed, 16 Apr 2025 02:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769863; cv=none; b=KWa8mcHBHWUbwT4kg0Ef7TV3teo9iTpGdDSLCtYaZn98T+auxyPiLxVB30V18UrKgqiCBg8ENF7/paeP4QpNn275z6IT2Xuuankdrktm5LEa3XiyiPphMEDxfK2f6pXRjxYv65yjuubG2OS4+87xS4Cqw+kO666JahNaEhMZrVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769863; c=relaxed/simple; bh=5MOeIHBM+usD4ZUhtxyVCKaIctcPE34AfdGdztUVcCk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R/t3543V0v4ccjxqp7qruI4Zc4y1CUII22WiwcY/gZIvaXoSfudqC8D7bHxrXxnqwdrQGebPATJn4X9ZZ8bimsAmMKPJVqOdeNH8Hksy4PZQnwL2mYl5l3KWwbl49OLC8j4M0G6eUTlPjFoQcRGaAHiDG7RDV9J93yvT4ZVfKzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lvZ3Q4Km; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lvZ3Q4Km" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769861; x=1776305861; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5MOeIHBM+usD4ZUhtxyVCKaIctcPE34AfdGdztUVcCk=; b=lvZ3Q4KmeowSgs0HDQfbYRQ3ZVK3xXShw387BLKclgJpRfizfOylOvm/ qTTVo8ZirDzHA+FG7HijbCOKkLdu+4+DBexvzOoOZSb77Qq1qLkfBmLOS TpRghdHtoxvPqHEkNFkOJsCg/m+ZlLNrGFXIOqtr9qQIRhMl1TjFi/Dd8 QGDXEqcIHZ+U76QSiOWCeEMF0CxiKIT5gKGTMkZ9L5ncPQQFx+sOKR6JO s9U/Xp1gIxkPFaR3QP7qpa4v2tgFFX0H2kPQCW+DhFqcfESqIx2sHldnb 4mpfwoecK8nxYrRDJLNWw8/FM4kksQD77Pmzlil84EBP75ptCaPn9rD9T A==; X-CSE-ConnectionGUID: 8GYPD73MQl2JLOgPrjrI/A== X-CSE-MsgGUID: e+43c6I7SmiDDiS2r/MxfQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998183" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998183" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:41 -0700 X-CSE-ConnectionGUID: arO8y6H5Q0CkF9D8YChelw== X-CSE-MsgGUID: mABOB4zKTnSupPb5DR/AsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260488" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:41 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 07/10] x86/fpu: Refactor xfeature bitmask update code for sigframe XSAVE Date: Tue, 15 Apr 2025 19:16:57 -0700 Message-ID: <20250416021720.12305-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, saving register states in the signal frame, the legacy feature bits are always set in xregs_state->header->xfeatures. This code sequence can be generalized for reuse in similar cases. Refactor the logic to ensure a consistent approach across similar usages. Signed-off-by: Chang S. Bae --- Changes from the last posting: https://lore.kernel.org/lkml/20250214010607.7067-2-chang.seok.bae@intel.com/ * No change This patch and the next were previously posted together. I thought this refactoring is a meaningful step toward decoupling PKRU from an unnecessary dependency on XGETBV(1). --- arch/x86/kernel/fpu/signal.c | 11 +---------- arch/x86/kernel/fpu/xstate.h | 12 ++++++++++++ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index b8b4fa9c2d04..c3ec2512f2bb 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -114,7 +114,6 @@ static inline bool save_xstate_epilog(void __user *buf,= int ia32_frame, { struct xregs_state __user *x =3D buf; struct _fpx_sw_bytes sw_bytes =3D {}; - u32 xfeatures; int err; =20 /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ @@ -127,12 +126,6 @@ static inline bool save_xstate_epilog(void __user *buf= , int ia32_frame, err |=3D __put_user(FP_XSTATE_MAGIC2, (__u32 __user *)(buf + fpstate->user_size)); =20 - /* - * Read the xfeatures which we copied (directly from the cpu or - * from the state in task struct) to the user buffers. - */ - err |=3D __get_user(xfeatures, (__u32 __user *)&x->header.xfeatures); - /* * For legacy compatible, we always set FP/SSE bits in the bit * vector while saving the state to the user context. This will @@ -144,9 +137,7 @@ static inline bool save_xstate_epilog(void __user *buf,= int ia32_frame, * header as well as change any contents in the memory layout. * xrestore as part of sigreturn will capture all the changes. */ - xfeatures |=3D XFEATURE_MASK_FPSSE; - - err |=3D __put_user(xfeatures, (__u32 __user *)&x->header.xfeatures); + err |=3D set_xfeature_in_sigframe(x, XFEATURE_MASK_FPSSE); =20 return !err; } diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index 9a3a8ccf13bf..aadf02aed071 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -69,6 +69,18 @@ static inline u64 xfeatures_mask_independent(void) return fpu_kernel_cfg.independent_features; } =20 +static inline int set_xfeature_in_sigframe(struct xregs_state __user *xbuf= , u64 mask) +{ + u64 xfeatures; + int err; + + /* Read the xfeatures value already saved in the user buffer */ + err =3D __get_user(xfeatures, &xbuf->header.xfeatures); + xfeatures |=3D mask; + err |=3D __put_user(xfeatures, &xbuf->header.xfeatures); + return err; +} + /* * Update the value of PKRU register that was already pushed onto the sign= al frame. */ --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C22722A4EB for ; Wed, 16 Apr 2025 02:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769865; cv=none; b=Kb3zvQjq/44VX8CZmGI7BHh4zZkiSvkxq6gSFwnUNoPaHwkTkeaNzJNqAVymh50mfveISfGNdQYeHZNnmgoNtWHe+j9oqZ7vh1u1SZ2alAqswl4FdGEaCY3UDpkWjPBK/Pk+mRetiSfVE+h2J4IcuqBhcz8PNu8kEzOp5mMcfus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769865; c=relaxed/simple; bh=gkQKhjM3hJq53J8KDwyLOaPL+LB1NuqN1mHQhVIODcM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pZu2eGqUGgYVQXHdUSTessCF0HrTC/j4FghTxVHmYdBol0h7N6eIeK2EOr9gxKFE5unS6UnS11HnbRy7nuiSqEJWoVyHh1EWfZD15pfN+FfAPzr6NiT+pBgdSAt1yfaU+Yyc9w+dIS2NsErILtquj82lL6Oxi2V5Lpca8u6v0Tw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VyEj5Cid; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VyEj5Cid" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769863; x=1776305863; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gkQKhjM3hJq53J8KDwyLOaPL+LB1NuqN1mHQhVIODcM=; b=VyEj5CidpSOrNQm/VprG5zDvpxBBPrTTPWAjxcKGuFKbq4/eFjO91b95 0zZeESsPZGcdoLqvQCAxw83bqLrr+N9c4SrWb7e+AZwOBhQ/ak8miNpFk s2CnITZ/ImNkItpCGsbUi8ZmpiD2zTi3aBbW1+34/e9eByI4vFA0uSh6Q dL/BWwXwdFL6VwghBzX47hzXj0Q1HHR4WvnMQB6h0b7JuNPBgb0EQOQYz IhaEBhVSDaGpVtYMAtV0gTjZt3e2TWmJO4xDLMM00H+2lvwJXhHNlKrxl yeoxomn0fw1EDavEn/Jr0P6T2YRrJ0F0QDp7VCm2vu6dkGnQAuwUJCaEc Q==; X-CSE-ConnectionGUID: 0v8uKmvfRMizLWYph0xnXA== X-CSE-MsgGUID: DGNag0XqR6q0olJx12gUJQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998189" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998189" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:43 -0700 X-CSE-ConnectionGUID: GlKOvbGTTCiE1ZGX/Tc1Dw== X-CSE-MsgGUID: YHKIGLrjSuGcfRcwFQsYiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260498" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:43 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Aruna Ramakrishna , Tony W Wang-oc Subject: [PATCH 08/10] x86/pkeys: Simplify PKRU update in signal frame Date: Tue, 15 Apr 2025 19:16:58 -0700 Message-ID: <20250416021720.12305-9-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The signal delivery logic was modified to always set the PKRU bit in xregs_state->header->xfeatures by this commit: ae6012d72fa6 ("x86/pkeys: Ensure updated PKRU value is XRSTOR'd") However, the change derives the bitmask value using XGETBV(1), rather than simply updating the buffer that already holds the value. Thus, this approach induces an unnecessary dependency on XGETBV1 for PKRU handling. Eliminate the dependency by using the established helper function. Subsequently, remove the now-unused 'mask' argument. Signed-off-by: Chang S. Bae Cc: Aruna Ramakrishna Cc: Tony W Wang-oc --- Changes from the last posting: https://lore.kernel.org/lkml/20250214010607.7067-3-chang.seok.bae@intel.com/ * Massage the changelog Additional Context: Previously, the concern was raised about environments where XGETBV1 is unavailable =E2=80=94 such as in some virtual machines: https://lore.kernel.org/lkml/20250102075419.2559-1-TonyWWang-oc@zhaoxin= .com That patch tried to sidestep the problem by skipping PKRU updates entirely when XGETBV1 is inaccessible. However, this assumed the dependency was necessary, which isn=E2=80=99t the case. --- arch/x86/kernel/fpu/xstate.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index aadf02aed071..a6d987c16293 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -84,18 +84,15 @@ static inline int set_xfeature_in_sigframe(struct xregs= _state __user *xbuf, u64 /* * Update the value of PKRU register that was already pushed onto the sign= al frame. */ -static inline int update_pkru_in_sigframe(struct xregs_state __user *buf, = u64 mask, u32 pkru) +static inline int update_pkru_in_sigframe(struct xregs_state __user *buf, = u32 pkru) { - u64 xstate_bv; int err; =20 if (unlikely(!cpu_feature_enabled(X86_FEATURE_OSPKE))) return 0; =20 /* Mark PKRU as in-use so that it is restored correctly. */ - xstate_bv =3D (mask & xfeatures_in_use()) | XFEATURE_MASK_PKRU; - - err =3D __put_user(xstate_bv, &buf->header.xfeatures); + err =3D set_xfeature_in_sigframe(buf, XFEATURE_MASK_PKRU); if (err) return err; =20 @@ -319,7 +316,7 @@ static inline int xsave_to_user_sigframe(struct xregs_s= tate __user *buf, u32 pkr clac(); =20 if (!err) - err =3D update_pkru_in_sigframe(buf, mask, pkru); + err =3D update_pkru_in_sigframe(buf, pkru); =20 return err; } --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A6322A7EE for ; Wed, 16 Apr 2025 02:17:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769866; cv=none; b=cHod/ctHO0kQuLEmWw3oaPG5VkSaLREc6/aTBQGZLGb7jjIowGc+dti1I6AX7+Hq+U6s8keDIf3YBqb2pYAsMa0jZhy5WOvABR8QBN103UkAVcHJ+ybEUwlu/0GuqQtaNpCFHR3juhFEZdaJQ8m2DAgvTbk0DPVw7zmuaOKpd5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769866; c=relaxed/simple; bh=F70kJX0NTy44VydwUCIUFgm54FUl3J0CEYjaigN7TtA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C/EOnbkdmZCrclHVJoo1ZpdmRNLxxAZNQk4/ALKx6Mi8n8TeNnj0GVK5YL/KH0/y0AM1nkZk1T6VFl+xE/V1edx6/8gx5UCF+Fa9plTjHTw6xb1aw10QEvuOwGlmXAV/4UuAeIXW0u7SpYoquYfXCsds54R5y49Cj4gvVtWuePc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VXz5+ZYd; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VXz5+ZYd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769865; x=1776305865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F70kJX0NTy44VydwUCIUFgm54FUl3J0CEYjaigN7TtA=; b=VXz5+ZYd3W7GFBOBbtlklUCI82czfaBII7RFs+/wz8CJtqXUSfINr227 rIdf80ojAsuqsZo8yPOtOH+K4wr3DVmx4F0ujRh/JtLrYvgCnhbXroa/q D0JAc1oJapAh3eW7QqKymBA5pR/rn1XD3ix8y77G3qGNOLEYR3e+rVT+O VlSgEiTmHxEmHQhiKhrBDy3ZEEx7lEfx3IEZvIX1OuVsqDpOa4pPgo0dU NtaC///0DRkNWvwyseyEMS8MgnJSaeDgmRNB/cQ1kOXjvTJXyyQ8tHgp5 K3zy4GCqiwL98csyTUsn3BHZrksDc6fKl+fV5yyTN2o76Cfbv21Ui0NQ0 Q==; X-CSE-ConnectionGUID: N96qVMmrTuGvHo1za4Xt8g== X-CSE-MsgGUID: 2jbFBIM7SS+VYt+nia2aEA== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998198" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998198" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:45 -0700 X-CSE-ConnectionGUID: Xu53YA/8ToWJuDGzIvd3FA== X-CSE-MsgGUID: 3QHJOctUQpax7uw4/C1o7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260507" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:45 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Nikolay Borisov Subject: [PATCH 09/10] x86/fpu: Remove export of mxcsr_feature_mask Date: Tue, 15 Apr 2025 19:16:59 -0700 Message-ID: <20250416021720.12305-10-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The variable was previously referenced in KVM code but the last usage was removed by: ea4d6938d4c0 ("x86/fpu: Replace KVMs home brewed FPU copy from user") Remove its export symbol. Signed-off-by: Chang S. Bae Reviewed-by: Nikolay Borisov --- Changes from the last posting: https://lore.kernel.org/lkml/d143cc4c-8f8e-48e5-87f1-dded3272433a@suse.com * Note the commit that removed its usage (Nikolay) * Include review tag Apologies -- given the review tag, I should have followed up this earlier. --- arch/x86/kernel/fpu/init.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 16b6611634c3..2d9b5e677559 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -100,7 +100,6 @@ static void __init fpu__init_system_early_generic(void) * Boot time FPU feature detection code: */ unsigned int mxcsr_feature_mask __ro_after_init =3D 0xffffffffu; -EXPORT_SYMBOL_GPL(mxcsr_feature_mask); =20 static void __init fpu__init_system_mxcsr(void) { --=20 2.45.2 From nobody Fri Dec 19 20:36:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EDA1221F12 for ; Wed, 16 Apr 2025 02:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769869; cv=none; b=LuMp+gGEvKOETwa4N/QvICKrmE3Y3VjB9m/ZsYcN2w5c6EGhrxUo7zWxjUX0yUo3OACrUdJYYVcKYJvqY/zKes97sruoVRB5OFZ8VCMzqAJRqpbOI+bbblyJ9k2jwn6i7Nr0McX+KrS7GEWwxUFN5oFQccqUqD8bOuoREKi+G6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744769869; c=relaxed/simple; bh=k1KtmolTS7TvXL3ztJB2/zi3lUwTZt9i1snZyArI/H8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JZsA4ihLF5+kvIH11r9/h1P0xYG5xwL4Xl3HOCzN01pbfiqxcSBHX84tc+sUhwk9fHmY01NvR7mHz51yOJFkD/7PGkeAGejgINE3a6pWWudrp1wvlYmXeFDYtZ+r16/otrQkW07JZ0grgGI7W+vh7WnG2wQmohqx+9y87MrzY3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hqUKqDui; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hqUKqDui" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744769867; x=1776305867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k1KtmolTS7TvXL3ztJB2/zi3lUwTZt9i1snZyArI/H8=; b=hqUKqDuiDlSSW1rPkBs1XEc3wR+7TRui2ELYaoay+uB7nmcLVlaqEJIW ozcfG+qWZm+/57xBRHnsX1pLW1pqDgDVAolOeyXUOf7C5xPeKUryTcnTw nBu9yCZH6N2hNUORna+4ugcu7y+jtVyzPsZZK6JotG9D8QsvHytlfWamK BxehqDof6TwU1URTAZPhqN9tLOllamuHpLZUlBzQ8wdLPxyoX5ZW7Ecd9 m35If0kHJPDZS1rM9VNvmYpTpvJ06lLeq7Rtq3CPUpicP1+IDm6KrYSc8 UJGAN1b6ILxRB83p6jv4ph1ZbLZfo2kiI6ftPD/nWqXMn5d+vcelRGOiK g==; X-CSE-ConnectionGUID: 1NUD7du3Syqv2XYoshHJlA== X-CSE-MsgGUID: U3uKHhbpQaqRM5Ke3zMekg== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="48998204" X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="48998204" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 19:17:47 -0700 X-CSE-ConnectionGUID: HhUCit1FQx+vBFrKEqbGRQ== X-CSE-MsgGUID: 9s7fq6YTTQCbaWI5q3v9gA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,214,1739865600"; d="scan'208";a="130260517" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.128.227]) by orviesa010.jf.intel.com with ESMTP; 15 Apr 2025 19:17:47 -0700 From: "Chang S. Bae" To: mingo@redhat.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 10/10] x86/fpu: Rename fpu_reset_fpregs() to fpu_reset_fpstate_regs() Date: Tue, 15 Apr 2025 19:17:00 -0700 Message-ID: <20250416021720.12305-11-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250416021720.12305-1-chang.seok.bae@intel.com> References: <20250416021720.12305-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The original function name came from an overly compressed form of 'fpstate_regs' by commit: e61d6310a0f8 ("x86/fpu: Reset permission and fpstate on exec()") However, the term 'fpregs' typically refers to physical FPU registers. In contrast, this function copies the init values to fpu->fpstate->regs, not hardware registers. Rename the function to better reflect what it actually does. No functional change. Signed-off-by: Chang S. Bae --- Changes from the last posting: https://lore.kernel.org/lkml/20240530192739.172566-2-chang.seok.bae@intel.c= om * Refine the changelog * Add a note referencing the original naming decision. This patch was originally submitted as part of the In-Field Scan driver series. Although that series is now dropped that I believe, this rename still serves as a useful cleanup to correct a naming choice that I previously made :(. --- arch/x86/kernel/fpu/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 3a19877a314e..8d674435f173 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -733,7 +733,7 @@ static inline void restore_fpregs_from_init_fpstate(u64= features_mask) /* * Reset current->fpu memory state to the init values. */ -static void fpu_reset_fpregs(void) +static void fpu_reset_fpstate_regs(void) { struct fpu *fpu =3D x86_task_fpu(current); =20 @@ -768,7 +768,7 @@ void fpu__clear_user_states(struct fpu *fpu) =20 fpregs_lock(); if (!cpu_feature_enabled(X86_FEATURE_FPU)) { - fpu_reset_fpregs(); + fpu_reset_fpstate_regs(); fpregs_unlock(); return; } @@ -798,7 +798,7 @@ void fpu__clear_user_states(struct fpu *fpu) void fpu_flush_thread(void) { fpstate_reset(x86_task_fpu(current)); - fpu_reset_fpregs(); + fpu_reset_fpstate_regs(); } /* * Load FPU context before returning to userspace. --=20 2.45.2