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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-22c33fc47e0sm1235925ad.167.2025.04.15.17.02.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:13 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Benson Leung , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 1/7] platform/chrome: cros_ec_typec: No pending status means attention Date: Tue, 15 Apr 2025 17:02:01 -0700 Message-ID: <20250416000208.3568635-2-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable If we aren't expecting a status update when cros_typec_displayport_status_update() is called then we're handling an attention message, like HPD high/low or IRQ. Call typec_altmode_attention() in this case so that HPD signaling works in the DP altmode driver. Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov --- drivers/platform/chrome/cros_typec_altmode.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_altmode.c b/drivers/platfor= m/chrome/cros_typec_altmode.c index 557340b53af0..c2d9c548b5e8 100644 --- a/drivers/platform/chrome/cros_typec_altmode.c +++ b/drivers/platform/chrome/cros_typec_altmode.c @@ -280,11 +280,8 @@ int cros_typec_displayport_status_update(struct typec_= altmode *altmode, typec_altmode_get_drvdata(altmode); struct cros_typec_altmode_data *adata =3D &dp_data->adata; =20 - if (!dp_data->pending_status_update) { - dev_dbg(&altmode->dev, - "Got DPStatus without a pending request\n"); - return 0; - } + if (!dp_data->pending_status_update) + return typec_altmode_attention(altmode, data->status); =20 if (dp_data->configured && dp_data->data.conf !=3D data->conf) dev_dbg(&altmode->dev, --=20 https://chromeos.dev From nobody Fri Dec 19 19:15:52 2025 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEEAD2AE66 for ; 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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-73bd21c3216sm9157830b3a.49.2025.04.15.17.02.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:14 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Benson Leung , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 2/7] platform/chrome: cros_ec_typec: Allow DP configure to work Date: Tue, 15 Apr 2025 17:02:02 -0700 Message-ID: <20250416000208.3568635-3-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The DP altmode driver fails the configure stage because the status VDO that is spoofed in cros_typec_enable_dp() is missing a couple flags. Add them so that the configure succeeds. This has the nice side effect of properly reflecting the pin assignment and configuration of the DP altmode in sysfs. Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov --- drivers/platform/chrome/cros_ec_typec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index 6ee182101bc9..2cbe29f08064 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -531,7 +531,7 @@ static int cros_typec_enable_dp(struct cros_typec_data = *typec, } =20 /* Status VDO. */ - dp_data.status =3D DP_STATUS_ENABLED; + dp_data.status =3D DP_STATUS_ENABLED | DP_STATUS_CON_UFP_D | DP_STATUS_PR= EFER_MULTI_FUNC; if (port->mux_flags & USB_PD_MUX_HPD_IRQ) dp_data.status |=3D DP_STATUS_IRQ_HPD; if (port->mux_flags & USB_PD_MUX_HPD_LVL) --=20 https://chromeos.dev From nobody Fri Dec 19 19:15:52 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68C066F30C for ; Wed, 16 Apr 2025 00:02:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744761739; cv=none; b=KlHvzH/3rdhIJcoZJvm8xDaL+etVj57+OiJjYSvZnXuaUaeTefflLjpuVZODaP5RyZqHxO3YmSXXln4zH+yOG1RsGuH3b7Am5KVydsmLbQDM1Tudu/IASyx9GWEh98aKEEOv9fuccQuvIL85QUSG8+XS1x776dCklLYv8qcG8N4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744761739; c=relaxed/simple; bh=GwnkAZU+uW9fAkCDWWme3oB1O6PxoBs+pYMPoHkdFMQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aYHJDwgUecFp/raF+GoVkOOnALrHZwVPe8i3qqO+EU4c1heFEyjLzevJUL73Gu4UowBoCsMZZJPUsq5//r4Tf7V8HxkJabdevv9N/MryVNqX+HeCEiUeGL1e3opWRWxkI2F/Zs1ExKCHqq4Ja+zSjupimNCYPt1o9LwNUxXfRvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=jDxg0ZmW; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jDxg0ZmW" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2254e0b4b79so84045125ad.2 for ; Tue, 15 Apr 2025 17:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1744761737; x=1745366537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pLpTjFW7p6ghiYRblP02dy0kbs1t/nRG9KfdA64BMng=; b=jDxg0ZmWXkY7/crCU4dh2s0ImdvGa3j7mKy8npK2BmZp6SxxErN+YJw5TL8PoSxTc6 9G5uulvzJU1bR9eFHsBjgU2rEnJAtHWJb+7b+QmwwZqZ0JTBhAlU/34sZDLC6DnJjlNo J3DrfSpyMsN9ZDzq2VZpjr4riVdV+FqZlWbLQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744761737; x=1745366537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pLpTjFW7p6ghiYRblP02dy0kbs1t/nRG9KfdA64BMng=; b=ViQ1fGtVGU0vr9mv+tkX8zlYPdDa5ShIs6FQ9ugejW8B6dl0mh/9KMLgqqwJlgoiIM F49Uddn6tC0gcFrz4pdK4jjCg9HXSk2SUzVk20mIrh+a7tJ8bkc+N7EZ2Z07rPT9nCZf OuX0MMa8xpja53ysLKNS9iZsE63qCMSouNZ4wmi2OiWAZc5TbWhJesr3iLz7+W+t1Fkt t12Po31pbGskHjU+ly4FnTymo5+ZprVCeVHa+QM4YiJpXzo0zTSOMiwZg9ZeLk30u8lJ uOUAhbx75r2gQZ6BajFg8TVyTDhKZIJau2iqjbwLs+LLQC2N8d91E9Usg+E2QCG1V1aQ rjPw== X-Gm-Message-State: AOJu0Yw7e/uFwWtXoyyRwWA6qdzH7CVorfsaU4sWSi4IDy27dZ1EMF11 HGmdgqazgvYoCu//tNBrc5/YadRQtBKcbIi8vCnmUizeodP1CGNnLH8qE+9lFw== X-Gm-Gg: ASbGncvKXzxyryjKvJ12JJE/LdiJ/XpXBI4EOUgx8p8vxa/hh/uVuk7pPBvC9eDta7L q5x2Lf2Y/1rIaYTTycY4NYxNx9bX+q1reDBWRdvICm0LI79ioHF3DaoEJAPgTp47Szjpe1MrC7h 7QIrrXTZmZuWATD6sztYFiQ01djjd442D1UsjPV3YeACiKRbZ9XrtcEgOq2xzYa/dKL8TH+2380 IxHopSplUOMcnNi9G59i3igIbPdJj3z2Wpze690sSf7Xkyf/TwF66MulFoehFex3ujsW3kY/T1q GZaVhFLupX2thfs1Ka0V9AkwoEdGt2NLKPH3wrQldb3xgPLgjhczHxGAAUoYgdSw1qPeOpkkreZ NOw== X-Google-Smtp-Source: AGHT+IFgDSfSzHJQGblYKtBgX+uGjROsnXUma1oaTnVLcJEUU+QM71Xipmk/uC+evcJTJfTYjoWWzQ== X-Received: by 2002:a17:902:d585:b0:223:536d:f67b with SMTP id d9443c01a7336-22c31a86b22mr19203715ad.38.1744761736701; Tue, 15 Apr 2025 17:02:16 -0700 (PDT) Received: from localhost (199.24.125.34.bc.googleusercontent.com. [34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-308613b3849sm196331a91.38.2025.04.15.17.02.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:16 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Benson Leung , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 3/7] platform/chrome: cros_ec_typec: Support EC mode entry Date: Tue, 15 Apr 2025 17:02:03 -0700 Message-ID: <20250416000208.3568635-4-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Support ChromeOS EC firmwares that don't support AP mode entry. Check that the mode has been entered by querying the EC and reject mode entry attempts if the EC hasn't already entered the mode requested. This allows us to bind the DP altmode driver on devices that don't support AP mode entry, i.e. most ChromeOS devices where the EC controls mode entry. Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_altmode.c | 112 +++++++++++++------ 1 file changed, 75 insertions(+), 37 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_altmode.c b/drivers/platfor= m/chrome/cros_typec_altmode.c index c2d9c548b5e8..97ca4cfabbc0 100644 --- a/drivers/platform/chrome/cros_typec_altmode.c +++ b/drivers/platform/chrome/cros_typec_altmode.c @@ -58,31 +58,50 @@ static void cros_typec_altmode_work(struct work_struct = *work) static int cros_typec_altmode_enter(struct typec_altmode *alt, u32 *vdo) { struct cros_typec_altmode_data *adata =3D typec_altmode_get_drvdata(alt); - struct ec_params_typec_control req =3D { - .port =3D adata->port->port_num, - .command =3D TYPEC_CONTROL_COMMAND_ENTER_MODE, - }; + struct cros_ec_device *ec =3D adata->port->typec_data->ec; + unsigned int port =3D adata->port->port_num; int svdm_version; int ret; =20 if (!adata->ap_mode_entry) { - dev_warn(&alt->dev, - "EC does not support AP driven mode entry\n"); - return -EOPNOTSUPP; + struct ec_response_usb_pd_mux_info resp; + struct ec_params_usb_pd_mux_info req =3D { + .port =3D port, + }; + uint8_t flags; + + if (adata->sid =3D=3D USB_TYPEC_DP_SID) + flags =3D USB_PD_MUX_DP_ENABLED; + else if (adata->sid =3D=3D USB_TYPEC_TBT_SID) + flags =3D USB_PD_MUX_TBT_COMPAT_ENABLED; + else + return -EOPNOTSUPP; + + ret =3D cros_ec_cmd(ec, 0, EC_CMD_USB_PD_MUX_INFO, + &req, sizeof(req), &resp, sizeof(resp)); + if (ret < 0) + return ret; + + if (!(resp.flags & flags)) + return -EINVAL; + } else { + struct ec_params_typec_control req =3D { + .port =3D port, + .command =3D TYPEC_CONTROL_COMMAND_ENTER_MODE, + }; + + if (adata->sid =3D=3D USB_TYPEC_DP_SID) + req.mode_to_enter =3D CROS_EC_ALTMODE_DP; + else if (adata->sid =3D=3D USB_TYPEC_TBT_SID) + req.mode_to_enter =3D CROS_EC_ALTMODE_TBT; + else + return -EOPNOTSUPP; + + ret =3D cros_ec_cmd(ec, 0, EC_CMD_TYPEC_CONTROL, &req, sizeof(req), NULL= , 0); + if (ret < 0) + return ret; } =20 - if (adata->sid =3D=3D USB_TYPEC_DP_SID) - req.mode_to_enter =3D CROS_EC_ALTMODE_DP; - else if (adata->sid =3D=3D USB_TYPEC_TBT_SID) - req.mode_to_enter =3D CROS_EC_ALTMODE_TBT; - else - return -EOPNOTSUPP; - - ret =3D cros_ec_cmd(adata->port->typec_data->ec, 0, EC_CMD_TYPEC_CONTROL, - &req, sizeof(req), NULL, 0); - if (ret < 0) - return ret; - svdm_version =3D typec_altmode_get_svdm_version(alt); if (svdm_version < 0) return svdm_version; @@ -97,31 +116,52 @@ static int cros_typec_altmode_enter(struct typec_altmo= de *alt, u32 *vdo) schedule_work(&adata->work); =20 mutex_unlock(&adata->lock); - return ret; + + return 0; } =20 static int cros_typec_altmode_exit(struct typec_altmode *alt) { struct cros_typec_altmode_data *adata =3D typec_altmode_get_drvdata(alt); - struct ec_params_typec_control req =3D { - .port =3D adata->port->port_num, - .command =3D TYPEC_CONTROL_COMMAND_EXIT_MODES, - }; + struct cros_ec_device *ec =3D adata->port->typec_data->ec; + unsigned int port =3D adata->port->port_num; int svdm_version; int ret; =20 if (!adata->ap_mode_entry) { - dev_warn(&alt->dev, - "EC does not support AP driven mode exit\n"); - return -EOPNOTSUPP; + struct ec_response_usb_pd_mux_info resp; + struct ec_params_usb_pd_mux_info req =3D { + .port =3D port, + }; + uint8_t flags; + + if (adata->sid =3D=3D USB_TYPEC_DP_SID) + flags =3D USB_PD_MUX_DP_ENABLED; + else if (adata->sid =3D=3D USB_TYPEC_TBT_SID) + flags =3D USB_PD_MUX_TBT_COMPAT_ENABLED; + else + return -EOPNOTSUPP; + + ret =3D cros_ec_cmd(ec, 0, EC_CMD_USB_PD_MUX_INFO, + &req, sizeof(req), &resp, sizeof(resp)); + if (ret < 0) + return ret; + + if (resp.flags & flags) + return -EINVAL; + } else { + struct ec_params_typec_control req =3D { + .port =3D port, + .command =3D TYPEC_CONTROL_COMMAND_EXIT_MODES, + }; + + ret =3D cros_ec_cmd(adata->port->typec_data->ec, 0, EC_CMD_TYPEC_CONTROL, + &req, sizeof(req), NULL, 0); + + if (ret < 0) + return ret; } =20 - ret =3D cros_ec_cmd(adata->port->typec_data->ec, 0, EC_CMD_TYPEC_CONTROL, - &req, sizeof(req), NULL, 0); - - if (ret < 0) - return ret; - svdm_version =3D typec_altmode_get_svdm_version(alt); if (svdm_version < 0) return svdm_version; @@ -136,7 +176,8 @@ static int cros_typec_altmode_exit(struct typec_altmode= *alt) schedule_work(&adata->work); =20 mutex_unlock(&adata->lock); - return ret; + + return 0; } =20 static int cros_typec_displayport_vdm(struct typec_altmode *alt, u32 heade= r, @@ -254,9 +295,6 @@ static int cros_typec_altmode_vdm(struct typec_altmode = *alt, u32 header, { struct cros_typec_altmode_data *adata =3D typec_altmode_get_drvdata(alt); =20 - if (!adata->ap_mode_entry) - return -EOPNOTSUPP; - if (adata->sid =3D=3D USB_TYPEC_DP_SID) return cros_typec_displayport_vdm(alt, header, data, count); =20 --=20 https://chromeos.dev From nobody Fri Dec 19 19:15:52 2025 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D6A717A302 for ; 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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-22c33fe4de0sm1234335ad.212.2025.04.15.17.02.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:17 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Krzysztof Kozlowski , Lee Jones , Benson Leung , Guenter Roeck , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski , Krzysztof Kozlowski Subject: [PATCH 4/7] dt-bindings: Move google,cros-ec-typec binding to usb Date: Tue, 15 Apr 2025 17:02:04 -0700 Message-ID: <20250416000208.3568635-5-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This binding is about USB type-c control. Move the binding to the usb directory as it's a better home than chrome. Reviewed-by: Rob Herring (Arm) Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Lee Jones Cc: Benson Leung Cc: Guenter Roeck Cc: Tzung-Bi Shih Cc: Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Suggested-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd Acked-by: Lee Jones --- .../devicetree/bindings/mfd/google,cros-ec.yaml | 2 +- .../{chrome =3D> usb}/google,cros-ec-typec.yaml | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) rename Documentation/devicetree/bindings/{chrome =3D> usb}/google,cros-ec-= typec.yaml (72%) diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Do= cumentation/devicetree/bindings/mfd/google,cros-ec.yaml index 50f457090066..ac89696fa649 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -99,7 +99,7 @@ properties: gpio-controller: true =20 typec: - $ref: /schemas/chrome/google,cros-ec-typec.yaml# + $ref: /schemas/usb/google,cros-ec-typec.yaml# =20 ec-pwm: $ref: /schemas/pwm/google,cros-ec-pwm.yaml# diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.= yaml b/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml similarity index 72% rename from Documentation/devicetree/bindings/chrome/google,cros-ec-typec.y= aml rename to Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml index 9f9816fbecbc..3272d0e01f7e 100644 --- a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml +++ b/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml @@ -1,20 +1,20 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml# +$id: http://devicetree.org/schemas/usb/google,cros-ec-typec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Google Chrome OS EC(Embedded Controller) Type C port driver. +title: Google ChromeOS EC (Embedded Controller) USB Type-C Port Manager =20 maintainers: - Benson Leung - Prashant Malani =20 description: - Chrome OS devices have an Embedded Controller(EC) which has access to - Type C port state. This node is intended to allow the host to read and - control the Type C ports. The node for this device should be under a - cros-ec node like google,cros-ec-spi. + Chrome OS devices have an Embedded Controller (EC) which has access to + USB Type-C port state. This node is intended to allow the host to read a= nd + control the Type-C ports. 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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-22c33f1d392sm1327015ad.99.2025.04.15.17.02.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:19 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Krzysztof Kozlowski , Lee Jones , Benson Leung , Guenter Roeck , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 5/7] dt-bindings: usb: google,cros-ec-typec: Add ports for DP altmode Date: Tue, 15 Apr 2025 17:02:05 -0700 Message-ID: <20250416000208.3568635-6-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add a DT graph binding to google,cros-ec-typec so that it can combine DisplayPort (DP) and USB SuperSpeed (SS) data into a USB type-c endpoint that is connected to the usb-c-connector node's SS endpoint. Allow there to be multiple 'typec' nodes underneath the EC node so that one DT graph exists per DP bridge. The EC is actually controlling TCPCs and redrivers that combine the DP and USB signals together so this more accurately reflects the hardware design without introducing yet another DT node underneath the EC for USB type-c "stuff". If the type-c ports are being shared between a single DP controller then the ports need to know about each other and determine a policy to drive DP to one type-c port or the other. If the type-c ports each have their own dedicated DP controller then they're able to operate independently and enter/exit DP altmode independently as well. We can't connect the DP controller's endpoint to one usb-c-connector port@1 endpoint and the USB controller's endpoint to another usb-c-connector port@1 endpoint either because the DP muxing case would have DP connected to two usb-c-connector endpoints which the graph binding doesn't support. Therefore, one typec node is required per the capabilities of the type-c port(s) being managed. Add a port to the DisplayPort altmode as well, so that we can show the connection between the DP controller and the DP altmode. This lets us indicate which type-c ports the DP controller is wired to. For example, if DP was connected to ports 0 and 2, while port 1 was connected to another DP controller we wouldn't be able to implement that without having some other DT property to indicate which output ports are connected to the DP endpoint. Furthermore, this supports ChromeOS designs like Corsola where a DP controller/PHY is split with two lanes going to one connector and the other two lanes going to another connector. In this case, we wouldn't have the graph binding under the cros-ec-typec node, but we would have the graph binding in the DP altmode directly connected to the DP controller's two output endpoints. Cc: Rob Herring (Arm) Cc: Krzysztof Kozlowski Cc: Conor Dooley Acked-by: Lee Jones Cc: Benson Leung Cc: Guenter Roeck Cc: Tzung-Bi Shih Cc: Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd --- .../bindings/connector/usb-connector.yaml | 6 + .../bindings/mfd/google,cros-ec.yaml | 7 +- .../bindings/usb/google,cros-ec-typec.yaml | 165 ++++++++++++++++++ 3 files changed, 175 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml= b/Documentation/devicetree/bindings/connector/usb-connector.yaml index 11e40d225b9f..e3d60997c03e 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -179,6 +179,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: VDO returned by Discover Modes USB PD command. =20 + port: + $ref: /schemas/graph.yaml#/properties/port + description: OF graph bindings modeling a data bus to the + DisplayPort altmode from the DisplayPort controller. Used wh= en + the altmode switch is part of the port manager. + port: $ref: /schemas/graph.yaml#/properties/port description: OF graph bindings modeling a data bus to the connector, e= .g. diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Do= cumentation/devicetree/bindings/mfd/google,cros-ec.yaml index ac89696fa649..63d506e88abb 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -98,9 +98,6 @@ properties: =20 gpio-controller: true =20 - typec: - $ref: /schemas/usb/google,cros-ec-typec.yaml# - ec-pwm: $ref: /schemas/pwm/google,cros-ec-pwm.yaml# deprecated: true @@ -163,6 +160,10 @@ patternProperties: type: object $ref: /schemas/extcon/extcon-usbc-cros-ec.yaml# =20 + "^typec(-[0-9])*$": + type: object + $ref: /schemas/usb/google,cros-ec-typec.yaml# + required: - compatible =20 diff --git a/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yam= l b/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml index 3272d0e01f7e..611345bbe884 100644 --- a/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml +++ b/Documentation/devicetree/bindings/usb/google,cros-ec-typec.yaml @@ -26,6 +26,55 @@ properties: '#size-cells': const: 0 =20 + mux-gpios: + description: GPIOs indicating which way the DisplayPort mux is steered + minItems: 1 + maxItems: 3 + + no-hpd: + description: Indicates this device doesn't signal HPD for DisplayPort + type: boolean + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Port for DisplayPort (DP) data + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Input DP port + + patternProperties: + '^endpoint@[1-8]$': + $ref: /schemas/graph.yaml#/properties/endpoint + description: Output to the usb-c connector's DP altmode + + required: + - endpoint@0 + + anyOf: + - required: + - endpoint@1 + - required: + - endpoint@2 + - required: + - endpoint@3 + - required: + - endpoint@4 + - required: + - endpoint@5 + - required: + - endpoint@6 + - required: + - endpoint@7 + - required: + - endpoint@8 + patternProperties: '^connector@[0-9a-f]+$': $ref: /schemas/connector/usb-connector.yaml# @@ -35,10 +84,30 @@ patternProperties: required: - compatible =20 +allOf: + - if: + required: + - no-hpd + then: + properties: + ports: + required: + - port@0 + - if: + required: + - mux-gpios + then: + properties: + ports: + required: + - port@0 + additionalProperties: false =20 examples: - |+ + #include + spi { #address-cells =3D <1>; #size-cells =3D <0>; @@ -47,6 +116,8 @@ examples: compatible =3D "google,cros-ec-spi"; reg =3D <0>; interrupts =3D <35 0>; + #gpio-cells =3D <2>; + gpio-controller; =20 typec { compatible =3D "google,cros-ec-typec"; @@ -54,12 +125,106 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 + mux-gpios =3D <&cros_ec 42 GPIO_ACTIVE_HIGH>, <&cros_ec 3 GPIO_A= CTIVE_HIGH>; + connector@0 { compatible =3D "usb-c-connector"; reg =3D <0>; power-role =3D "dual"; data-role =3D "dual"; try-power-role =3D "source"; + + altmodes { + displayport { + port { + usbc0_dp: endpoint { + remote-endpoint =3D <&dp_out0>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_c0_hs: endpoint { + remote-endpoint =3D <&usb_hub_dfp3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + usb_c0_ss: endpoint { + remote-endpoint =3D <&usb_hub_dfp3_ss>; + }; + }; + }; + }; + + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + try-power-role =3D "source"; + + altmodes { + displayport { + port { + usbc1_dp: endpoint { + remote-endpoint =3D <&dp_out1>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_c1_hs: endpoint { + remote-endpoint =3D <&usb_hub_dfp2_hs>; + }; + }; + + port@1 { + reg =3D <1>; + usb_c1_ss: endpoint { + remote-endpoint =3D <&usb_hub_dfp2_ss>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dp_phy>; + }; + + dp_out0: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&usbc0_dp>; + }; + + dp_out1: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&usbc1_dp>; + }; + }; }; }; }; --=20 https://chromeos.dev From nobody Fri Dec 19 19:15:52 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DBDB1B4F0A for ; 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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-22c33f1d091sm1324475ad.61.2025.04.15.17.02.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:21 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Benson Leung , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 6/7] platform/chrome: cros_ec_typec: Add support for DP altmode via drm_bridge Date: Tue, 15 Apr 2025 17:02:06 -0700 Message-ID: <20250416000208.3568635-7-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Trogdor platforms, the USB DP altmode is entered and exited by the EC depending on if DP altmode is possible and if HPD is asserted for a port. Trogdor has two USB-C connectors but the AP only supports one DP controller, so the first USB-C connector to assert HPD "wins". The DP controller on the AP is fixed to output two lanes DP that goes to an analog mux that steers the DP lanes to one of the two USB-C connectors. The HPD state in the DP altmode is "captured" by the EC and redriven from a GPIO on the EC to the AP's GPIO that is muxed to the DisplayPort controller inside the AP SoC. This allows both HPD high/low and HPD IRQ to be signaled from the EC as well as making DP altmode possible on either USB-C connector except at the same time. Add a drm_bridge to the ChromeOS EC driver to represent this analog mux on Trogdor and teach the kernel that DP altmode is using this DP controller on the AP. When the DT node has a graph binding, we assume that we're muxing DP to one of many USB-C connectors and we terminate the bridge chain here. In almost all cases we want this bridge to be the one that signals HPD because the EC is the one managing HPD and redriving the GPIO, except for in the case that the DP altmode driver is enabled in which case HPD will be signaled with drm_bridge_connector_oob_hotplug_event(). Unfortunately Trogdor EC firmwares have a bug where HPD state isn't discoverable properly, so we skip signaling HPD in that case if the "no-hpd" property exists in the node. Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd --- drivers/platform/chrome/Kconfig | 1 + drivers/platform/chrome/cros_ec_typec.c | 50 +++++++++++++++++++++++++ drivers/platform/chrome/cros_ec_typec.h | 7 ++++ 3 files changed, 58 insertions(+) diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kcon= fig index 1b2f2bd09662..0ed8637b8853 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -247,6 +247,7 @@ config CROS_EC_TYPEC depends on MFD_CROS_EC_DEV && TYPEC depends on CROS_USBPD_NOTIFY depends on USB_ROLE_SWITCH + depends on DRM_BRIDGE default MFD_CROS_EC_DEV select CROS_EC_TYPEC_ALTMODES if TYPEC_DP_ALTMODE select CROS_EC_TYPEC_ALTMODES if TYPEC_TBT_ALTMODE diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index 2cbe29f08064..27324cf0c0c6 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,8 @@ #include #include =20 +#include + #include "cros_ec_typec.h" #include "cros_typec_vdm.h" #include "cros_typec_altmode.h" @@ -337,6 +340,9 @@ static int cros_typec_init_ports(struct cros_typec_data= *typec) u32 port_num =3D 0; =20 nports =3D device_get_child_node_count(dev); + /* Don't count any 'ports' child node */ + if (of_graph_is_present(dev->of_node)) + nports--; if (nports =3D=3D 0) { dev_err(dev, "No port entries found.\n"); return -ENODEV; @@ -350,6 +356,10 @@ static int cros_typec_init_ports(struct cros_typec_dat= a *typec) /* DT uses "reg" to specify port number. */ port_prop =3D dev->of_node ? "reg" : "port-number"; device_for_each_child_node(dev, fwnode) { + /* An OF graph isn't a connector */ + if (fwnode_name_eq(fwnode, "ports")) + continue; + if (fwnode_property_read_u32(fwnode, port_prop, &port_num)) { ret =3D -EINVAL; dev_err(dev, "No port-number for port, aborting.\n"); @@ -417,6 +427,42 @@ static int cros_typec_init_ports(struct cros_typec_dat= a *typec) return ret; } =20 +static int cros_typec_dp_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL; +} + +static const struct drm_bridge_funcs cros_typec_dp_bridge_funcs =3D { + .attach =3D cros_typec_dp_bridge_attach, +}; + +static int cros_typec_init_dp_bridge(struct cros_typec_data *typec) +{ + struct device *dev =3D typec->dev; + struct cros_typec_dp_bridge *dp_bridge; + struct drm_bridge *bridge; + struct device_node *np =3D dev->of_node; + + /* Not capable of DP altmode switching. Ignore. */ + if (!of_graph_is_present(np)) + return 0; + + dp_bridge =3D devm_kzalloc(dev, sizeof(*dp_bridge), GFP_KERNEL); + if (!dp_bridge) + return -ENOMEM; + typec->dp_bridge =3D dp_bridge; + + bridge =3D &dp_bridge->bridge; + bridge->funcs =3D &cros_typec_dp_bridge_funcs; + bridge->of_node =3D np; + bridge->type =3D DRM_MODE_CONNECTOR_DisplayPort; + if (!device_property_read_bool(dev, "no-hpd")) + bridge->ops |=3D DRM_BRIDGE_OP_HPD; + + return devm_drm_bridge_add(dev, bridge); +} + static int cros_typec_usb_safe_state(struct cros_typec_port *port) { int ret; @@ -1276,6 +1322,10 @@ static int cros_typec_probe(struct platform_device *= pdev) typec->num_ports =3D EC_USB_PD_MAX_PORTS; } =20 + ret =3D cros_typec_init_dp_bridge(typec); + if (ret < 0) + return ret; + ret =3D cros_typec_init_ports(typec); if (ret < 0) return ret; diff --git a/drivers/platform/chrome/cros_ec_typec.h b/drivers/platform/chr= ome/cros_ec_typec.h index 9fd5342bb0ad..090f8f5c0492 100644 --- a/drivers/platform/chrome/cros_ec_typec.h +++ b/drivers/platform/chrome/cros_ec_typec.h @@ -14,6 +14,8 @@ #include #include =20 +#include + /* Supported alt modes. */ enum { CROS_EC_ALTMODE_DP =3D 0, @@ -35,6 +37,7 @@ struct cros_typec_data { unsigned int pd_ctrl_ver; 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[34.125.24.199]) by smtp.gmail.com with UTF8SMTPSA id 41be03b00d2f7-b0b22217eebsm117742a12.67.2025.04.15.17.02.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 17:02:23 -0700 (PDT) From: Stephen Boyd To: Tzung-Bi Shih Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, Dmitry Baryshkov , Krzysztof Kozlowski , Rob Herring , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , Benson Leung , chrome-platform@lists.linux.dev, Pin-yen Lin , Abhishek Pandit-Subedi , =?UTF-8?q?=C5=81ukasz=20Bartosik?= , Jameson Thies , Andrei Kuchynski Subject: [PATCH 7/7] platform/chrome: cros_ec_typec: Support DP muxing Date: Tue, 15 Apr 2025 17:02:07 -0700 Message-ID: <20250416000208.3568635-8-swboyd@chromium.org> X-Mailer: git-send-email 2.49.0.604.gff1f9ca942-goog In-Reply-To: <20250416000208.3568635-1-swboyd@chromium.org> References: <20250416000208.3568635-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Most ARM based chromebooks with two usb-c-connector nodes and one DP controller are muxing the DP lanes between the two USB ports. This is done so that the type-c ports are at least equal in capability if not functionality. Either an analog mux is used to steer the DP signal to one or the other port, or a DP bridge chip has two lanes (e.g. DP ML0/ML1) wired to one type-c port while the other two (e.g. DP ML2/ML3) are wired to another type-c port. If a user connects a DP capable cable to both usb-c-connectors the EC likes to inform the AP that both ports have entered DP altmode, even though one of those ports can't actually display anything because the DP lanes aren't steered there. The answer to this problem is to look at the HPD bit in the EC messages. The port that isn't steered for DP won't ever see HPD be asserted, because the EC hides HPD state for the other port. This isn't a great solution though, because some EC firmwares don't even signal HPD state in the message at all. Oops! And it really does throw the whole type-c subsystem for a loop when the port has DP altmode present but it can't be entered properly. Let's fix these problems by doing two things. First, we'll only allow the port that's steered for DP to enter DP mode. Do that by checking the mux-gpios whenever we see that the EC tells us DP mode has been entered. If the mux isn't selecting this port, remove the flag from the message so that DP mode doesn't look to be entered. Second, inject HPD into the EC message when the EC has busted firmware. In this case, DT authors add 'no-hpd' to the typec node (essentially only on Trogdor). Listen for HPD events from the drm_bridge and read the mux when HPD is asserted to figure out which port actually had HPD asserted on it. When the port state is processed, check the bit against the port and if DP mode is entered, i.e. the mux is still steering toward that port, check if HPD is asserted on that port and inject HPD. This is necessary so that the typec framework can update the HPD state in sysfs, and eventually call drm_connector_oob_hotplug_event() from the DP altmode driver. Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Cc: Abhishek Pandit-Subedi Cc: =C5=81ukasz Bartosik Cc: Jameson Thies Cc: Andrei Kuchynski Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_ec_typec.c | 115 +++++++++++++++++++ drivers/platform/chrome/cros_ec_typec.h | 14 +++ drivers/platform/chrome/cros_typec_altmode.c | 2 + 3 files changed, 131 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index 27324cf0c0c6..10079129645d 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -427,6 +428,41 @@ static int cros_typec_init_ports(struct cros_typec_dat= a *typec) return ret; } =20 +static void cros_typec_dp_bridge_hpd_notify(struct drm_bridge *bridge, enu= m drm_connector_status status) +{ + struct cros_typec_dp_bridge *dp_bridge =3D bridge_to_cros_typec_dp_bridge= (bridge); + struct cros_typec_data *typec =3D dp_bridge->typec_data; + struct gpio_desc *mux_gpio =3D dp_bridge->mux_gpio; + int val; + DECLARE_BITMAP(orig, EC_USB_PD_MAX_PORTS); + DECLARE_BITMAP(changed, EC_USB_PD_MAX_PORTS); + + if (!mux_gpio) + return; + + /* This bridge signals HPD so it must be able to detect HPD properly */ + if (dp_bridge->bridge.ops & DRM_BRIDGE_OP_HPD) + return; + + bitmap_copy(orig, dp_bridge->hpd_asserted, EC_USB_PD_MAX_PORTS); + bitmap_zero(changed, EC_USB_PD_MAX_PORTS); + + if (status =3D=3D connector_status_connected) { + val =3D gpiod_get_value_cansleep(mux_gpio); + if (val < 0) { + dev_err(typec->dev, "Failed to read mux gpio\n"); + return; + } + __set_bit(val, changed); + } + + bitmap_copy(dp_bridge->hpd_asserted, changed, EC_USB_PD_MAX_PORTS); + + /* Refresh port state. */ + if (!bitmap_equal(orig, changed, EC_USB_PD_MAX_PORTS)) + schedule_work(&typec->port_work); +} + static int cros_typec_dp_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { @@ -435,6 +471,7 @@ static int cros_typec_dp_bridge_attach(struct drm_bridg= e *bridge, =20 static const struct drm_bridge_funcs cros_typec_dp_bridge_funcs =3D { .attach =3D cros_typec_dp_bridge_attach, + .hpd_notify =3D cros_typec_dp_bridge_hpd_notify, }; =20 static int cros_typec_init_dp_bridge(struct cros_typec_data *typec) @@ -452,6 +489,11 @@ static int cros_typec_init_dp_bridge(struct cros_typec= _data *typec) if (!dp_bridge) return -ENOMEM; typec->dp_bridge =3D dp_bridge; + dp_bridge->typec_data =3D typec; + + dp_bridge->mux_gpio =3D devm_gpiod_get_optional(dev, "mux", GPIOD_ASIS); + if (IS_ERR(dp_bridge->mux_gpio)) + return dev_err_probe(dev, PTR_ERR(dp_bridge->mux_gpio), "failed to get m= ux gpio\n"); =20 bridge =3D &dp_bridge->bridge; bridge->funcs =3D &cros_typec_dp_bridge_funcs; @@ -662,6 +704,77 @@ static int cros_typec_enable_usb4(struct cros_typec_da= ta *typec, return typec_mux_set(port->mux, &port->state); } =20 +/* + * Some ECs like to tell AP that both ports have DP enabled when that's + * impossible because the EC is muxing DP to one or the other port. Check = the + * mux on the EC in this case and ignore what the EC tells us about DP on = the + * port that isn't actually muxed for DP. + */ +void cros_typec_check_dp(struct cros_typec_data *typec, + struct ec_response_usb_pd_mux_info *resp, + struct cros_typec_port *port) +{ + struct cros_typec_dp_bridge *dp_bridge =3D typec->dp_bridge; + struct gpio_desc *mux_gpio; + int val; + + /* Never registered a drm_bridge. Skip. */ + if (!dp_bridge) + return; + + /* Don't need to override DP enabled when DP isn't enabled. */ + if (!(resp->flags & USB_PD_MUX_DP_ENABLED)) + return; + + mux_gpio =3D dp_bridge->mux_gpio; + /* EC mux is required to determine which port actually has DP on it. */ + if (!mux_gpio) + return; + + val =3D gpiod_get_value_cansleep(mux_gpio); + if (val < 0) { + dev_err(typec->dev, "Failed to read mux gpio\n"); + return; + } + + /* Only the muxed port can have DP enabled. Ignore. */ + if (val !=3D port->port_num) + resp->flags &=3D ~USB_PD_MUX_DP_ENABLED; +} + +/* + * Some ECs don't notify AP when HPD goes high or low because their firmwa= re is + * broken. Capture the state of HPD in cros_typec_dp_bridge_hpd_notify() a= nd + * inject the asserted state into the EC's response (deasserted is the + * default). + */ +static void cros_typec_inject_hpd(struct cros_typec_data *typec, + struct ec_response_usb_pd_mux_info *resp, + struct cros_typec_port *port) +{ + struct cros_typec_dp_bridge *dp_bridge =3D typec->dp_bridge; + + /* Never registered a drm_bridge. Skip. */ + if (!dp_bridge) + return; + + /* Don't need to inject HPD level when DP isn't enabled. */ + if (!(resp->flags & USB_PD_MUX_DP_ENABLED)) + return; + + /* This bridge signals HPD so it doesn't need to be reinjected */ + if (dp_bridge->bridge.ops & DRM_BRIDGE_OP_HPD) + return; + + /* + * The default setting is HPD deasserted. Ignore if nothing to inject. + */ + if (!test_bit(port->port_num, dp_bridge->hpd_asserted)) + return; + + resp->flags |=3D USB_PD_MUX_HPD_LVL; +} + static int cros_typec_configure_mux(struct cros_typec_data *typec, int por= t_num, struct ec_response_usb_pd_control_v2 *pd_ctrl) { @@ -682,6 +795,8 @@ static int cros_typec_configure_mux(struct cros_typec_d= ata *typec, int port_num, port_num, ret); return ret; } + cros_typec_check_dp(typec, &resp, port); + cros_typec_inject_hpd(typec, &resp, port); =20 /* No change needs to be made, let's exit early. */ if (port->mux_flags =3D=3D resp.flags && port->role =3D=3D pd_ctrl->role) diff --git a/drivers/platform/chrome/cros_ec_typec.h b/drivers/platform/chr= ome/cros_ec_typec.h index 090f8f5c0492..b4b331aa5dc7 100644 --- a/drivers/platform/chrome/cros_ec_typec.h +++ b/drivers/platform/chrome/cros_ec_typec.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,19 @@ struct cros_typec_port { =20 struct cros_typec_dp_bridge { struct drm_bridge bridge; + struct cros_typec_data *typec_data; + struct gpio_desc *mux_gpio; + DECLARE_BITMAP(hpd_asserted, EC_USB_PD_MAX_PORTS); }; =20 +static inline struct cros_typec_dp_bridge * +bridge_to_cros_typec_dp_bridge(struct drm_bridge *bridge) +{ + return container_of(bridge, struct cros_typec_dp_bridge, bridge); +} + +void cros_typec_check_dp(struct cros_typec_data *typec, + struct ec_response_usb_pd_mux_info *resp, + struct cros_typec_port *port); + #endif /* __CROS_EC_TYPEC__ */ diff --git a/drivers/platform/chrome/cros_typec_altmode.c b/drivers/platfor= m/chrome/cros_typec_altmode.c index 97ca4cfabbc0..10d21da592f1 100644 --- a/drivers/platform/chrome/cros_typec_altmode.c +++ b/drivers/platform/chrome/cros_typec_altmode.c @@ -82,6 +82,7 @@ static int cros_typec_altmode_enter(struct typec_altmode = *alt, u32 *vdo) if (ret < 0) return ret; =20 + cros_typec_check_dp(adata->port->typec_data, &resp, adata->port); if (!(resp.flags & flags)) return -EINVAL; } else { @@ -147,6 +148,7 @@ static int cros_typec_altmode_exit(struct typec_altmode= *alt) if (ret < 0) return ret; =20 + cros_typec_check_dp(adata->port->typec_data, &resp, adata->port); if (resp.flags & flags) return -EINVAL; } else { --=20 https://chromeos.dev