From nobody Mon Feb 9 23:15:40 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5DD0221577; Tue, 15 Apr 2025 17:29:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744738143; cv=none; b=S+HWq0yvbbYjkeMeWnoI+jqlvKfFUS73BNwLzIgmWBZh/lNpm7LhMUunJjQDwvH+cc3tQ4dV+xnfFe+HITKNlHVLIt0uVE9EqWfHgiUlgJCv2I3h+a1qI9+N/bCqXFeYiKcRdSQUppQq2HtP6DwJq2iw7X+4ehxOcpAHH6ctdds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744738143; c=relaxed/simple; bh=Him4JK+FJftB/n6P7c5Iyd2TEDiWgRHDCdeuF/oYQK0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TvaSvaNK4W+GfwMHEWY5UBc59fTgDssgStuNaCbo1hKBU+SnoYaktqQldpoEOb1pXagvH3zdIXc9Adp7hTiWFVNimTwm2tV04KmQxEfsHxu17KlJ8myJpnl9X0Z9GaszMGvsDBOtpiv2WX43sX/CAsbB09g40C5vQkqaafCCuQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MjP8f1/e; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MjP8f1/e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744738142; x=1776274142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Him4JK+FJftB/n6P7c5Iyd2TEDiWgRHDCdeuF/oYQK0=; b=MjP8f1/eS8efthlI9w+2FiojPeEjAt9E3DnwQt2pukoNnfSTzWEtQ2VW 7x9V8+2BHWlUWmTk+E9FJFSCgrBqIljLCEsvyNTQLfoiygsEugTpx3DjY TRiISuYiNU8Gi5xS6ElqweVj6rFqlLizn7Sap8d5a1eWltu+gcbYFljkE XG9xDswyC1LOiHXuLVCtCN0o4cPOiXCqptocKlGPoatwI7r0nsxb3qJQZ nr7DtVRwAdNH98raBPMkFjFrymuzaNDBqz/hQ+6BCfUUmdlkLXqZScusI D+LrAZSDXsnCV9k2L5l6b2r7+X38oINkYVIniSf7LJy+hAbUrfIzniOy/ A==; X-CSE-ConnectionGUID: r7sNgJ02SMe/JCCnQo8I3A== X-CSE-MsgGUID: n1J94QXQS4OYa30w+BCV9Q== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="46275620" X-IronPort-AV: E=Sophos;i="6.15,213,1739865600"; d="scan'208";a="46275620" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 10:29:02 -0700 X-CSE-ConnectionGUID: PfLsZR+lRWi6TF6nxdLEUQ== X-CSE-MsgGUID: /iM9akVTRKa82X5ywH23LQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,213,1739865600"; d="scan'208";a="130729635" Received: from newjersey.igk.intel.com ([10.102.20.203]) by fmviesa010.fm.intel.com with ESMTP; 15 Apr 2025 10:28:58 -0700 From: Alexander Lobakin To: intel-wired-lan@lists.osuosl.org Cc: Alexander Lobakin , Michal Kubiak , Maciej Fijalkowski , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Simon Horman , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-next 02/16] libeth: support native XDP and register memory model Date: Tue, 15 Apr 2025 19:28:11 +0200 Message-ID: <20250415172825.3731091-3-aleksander.lobakin@intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250415172825.3731091-1-aleksander.lobakin@intel.com> References: <20250415172825.3731091-1-aleksander.lobakin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expand libeth's Page Pool functionality by adding native XDP support. This means picking the appropriate headroom and DMA direction. Also, register all the created &page_pools as XDP memory models. A driver then can call xdp_rxq_info_attach_page_pool() when registering its RxQ info. Signed-off-by: Alexander Lobakin --- include/net/libeth/rx.h | 6 +++++- drivers/net/ethernet/intel/libeth/rx.c | 20 +++++++++++++++----- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/net/libeth/rx.h b/include/net/libeth/rx.h index 7d5dc58984b1..5d991404845e 100644 --- a/include/net/libeth/rx.h +++ b/include/net/libeth/rx.h @@ -13,8 +13,10 @@ =20 /* Space reserved in front of each frame */ #define LIBETH_SKB_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) +#define LIBETH_XDP_HEADROOM (ALIGN(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ + NET_IP_ALIGN) /* Maximum headroom for worst-case calculations */ -#define LIBETH_MAX_HEADROOM LIBETH_SKB_HEADROOM +#define LIBETH_MAX_HEADROOM LIBETH_XDP_HEADROOM /* Link layer / L2 overhead: Ethernet, 2 VLAN tags (C + S), FCS */ #define LIBETH_RX_LL_LEN (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN) /* Maximum supported L2-L4 header length */ @@ -66,6 +68,7 @@ enum libeth_fqe_type { * @count: number of descriptors/buffers the queue has * @type: type of the buffers this queue has * @hsplit: flag whether header split is enabled + * @xdp: flag indicating whether XDP is enabled * @buf_len: HW-writeable length per each buffer * @nid: ID of the closest NUMA node with memory */ @@ -81,6 +84,7 @@ struct libeth_fq { /* Cold fields */ enum libeth_fqe_type type:2; bool hsplit:1; + bool xdp:1; =20 u32 buf_len; int nid; diff --git a/drivers/net/ethernet/intel/libeth/rx.c b/drivers/net/ethernet/= intel/libeth/rx.c index aa5d878181f7..c0be9cb043a1 100644 --- a/drivers/net/ethernet/intel/libeth/rx.c +++ b/drivers/net/ethernet/intel/libeth/rx.c @@ -70,7 +70,7 @@ static u32 libeth_rx_hw_len_truesize(const struct page_po= ol_params *pp, static bool libeth_rx_page_pool_params(struct libeth_fq *fq, struct page_pool_params *pp) { - pp->offset =3D LIBETH_SKB_HEADROOM; + pp->offset =3D fq->xdp ? LIBETH_XDP_HEADROOM : LIBETH_SKB_HEADROOM; /* HW-writeable / syncable length per one page */ pp->max_len =3D LIBETH_RX_PAGE_LEN(pp->offset); =20 @@ -157,11 +157,12 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct = napi_struct *napi) .dev =3D napi->dev->dev.parent, .netdev =3D napi->dev, .napi =3D napi, - .dma_dir =3D DMA_FROM_DEVICE, }; struct libeth_fqe *fqes; struct page_pool *pool; - bool ret; + int ret; + + pp.dma_dir =3D fq->xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; =20 if (!fq->hsplit) ret =3D libeth_rx_page_pool_params(fq, &pp); @@ -175,18 +176,26 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct = napi_struct *napi) return PTR_ERR(pool); =20 fqes =3D kvcalloc_node(fq->count, sizeof(*fqes), GFP_KERNEL, fq->nid); - if (!fqes) + if (!fqes) { + ret =3D -ENOMEM; goto err_buf; + } + + ret =3D xdp_reg_page_pool(pool); + if (ret) + goto err_mem; =20 fq->fqes =3D fqes; fq->pp =3D pool; =20 return 0; =20 +err_mem: + kvfree(fqes); err_buf: page_pool_destroy(pool); =20 - return -ENOMEM; + return ret; } EXPORT_SYMBOL_GPL(libeth_rx_fq_create); =20 @@ -196,6 +205,7 @@ EXPORT_SYMBOL_GPL(libeth_rx_fq_create); */ void libeth_rx_fq_destroy(struct libeth_fq *fq) { + xdp_unreg_page_pool(fq->pp); kvfree(fq->fqes); page_pool_destroy(fq->pp); } --=20 2.49.0