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Tue, 15 Apr 2025 01:54:55 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:1883:aa4:a265:bc12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae9797aasm13616001f8f.56.2025.04.15.01.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 01:54:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3] soc: renesas: sysc: Add SoC identification for RZ/V2N SoC Date: Tue, 15 Apr 2025 09:54:38 +0100 Message-ID: <20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add SoC identification for the RZ/V2N SoC using the System Controller (SYS) block. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- Hi All, This patch is from series [0]. Since most of the patches have already been queued, I'm sending this one separately. [0] https://lore.kernel.org/all/20250407191628.323613-5-prabhakar.mahadev-l= ad.rj@bp.renesas.com/ Cheers, Prabhakar v2->v3: - Updated dev_info message to include the SoC revision and feature flags. - Dropped `` include. v1->v2: - No changes in the code. --- drivers/soc/renesas/Kconfig | 5 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a09g056-sys.c | 77 +++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.c | 3 ++ drivers/soc/renesas/rz-sysc.h | 1 + 5 files changed, 87 insertions(+) create mode 100644 drivers/soc/renesas/r9a09g056-sys.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index f02b8fe60e6b..fbc3b69d21a7 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -396,6 +396,7 @@ config ARCH_R9A09G047 config ARCH_R9A09G056 bool "ARM64 Platform support for RZ/V2N" default y if ARCH_RENESAS + select SYS_R9A09G056 help This enables support for the Renesas RZ/V2N SoC variants. =20 @@ -445,6 +446,10 @@ config SYS_R9A09G047 bool "Renesas RZ/G3E System controller support" if COMPILE_TEST select SYSC_RZ =20 +config SYS_R9A09G056 + bool "Renesas RZ/V2N System controller support" if COMPILE_TEST + select SYSC_RZ + config SYS_R9A09G057 bool "Renesas RZ/V2H System controller support" if COMPILE_TEST select SYSC_RZ diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 81d4c5726e4c..3bdcc6a395d5 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032) +=3D r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) +=3D r9a08g045-sysc.o obj-$(CONFIG_SYS_R9A09G047) +=3D r9a09g047-sys.o +obj-$(CONFIG_SYS_R9A09G056) +=3D r9a09g056-sys.o obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o =20 # Family diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a0= 9g056-sys.c new file mode 100644 index 000000000000..1b7185db929d --- /dev/null +++ b/drivers/soc/renesas/r9a09g056-sys.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2N System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +#define SYS_LSI_MODE_SEC_EN BIT(16) +/* + * BOOTPLLCA[1:0] + * [0,0] =3D> 1.1GHZ + * [0,1] =3D> 1.5GHZ + * [1,0] =3D> 1.6GHZ + * [1,1] =3D> 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +#define SYS_RZV2N_FEATURE_G31 BIT(0) +#define SYS_RZV2N_FEATURE_C55 BIT(1) +#define SYS_RZV2N_FEATURE_SEC BIT(2) + +static void rzv2n_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + unsigned int part_number; + u32 prr_val, mode_val; + u8 feature_flags; + + prr_val =3D readl(sysc_base + SYS_LSI_PRR); + mode_val =3D readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU, ISP and Cryptographic configuration */ + feature_flags =3D !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G3= 1 : 0; + feature_flags |=3D !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C= 55 : 0; + feature_flags |=3D (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_S= EC : 0; + + part_number =3D 41 + feature_flags; + + dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr-= >family, + soc_dev_attr->soc_id, part_number, soc_dev_attr->revision, feature_flag= s ? + " with" : "", feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)= " : "", + feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "", + feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) !=3D SYS_LSI_MODE_= CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __= initconst =3D { + .family =3D "RZ/V2N", + .id =3D 0x867d447, + .devid_offset =3D 0x304, + .revision_mask =3D GENMASK(31, 28), + .specific_id_mask =3D GENMASK(27, 0), + .print_id =3D rzv2n_sys_print_id, +}; + +const struct rz_sysc_init_data rzv2n_sys_init_data =3D { + .soc_id_init_data =3D &rzv2n_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 14db508f669f..ffa65fb4dade 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] =3D { #ifdef CONFIG_SYS_R9A09G047 { .compatible =3D "renesas,r9a09g047-sys", .data =3D &rzg3e_sys_init_data= }, #endif +#ifdef CONFIG_SYS_R9A09G056 + { .compatible =3D "renesas,r9a09g056-sys", .data =3D &rzv2n_sys_init_data= }, +#endif #ifdef CONFIG_SYS_R9A09G057 { .compatible =3D "renesas,r9a09g057-sys", .data =3D &rzv2h_sys_init_data= }, #endif diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index aa83948c5117..56bc047a1bff 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -42,5 +42,6 @@ struct rz_sysc_init_data { extern const struct rz_sysc_init_data rzg3e_sys_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; extern const struct rz_sysc_init_data rzv2h_sys_init_data; +extern const struct rz_sysc_init_data rzv2n_sys_init_data; =20 #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ --=20 2.49.0