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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Yanteng Si , Feiyang Chen , loongarch@lists.linux.dev, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Huacai Chen , Biao Dong , Baoqi Zhang Subject: [PATCH net-next 2/3] net: stmmac: dwmac-loongson: Add new multi-chan IP core support Date: Tue, 15 Apr 2025 15:11:27 +0800 Message-ID: <20250415071128.3774235-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250415071128.3774235-1-chenhuacai@loongson.cn> References: <20250415071128.3774235-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxGcS1Bv5ni3SCAA--.35528S4 X-CM-SenderInfo: hfkh0x5xdftxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj93XoW3WF1DGFWDtr43tryxCF47KFX_yoW7KFW3pr WfAFW2grWrWF4Yvan8J3yUZr15ArWYq39rXF42k340kF90yryjvFyrKFWYkrZ7CFZYyF42 vFykCr4kWF1UCFbCm3ZEXasCq-sJn29KB7ZKAUJUUUUf529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWr XwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8_gA5UUUUU== Content-Type: text/plain; charset="utf-8" Add a new multi-chan IP core (0x12) support which is used in Loongson- 2K3000/Loongson-3B6000M. Compared with the 0x10 core, the new 0x12 core reduces channel numbers from 8 to 4, but checksum is supported for all channels. Tested-by: Biao Dong Signed-off-by: Baoqi Zhang Signed-off-by: Huacai Chen Reviewed-by: Andrew Lunn --- .../ethernet/stmicro/stmmac/dwmac-loongson.c | 62 +++++++++++-------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-loongson.c index f5fdef56da2c..3f8949547f88 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c @@ -68,10 +68,11 @@ =20 #define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03 #define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13 -#define DWMAC_CORE_LS_MULTICHAN 0x10 /* Loongson custom ID */ -#define CHANNEL_NUM 8 +#define DWMAC_CORE_MULTICHAN_V1 0x10 /* Loongson custom ID 0x10 */ +#define DWMAC_CORE_MULTICHAN_V2 0x12 /* Loongson custom ID 0x12 */ =20 struct loongson_data { + u32 multichan; u32 loongson_id; struct device *dev; }; @@ -120,18 +121,29 @@ static void loongson_default_data(struct pci_dev *pde= v, plat->dma_cfg->pbl =3D 32; plat->dma_cfg->pblx8 =3D true; =20 - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) { - plat->rx_queues_to_use =3D CHANNEL_NUM; - plat->tx_queues_to_use =3D CHANNEL_NUM; + switch (ld->loongson_id) { + case DWMAC_CORE_MULTICHAN_V1: + ld->multichan =3D 1; + plat->rx_queues_to_use =3D 8; + plat->tx_queues_to_use =3D 8; =20 /* Only channel 0 supports checksum, * so turn off checksum to enable multiple channels. */ - for (i =3D 1; i < CHANNEL_NUM; i++) + for (i =3D 1; i < 8; i++) plat->tx_queues_cfg[i].coe_unsupported =3D 1; - } else { + + break; + case DWMAC_CORE_MULTICHAN_V2: + ld->multichan =3D 1; + plat->rx_queues_to_use =3D 4; + plat->tx_queues_to_use =3D 4; + break; + default: + ld->multichan =3D 0; plat->tx_queues_to_use =3D 1; plat->rx_queues_to_use =3D 1; + break; } } =20 @@ -329,14 +341,14 @@ static struct mac_device_info *loongson_dwmac_setup(v= oid *apriv) return NULL; =20 /* The Loongson GMAC and GNET devices are based on the DW GMAC - * v3.50a and v3.73a IP-cores. But the HW designers have changed the - * GMAC_VERSION.SNPSVER field to the custom 0x10 value on the - * network controllers with the multi-channels feature + * v3.50a and v3.73a IP-cores. But the HW designers have changed + * the GMAC_VERSION.SNPSVER field to the custom 0x10/0x12 value + * on the network controllers with the multi-channels feature * available to emphasize the differences: multiple DMA-channels, * AV feature and GMAC_INT_STATUS CSR flags layout. Get back the * original value so the correct HW-interface would be selected. */ - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) { + if (ld->multichan) { priv->synopsys_id =3D DWMAC_CORE_3_70; *dma =3D dwmac1000_dma_ops; dma->init_chan =3D loongson_dwmac_dma_init_channel; @@ -357,13 +369,13 @@ static struct mac_device_info *loongson_dwmac_setup(v= oid *apriv) if (mac->multicast_filter_bins) mac->mcast_bits_log2 =3D ilog2(mac->multicast_filter_bins); =20 - /* Loongson GMAC doesn't support the flow control. LS2K2000 - * GNET doesn't support the half-duplex link mode. + /* Loongson GMAC doesn't support the flow control. Loongson GNET + * without multi-channel doesn't support the half-duplex link mode. */ if (pdev->device =3D=3D PCI_DEVICE_ID_LOONGSON_GMAC) { mac->link.caps =3D MAC_10 | MAC_100 | MAC_1000; } else { - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) + if (ld->multichan) mac->link.caps =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; else @@ -392,9 +404,11 @@ static int loongson_dwmac_msi_config(struct pci_dev *p= dev, struct plat_stmmacenet_data *plat, struct stmmac_resources *res) { - int i, ret, vecs; + int i, ch_num, ret, vecs; + + ch_num =3D min(plat->tx_queues_to_use, plat->rx_queues_to_use); =20 - vecs =3D roundup_pow_of_two(CHANNEL_NUM * 2 + 1); + vecs =3D roundup_pow_of_two(ch_num * 2 + 1); ret =3D pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI); if (ret < 0) { dev_warn(&pdev->dev, "Failed to allocate MSI IRQs\n"); @@ -403,14 +417,12 @@ static int loongson_dwmac_msi_config(struct pci_dev *= pdev, =20 res->irq =3D pci_irq_vector(pdev, 0); =20 - for (i =3D 0; i < plat->rx_queues_to_use; i++) { - res->rx_irq[CHANNEL_NUM - 1 - i] =3D - pci_irq_vector(pdev, 1 + i * 2); + for (i =3D 0; i < ch_num; i++) { + res->rx_irq[ch_num - 1 - i] =3D pci_irq_vector(pdev, 1 + i * 2); } =20 - for (i =3D 0; i < plat->tx_queues_to_use; i++) { - res->tx_irq[CHANNEL_NUM - 1 - i] =3D - pci_irq_vector(pdev, 2 + i * 2); + for (i =3D 0; i < ch_num; i++) { + res->tx_irq[ch_num - 1 - i] =3D pci_irq_vector(pdev, 2 + i * 2); } =20 plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; @@ -572,7 +584,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, c= onst struct pci_device_id goto err_disable_device; =20 /* Use the common MAC IRQ if per-channel MSIs allocation failed */ - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) + if (ld->multichan) loongson_dwmac_msi_config(pdev, plat, &res); =20 ret =3D stmmac_dvr_probe(&pdev->dev, plat, &res); @@ -584,7 +596,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, c= onst struct pci_device_id err_plat_clear: if (dev_of_node(&pdev->dev)) loongson_dwmac_dt_clear(pdev, plat); - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) + if (ld->multichan) loongson_dwmac_msi_clear(pdev); err_disable_device: pci_disable_device(pdev); @@ -603,7 +615,7 @@ static void loongson_dwmac_remove(struct pci_dev *pdev) if (dev_of_node(&pdev->dev)) loongson_dwmac_dt_clear(pdev, priv->plat); =20 - if (ld->loongson_id =3D=3D DWMAC_CORE_LS_MULTICHAN) + if (ld->multichan) loongson_dwmac_msi_clear(pdev); =20 pci_disable_device(pdev); --=20 2.47.1