From nobody Fri Dec 19 17:36:41 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B186288CB1 for ; Tue, 15 Apr 2025 09:39:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709983; cv=none; b=EB+hChD0ZH8sZEUzMkaY1dp3lZkUfMqSupQ4K7Gb/NHeHSpqKHu9kIqgGrDBqwiEbXruAeQJ41vZnTa0wL3o/cvQx9pyKMRj2RL0Mm+vF/ZHfibLS3Uxwe84rD5PXOfCjA3ze+ZIuVGsxA1UoQPQxIHlq8pmwlehNsQvfn8ZELg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709983; c=relaxed/simple; bh=0Q7QbXFjOZLIKz45r8s6tdHPD3ihS77NgezOAW5kr0E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=omqn2UeiuNwDkSG0r4y5fC4Tmzj536hS+XHTYfNluUVtgy8TPxpIThhqPfX2iJgiDZUu9DG/snPhwcMtLnMfVT49DO7GY7TctEEbEOfBp5Wrel3k0w1JAV4ZeQDa3bqR5R83W9P3Sfdvhh+WRQUFZ3Xb9KBxEsAh9/CgM21A8AU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kL1zVUfr; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kL1zVUfr" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tH6h005264 for ; Tue, 15 Apr 2025 09:39:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= EMnI8sXQc6fcICVFpeOcXllxBiGB1u5ryoWnljhdAJU=; b=kL1zVUfr36rU/fJ7 gQxGIoxK1xzW6l9QfjImDxtZDsyxJ6w5NM/GwM6Icwwbw4LhjIFVSzg4tDEQxLzy ZInJzE86UNyLBVRJTnah6/HZuWd+ViBReweuRJZOabYyjkZFOO1xFNY+poe3vcpO NO2zWkoEyGSZTIIidN1E1frh9X4I4Xp2Tcspv1FpprnIH11Bx5WFIkTTHQAQ3vir lfNamnQhQp2WNBPiMKkVs0J8Sd1YB/hjs2Ar2sxYlyOfNnILoP1ns9ybhudgAcUE 57Uug6jGStzbjOAxVIjuQdF4wQAt+S+SEpPy7hhwVr40zENL+3oTEYUU2VUz6uIt hzzNXw== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yhbpqb65-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:40 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-47693206d3bso106273551cf.1 for ; Tue, 15 Apr 2025 02:39:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709979; x=1745314779; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EMnI8sXQc6fcICVFpeOcXllxBiGB1u5ryoWnljhdAJU=; b=FlJYtI7uapYQGGJdYHMoAngNbUPVphyyRtcxRoPAUIOWldckIO/L+9q4DXqqSdc+ya aD9MkJ2Z3Tl0LfnyrF2o3kklz987qMuOo935wAYV+f3mgilUdglnaP9eMSJcAlOjPwpA CyI24QYLYpyj6qFJOTmkdB+1wxH32IJIrAzxiRAn4fP1e209SoxyO0HHedtK0qgoJXEg W5KQVjEJW2p9X3NnCGiw7ClS6BWhvAB78YbhdZhW0sslwOFmS3+yWJaNZp47VXfl4+UI PMz+584Gd//wCiZzNnqNDI7kRvlT2RqsVZ8Mma8fcZRksuTamyB461hKDPHnX9zhZH8X 5p0Q== X-Forwarded-Encrypted: i=1; AJvYcCX4YxWyoUBsXX/QJj1M6N+D+cY3zKCE1O4FjVoW/OvCZv9yBgC9j44WBpbQfuDSsbyt9QchOxlxChC++tc=@vger.kernel.org X-Gm-Message-State: AOJu0YzKlLW6plzkV70aJPdZbSJLCTyZj3/Hl3Rjq7nkUF1XuRivHbVJ 2LPSY7lV/WBWfvzFnK0LShgKjvXd7nPTmLSL1Y6hhZ6b1EfqvlaOllaG/fawZbcwd/rrUqZMJQC TnnMaHRhW70QhC6up1vRW3gGg1toNip37fFmjRCgv6XjAnNubUVg4as6xs85i+cY= X-Gm-Gg: ASbGncuttHXYCmZyjOueeP9mn9JqGZbDw6IVg8nf9R91sxPZQSm1+K/vgiaTckR/lzC J5ZiKDYmgIxqaVFU/Dlzx2rK2oETGJ8at/H2r4v8V1Na+acOtQI53o0m+QygmkIJwunQJ8hQBo5 L3BOupeR9OF2Rt8JMyWbsb2khyMsLaiUmYAscSa3CYGyeuanjHVBmxrLmiMFTql8ddpbh0eeSbw 5Fin3VXdWW35pIMgNqW77D60U5NmB53WBllh9lmSOT3gDv/D2awthNcIP1W9y3kRvV4mX8YkLfk CegrPhXWqGg06gU8Cy9TDhKkKqbIvK5KiJqB621QE+HQVLHo/V5zEEIejfW9jGK5NA8qTzFIcf4 iBLchSMNuHBSsw91e7d1jdlvG X-Received: by 2002:a0c:aa05:0:b0:6f2:a457:197 with SMTP id 6a1803df08f44-6f2a4570302mr17557866d6.32.1744709979233; Tue, 15 Apr 2025 02:39:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8HQSOjLdhDHbjx7MvKXFQUeBcuAVyf9AOBVsTgsUZ5CPpSKyGS2MuHBbgjiijyBhmUGHLfg== X-Received: by 2002:a0c:aa05:0:b0:6f2:a457:197 with SMTP id 6a1803df08f44-6f2a4570302mr17557576d6.32.1744709978884; Tue, 15 Apr 2025 02:39:38 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:37 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:29 +0300 Subject: [PATCH v3 01/10] dt-bindings: display/msm: dp-controller: describe SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-1-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=950; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=t96ussCqWyIQAdmFD81iVPY1jwLXVD8SP3JFMa/Qjfw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilVM5htI38HvCqRt9nmZdp5w/Rq/WsUjy1Jg k4ECt/1uxWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVQAKCRCLPIo+Aiko 1S1RCACWIt1/w4yRBzi/5jbjFt1pJ+46EIYDCwGfet0spVeQ215ieyx4/27ucKQt9TBgzz+voDd TWRehj8HgLrW/C+JaCj96Seq6llg726XbHB+/sMhFDhstlhVb6yhJVnnlYsJGJREMxur9gvLHS9 dIOdBe0Ilk9x2Lbd1icTCOcOPaDGNSMSTJBi3hc+p85r7bNyeSqrrrt7cx8VH0IB6KaRxPVcEu7 HXtJE7m1KFrefpz7YjYN0I6A7zhWcfgQzFu7znRrImeQP9HjVUogsN7B1pUkd9ezpVB5j6bA51c KCXl7IM4ZOJN6IiHOIJHGfckVOJledcW2qqRlPyPd4SRN/zh X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: IvpsNeQd0CaaJoShrvpeVREdbjhxBX8E X-Proofpoint-GUID: IvpsNeQd0CaaJoShrvpeVREdbjhxBX8E X-Authority-Analysis: v=2.4 cv=I+plRMgg c=1 sm=1 tr=0 ts=67fe295c cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=qy0Ph95xh7xgto4wCWoA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=926 clxscore=1015 impostorscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Describe DisplayPort controller present on Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index e00b88332f2fed2fc33f6d72c5cc3d827cd7594e..246bbb509bea18bed32e3a442d0= 926a24498c960 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8650-dp - items: - enum: + - qcom,sar2130p-dp - qcom,sm6350-dp - qcom,sm8150-dp - qcom,sm8250-dp --=20 2.39.5 From nobody Fri Dec 19 17:36:41 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E124128936A for ; Tue, 15 Apr 2025 09:39:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709984; cv=none; b=lZbVJF5vUYUFtgCirD09KkeEUSwyOqJFRcuRZpLq1aFbhXfuC+99Tx1A8Zz5mL4d5MpJUG9v70vKzm7Ytd8A4u0ep6KBMRpo4YU+uPE+3UF4zCGnztZT3tBNVeh1VZgzd+FXTssn0l2//9Osn6Jnox3SwlLMuvHzhuGlCdaCQf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709984; c=relaxed/simple; bh=f5nEiMxpCpJ8tG4rxgWOSIOxABVTgec4J5cSa+ld9WA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t16pSUl/rQyJ1DQ/oESmnB/reOBEsHcZsxjb4JuVl7TnRjbX2ZuhUi5u2qxneA2NF5eNGQtCLGRWmbWDVxLzR0bC1RPDxXq+y0G0hKvUc9dvVZ+wAx0BLD99yYYDqd+sMQhqcNHZIE44ZJPS0jvZWtC38F8+NL6OsaZ09diwVK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=SB6nraEn; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="SB6nraEn" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tV8b002511 for ; Tue, 15 Apr 2025 09:39:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= EMjst29DNTaDM7RdBr29Vu4Zmfecm1OtVXRpr93QCUU=; b=SB6nraEnl5B3L6i3 XkVG35p0i6+ofgk9E7yggVrXfq0r9Olv7vhSl6sjdYC0ZCA7B1xixp2/xcMDlUEs PwUnsLqpRKCNrAiqwhUtbathZVEwNg4xmRrW4XaeI5UeJZikPC+7g8UMutqOEqL+ EnvQTtx64givPQ4YDie4CscAsv2pgVPRELlB8ZiTiBVR2Go1EKpSwMc97UJTXT+q SFiG0Agz+IIA9aEBoHebc3p1qK8k9GPDkWcwCkT6gEwX+5cUO71SnQ/RSoQHw695 sEtieM/DUJmqBhQUGGpi3aTwxd68nE4l0OYbuk9VixsoQZhWp0q3X5Ym+WmsqlBp yLuR0A== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45ygxjycch-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:41 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-6ed16cc6e39so90022226d6.1 for ; Tue, 15 Apr 2025 02:39:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709980; x=1745314780; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EMjst29DNTaDM7RdBr29Vu4Zmfecm1OtVXRpr93QCUU=; b=ahHtBolHM7Jj4rhzEKm9aqgaQgPfr0M8ogVU6yxjEc5HJde24ecKpecUasNnmzhRrp 4+c5m5QpDLZ5qitCB6ciUS1yNNedQSlrKXgfhZD5ugSuN2zmrUq6IGpTgEih/ta4z+Qq gXhJzoM+FGPXTmX0NAoO9IcO4LEx2JvNFS/TuV8UyeBatl94f9Y/gRMPQ+ulxnbWzUwn H5RrUaeF57cjuJiRQDelCM9Yftc7+1AqaKhZ+THnWl5Vx1GlOr1kcbQSW7c5ILl+MDGB 4cuRip4yNakFjFTVFuZaBe2HLCNjHqrXzV4ymMN6yfw/1ZFfBUNn2/NhYdEb3HouJP5C oN4w== X-Forwarded-Encrypted: i=1; AJvYcCUtzEjmX/OMMYFwAQ8HS0a5QMPfdS/k0Ovnt02uQbhoc3wCzUZB9XbKouaM87ccjkJuMocsrXuoAAoDSLw=@vger.kernel.org X-Gm-Message-State: AOJu0YwPeg8hsi8LxlvjxT2UqGgVlKnmRG7cqA9e+5IfwC2xtEa5ySlW YooruO8dZlk1w+hXEhgApasNzE9Rgy0zW9c64w/mme3KE/bVZrcd3s3ZbAa5ge+7Jp1jR78dtHi OB1qkIVBaCnSJ8gS/myLcC9WH1FeLowhFQRL2bIU6h8O+fNrxAwYHLGIgLPD1PSc= X-Gm-Gg: ASbGnctw5wpSu/aKyZ7fMa6ETVHc/C/QFlnFvZmeskH0vQ3xY96MfiVxgb6PVxjuFRX AK2LDQB7vcgMwoItFo38AeEJKdcX7a6jEkt5o9OL9KJvH6VRJ5GDcxh/uFr4Vj6Aite9B7jhRhb itkzpkiRPjnDXsk42ovCpmn6iFRmxEHFteYgH20CSJXW12maj/bh4DFyzzMjTD4Z0/7CO0phspU R5720VW3xWMQ+ZgPyfL1o5HbUHloRlLXq17wPE7wJYYsRXwk7JhAdy3+PTx/1PIOPy+nfKtEg7A aDTKLxXIzxjE8TU66jHjWAHKTmyx+AGG5MBhLedUip2KEd+0b2NsUYVUzOjwDFtHdawULiXHg74 tY081RX75VRx3KTlRIZbi7+/9 X-Received: by 2002:a05:6214:19c5:b0:6ee:b77c:7dbe with SMTP id 6a1803df08f44-6f230d27c21mr193434226d6.12.1744709980641; Tue, 15 Apr 2025 02:39:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQp2HjVEeO0ktbov4KZJe4bJnmpotAkHqTPZqWnlxP97B4y0MeVgdf+Bpf8V/w9ZAnpH3sOw== X-Received: by 2002:a05:6214:19c5:b0:6ee:b77c:7dbe with SMTP id 6a1803df08f44-6f230d27c21mr193433886d6.12.1744709980357; Tue, 15 Apr 2025 02:39:40 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:39 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:30 +0300 Subject: [PATCH v3 02/10] dt-bindings: display/msm: dsi-controller-main: describe SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-2-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1325; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=PNM3/R9939920NNRFa+kSPKtbONWgfGTtTNO9ijO+vE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilVrA3uEJ69v1dp520K7RYb5A0BSH4RNdJGh 6YpzIXJKguJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVQAKCRCLPIo+Aiko 1QQNB/46R21cEA9UsOBhj4cdENgoT+GeVGYBZ6fBavXGRXxth9LvnU1MtN5c7S5xOWGd35PypCf Ley8En0qAy9vAmGlD67vkSlMr+Om2vHCk5Kxt70R7aWAf6Y+cgc0jId/kpzTz6NP6h+8YQgQnej rff3dPK369Ff76/b7EpPBxWhAamZUdKBsrp0KHxaryppLO6veyz0/plFD7zT8NVlPGrdIBkxImv 557qYxNphcbJOfHkJnUmFlpa84lu40XmCGNAeq3zRzA/5OZf9JvwC0EGyr2TwpiuLYPPHeVBEk1 G9/qmCs2DRVsxt7TRcvid3UlGoRcF/WHOzqCcyARtgc8WmE8 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=WecMa1hX c=1 sm=1 tr=0 ts=67fe295d cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=93dKIss0COAcHyiF0SEA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: oit66fE_s-F_2u8U0UFzB7tuKKvF7STL X-Proofpoint-ORIG-GUID: oit66fE_s-F_2u8U0UFzB7tuKKvF7STL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 impostorscore=0 mlxlogscore=865 spamscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Describe MIPI DSI controller present on Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 2aab33cd0017cd4a0c915b7297bb3952e62561fa..a3e05e34bf14dd5802fc538ca8b= 69846384f8742 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -23,6 +23,7 @@ properties: - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl @@ -314,6 +315,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm845-dsi-ctrl --=20 2.39.5 From nobody Fri Dec 19 17:36:41 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72DC9288C88 for ; Tue, 15 Apr 2025 09:39:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709986; cv=none; b=FE4K37SDS4/o97vVPDmX9yhN4jEIFGUvG704a9IhCKTrr3k1UfEOi9sI5yZl8IUD6wBx7mb2q3BtgnuGntuk0UDcIybK9Rq/y8/33ug4kgS42AtpvM3/OX3E4FMbF8gxkFtWfY0xa8JB5WR4sJSrkILK75N4sHUkP2BhjhYGrWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709986; c=relaxed/simple; bh=RGg6LqJQHNLz/YdyIPSyHxFlnkDpez0kLY/KCeMZs7M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LLcNV3YDgmz+44i8yzHPbmtJcX25fjc7TY/Lwb0DyPDcW0uCmsd1FklZAhfET08ORhKXWLpEhzQl9Eqm1OAClPYrLMOpAIcT4Lq255eXWogbTcNyaJeJvkZ04ja664+uc5L5lhcD15IE/wx63nTHljYZrOt4Yqh79ZH6twU1cyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=k/IqUdzR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="k/IqUdzR" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tGru013127 for ; Tue, 15 Apr 2025 09:39:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /QbvJSKxnfDapkwl00/Ate2tQHcvUoOl5cDQeaEM+xs=; b=k/IqUdzRBucNQj92 R2oMofXUSvg68XqSvUpoLzeKhEkncj37fRhj7sxxT//9KzNeIettuvkUxeJbWAhp fdJjNj2HXxpls9vmuDQkZy2t6pBID1MAMU3GPI+sdTNiLGXnK3Bv01zlRd9uy6yR 4YZWkhKD5Y/7HxcIA5Bs2wddIVY5vA8gCr2nLxUDQyYEv6WcpM19N/W1MAE2OzLE kP3LvobnWGmInRCNGAwZVuwvEXT0KDAN7KStXKnT3/irwgp00WQDh7d93J2knVTQ KXKNbhFJslrB1yBKTxM7Dd6sGnRj48GgY5phhPhURKtEstJDk3TXGjfIY1iIvTnP pygfig== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45ygd6fgwa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:43 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-6f0e2d30ab4so94713686d6.1 for ; Tue, 15 Apr 2025 02:39:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709982; x=1745314782; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/QbvJSKxnfDapkwl00/Ate2tQHcvUoOl5cDQeaEM+xs=; b=TgcYLIcYlH0MzyzBe/DMCB58SLuh//oupl5rNBz2rluiZVBd8D7yPogIfHJxb6ym8d QcST6cdhp+wkIn5+AqMDAhH2Y2PtVTXNX0L7R6C0ElVSDJEz43LcUhsUYtkNDRqgJjcO 7jit2WYCakc/MyWVnE0zXMxxoxboSuYBy2FdUuR3n71V5fSZi9/OQjwuVk4FUiU7ow42 ha+QncdGkOC1mxbcHr0CW30rQJo3X9CIqtY16iXSOFNkVueDiuvB4N+RrVOTHEMyqzKb IUctN4UKEComkZ4KTsJc2cRAZhvOeqqV9MNEzW57cpAPUGhTmrZ0aNwtaeh+qZ0zW2/2 LRTg== X-Forwarded-Encrypted: i=1; AJvYcCVqKkTCvc5TP4HR/UNImRQtMj3J59DA1s6m7KNEDxHgUch+MRviHC9/4/TQ5A5OQnhJcxwE1JyL9PgRYis=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9SkwTPMvFw1inhafaTkAI/FBYGTJjCpjnvcgri+EDrM7y669I koucZ+4gPHo557KUt/p/NYtWgOoaU9p+06sBOsM3eMCpOG7CZ86w29CjNrx2fr7XdgHdue32dJL 1DKSSGn+r78va89nbN+jH4lLs/FmuuIAVKl3runBxWG/FYrLoe0sbIh9RJbmmt2M= X-Gm-Gg: ASbGncuPK8JPd/usMwwHQbQqKJTuJaZsugYSXkYWZTMscDnD3yKGZPk1MK9wDo/d5uy Ok4t+udtuegWtdEVvplngqRTF2I3+ldOvq9nV3NO8dn4R33UHlNLxx+9IDrGRjynYwTBcuIAJtA 8zCE90FdSVzdd6q7NMFWbu6sKBr3VZyGxsSq4jG//O/O4GvEgyDphmVEW955LtQxCWl6np/XCkT d27LRZonXD2ibOyLgozbZvdoop3fZTkF5t+rjSaY/9vr27cLfQe9WJCspD1+VosCgPupCCCVoJV gbyorXzhYoX+P5OvL1PQbi3HBL9buAOEcfZOBHltScW4ZGw7kUMAkv3YNI50z8jTEY/2Mb8eKgz H12fVCXQdJXhZpqBtSrhezOsZ X-Received: by 2002:ad4:5ca4:0:b0:6f0:e2d4:51fe with SMTP id 6a1803df08f44-6f230d950dfmr209919616d6.26.1744709982011; Tue, 15 Apr 2025 02:39:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFD83JrRkLeYEAhElysIxFYiO/qrqAOuHzc5Obfv6TO5nQKTCzkIT8H0zCFaFZ205TMR64XhQ== X-Received: by 2002:ad4:5ca4:0:b0:6f0:e2d4:51fe with SMTP id 6a1803df08f44-6f230d950dfmr209919446d6.26.1744709981708; Tue, 15 Apr 2025 02:39:41 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:40 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:31 +0300 Subject: [PATCH v3 03/10] dt-bindings: display/msm: dsi-phy-7nm: describe SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-3-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=939; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=azlck2n2u+qrgsVJ0BAEOEuqH2At8nKdcftYTsEljlc=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ/o/zTCVhoZqo+Bz7P3TL5bcP8LWqHb9WPmSzRN/6Mx8t JRtt11JJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmEq3B/t+n82fyAwOWZ0dv PQi/YfRnoaUis4BRVXovq1edzsmEqUVHTrdOvs16+XxRjd2kRFfpKnYrr3s/Sg5n8zE+vRt19kr emb2N7Hczpm7uPHs5a8Ozdt+nsWZnpopssj7n9ztevHnXqT+KM7bJHD9U4ZDceeCz3UZJxqhcY2 bfKZJHtx0J+unkeXSPm4/mvxRFo6DpBWrLlG7E39CzPrSUUffJtip2YckvRx9dFTl68ax/rjRj/ rITUXJcKVqJTgevc69s124x8WP8UtfY35m3NJmb+5v1HSOB9Wulv7/psJ691q+2W5pRoniGdIzb oQd2T3rNquoO2tobl3n9+WZ2iC+twMVggef195KsnoXcAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: WS_iVtFodwKxIvFzjs7W0UKh6qvz0zRF X-Proofpoint-GUID: WS_iVtFodwKxIvFzjs7W0UKh6qvz0zRF X-Authority-Analysis: v=2.4 cv=ANaQCy7k c=1 sm=1 tr=0 ts=67fe295f cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=5g6dqdCWcepBQtZB-T0A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=926 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Describe MIPI DSI PHY present on Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 321470435e654f1d569fc54f6a810e3f70fb168c..f79be422b8892484216b407f738= 5789764c2de1b 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 + - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm - qcom,sm6375-dsi-phy-7nm - qcom,sm8350-dsi-phy-5nm --=20 2.39.5 From nobody Fri Dec 19 17:36:41 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E51872853EB for ; Tue, 15 Apr 2025 09:39:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709988; cv=none; b=sNcOG8vGOg7zWpy6/EOjMbVD8WaY7x2RSALklek487I7hhj2VBI/zuBWr/NKDOQ4I3SvSl2Jfluz+ezPqr60OgYAPB0qQn7Hwxzxb7L4f/9NBjHQff3/CrlVeyhAbvabZE2YzMIdcmJuobLYhrqiyDOdpuVOzk6/qwdMXxQGEHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709988; c=relaxed/simple; bh=WwCvGbKN1UfpAvbEF24uDaZkMcpdSei4ppmMTFjiumY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fl2v/oDms8b1sE54fYL31nzSUc3JTYJSzSR3AP2EoA4y2hXQMWZ2fTJkjKsL9EjzN7hwoK3AIKDiEw7KzX0ZdlD5dzGzSBWm5xX+JLy5p5ffj14GPpp3ZaRG64QaAYxFFyfbu5/+II0p9jP0VumJxg0jNeaX+sD/3QrztLYkPYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Crry7EYQ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Crry7EYQ" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tH9P002235 for ; Tue, 15 Apr 2025 09:39:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= boXGEJ9vm7laFVs45kpF+i7DaEsEXFuWOHSJOklGi48=; b=Crry7EYQoQ7jclKC t2LkwXKWi3UGPmFyK4i1sqV1VOjGoUvZR9vAP0XeSwg8+YsbGEnENEbXIQRzeEV5 BMh9agY8PrayU9Uty3JzPLhIj7uokz0VvnQKnaOhxWj8mVMFkh1Iv321fTU4QF5s 4Il9Pf/tIFhmokJKlKT8DbTW0jLbGkb2/5GGH8+RTBfnuLWmlkALWogr79m0h4x9 wrPjuNzXSHfBXb6PDKc0qCqFmGlPz05aWQMCeobtH+OBbTDKFttO5zoNgnUWAmcB uFWyEZ+MWQ+cgVahOmCINpKvW/+oQS3bAWvAhTnwjRwcSR2Kmyd/g13CbXAT+a7w ML39aA== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yf4vfmbg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:44 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-6e91ee078aaso92050726d6.3 for ; Tue, 15 Apr 2025 02:39:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709983; x=1745314783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=boXGEJ9vm7laFVs45kpF+i7DaEsEXFuWOHSJOklGi48=; b=FiKLG5ijOls6uKDcqYuD1BK7okVc1J9h9nMKH0xxkSIGaptxE1uE/UsGS0hBiobOaa FJx8x17AfyI0dSOA/WVHMtK4LJtEznDv7UeZJF4d22Ar2tH6f8uh9g7pzXInIqfrEyc5 XZijrFAHJW+g0176rpzoUqK0mkCilNL9tSqBP3a+ryfe4ZH59PjZ++Htk6W8/jRl/dGP HvZbIUK6EBD/a28HXaNWQQLaRN5TpYBfQ5k+6Az9IQAdYrjLkaO7gAxg+zkYP+KUaJif XxYV35rWHzXTqi6rW3xMl2mqaBiRqoFNJ2XK0xrupx/CVGYzbAYHBsHQgk4+moA89GS2 i1Jg== X-Forwarded-Encrypted: i=1; AJvYcCUL4z/SABFtdLACLKuE7SAM6/+KiTRc8qqMs7uOY/sa99zbKUAT+kfxlhvHzt9QlDvEKWj3jTd541kucNU=@vger.kernel.org X-Gm-Message-State: AOJu0YzFU3Fs5lHz7fmK9uuqJg65hPmppwwD9LnTI4B0XxmAHiU0sgj4 igCdqe6wDEZSrP9tvYz19JUvcWt+gYpDRVGTIfFC8XjkiuQR4R8OHwvuBFQ0iAX/prJCut2RNMn YrsODrBo7wnU5pq+wNY95LUCtYR6f4bxFxFNuVa5KjpIhTfqpH9F7YPFQ9RXyiMQ= X-Gm-Gg: ASbGncvZD1NVV3wY/kamGgJqbcZ3CAk+eKHJ2h1bnrSApxqMlEMMcTMwQxtvXO3jYkU AJ8VBl7VWPcOKquDPP4XQkI4mLYnqqLPN4A/mYcWen4XpIMh17suFir0G6uHw4+RIeraYGXCpjr zHbC31ImIL2R36zYJ9AiFTS83cDcWCgfcvgiaFysIUk7xi1Lexk8N2ztrb1uAob11l/0KLcuuV/ gFOTUnfv3QzvSmtuesUNoerTiILkYyzsq+LoHXQALnXFV69qMFexGz40llz+fFqvjopywr2YuPv u1iT7zhIY2fWVX+XL4SqeqDXrD/rTmTspcIdjPBERtb6UYrvKGcMTrPBHNHmGaE7Dm7SnhDSSUy 7iez+HYSz9eMgP1kutdIPZ6KG X-Received: by 2002:a05:6214:cc6:b0:6e4:4011:9df7 with SMTP id 6a1803df08f44-6f230d1a647mr271627266d6.16.1744709983527; Tue, 15 Apr 2025 02:39:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHgv+l2YW7FLqgyNzvGDxI7BnqBldiXe67Jqf8Q0JmqBPbVtUaiY4utPWnf5VS4nhStjkZWOg== X-Received: by 2002:a05:6214:cc6:b0:6e4:4011:9df7 with SMTP id 6a1803df08f44-6f230d1a647mr271626936d6.16.1744709983180; Tue, 15 Apr 2025 02:39:43 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:42 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:32 +0300 Subject: [PATCH v3 04/10] dt-bindings: display/msm: qcom,sc7280-dpu: describe SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-4-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=934; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=IJ0quqH+dI7r+sJavUIADWzzAqD1L2X/CIVzw9kCDtE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilWDCo+pRdd0GrlabWfVcz8v6zf4ozWEeLZA /Fu3nJWwiGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVgAKCRCLPIo+Aiko 1ZCmB/9c4hLwLkqR989lkSnfX7RFd+RyXe2921PtOP8h3L7D9zPDDrRiPBsEIoM2IWDEgcRu29V TOK54ArIZFVtHuBzxHBrMKjeGTaEit0RHjeaueqX/uUaeFVZY3ZekNjO95YrhwBjDam3HZh5c3P KM6XNV83M1FHTLgDV4JtQyPebgUeMio3Rkb431dyZ450VyePsBt408lhO6oM08G1dvxgHIZ2kNH sGaQTCgD/TxOiRxM1flWQ2L1ost0uIylgYTY93Tavz3lOMs7y5XPP72eGnK6y80sGhBIcEll8cb FXyLoKPZm5mLpXx4et9YY0hagzeFfwiWKhu7H5nZHb7ecY2x X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: VaS9zd-Zsh42bxJWn8cT2iL8XiZc2sht X-Authority-Analysis: v=2.4 cv=IZ6HWXqa c=1 sm=1 tr=0 ts=67fe2960 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=P0d4iQPpJQof_2lRNe4A:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: VaS9zd-Zsh42bxJWn8cT2iL8XiZc2sht X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 mlxlogscore=914 mlxscore=0 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150065 From: Dmitry Baryshkov Describe DPU controller present on Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 6902795b4e2c249c2b543c1c5350f739a30553f2..df9ec15ad6c3ca1f77bebaab19f= fa3adb985733d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sar2130p-dpu - qcom,sc7280-dpu - qcom,sc8280xp-dpu - qcom,sm8350-dpu --=20 2.39.5 From nobody Fri Dec 19 17:36:41 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53C3A28DEF5 for ; Tue, 15 Apr 2025 09:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709989; cv=none; b=lIrhqYcmIKKEp5nJz+iqDsb8aiGVxPiKnPRboaaWWeq81j9OUL9hDq3A9xFSEDnDEOhG/8BBAf/wG8QwlpFzfqNlYLIqmwLW32yybvxm+VjnkyXYDYZnExiJUlGFW+Zcjq5dY5b7KkU0NUeGLA20ckzNYUg1oCUD9IhtlZwn4P0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709989; c=relaxed/simple; bh=X2svwOm76ptx+3+e2+/b8ojkomLzNMh7cQq7eEhIUIY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oJuiEhz4rN0unKVQmXt9IT0pPqbH97kfgYukqBvhLu2FhA2YeeQ3F0uXoSMNXAcUygH0pGVBWN2VRXIVDTvednLLFWJTgqv5WBM2N3URd4ZXnJypModuAGhQ2ldK/VzTKvpNgK4l1T8O8BI2jQQSiywhb8+Eb0hPElUWd1L+nuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FHWMXvAy; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FHWMXvAy" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tCXn022962 for ; Tue, 15 Apr 2025 09:39:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rJTrLJsWBAygM6/+ONh0vr3tYiSRbueh43nL89KqoeI=; b=FHWMXvAycthToF4u kWY3LkZlw4lL71qNYa8J3bB0TCyDe0UWCU5Xpm6GmmMapstGAjkvM4byIIpEZGTR BfTYPBep0LJz8qsfaOmwhOMGrIKvGBHVf+Cmfvlq4KTtxHVJoKJtgE2MSnZxJGCQ DROHDTFGRsdPAH+zwLjWGt6lNJPQoGdcydcmW/NaBuF4DCrK1fBBKxqMfJYYnxhr 1i6mJAIT92n2kWzPFbQ1Xq8SUfr2FWfR9ba/IymhSWJ5J1SQIRjRWZitK/snIyNC POSxR84AhIvOdtpNRYaEFyAgGsHqusZ1pHCitPvd6TpuwSUBg8Zkt5guLnIKqWKv quCj8A== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45ygj97gkw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:46 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-7c543ab40d3so787622085a.2 for ; Tue, 15 Apr 2025 02:39:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709985; x=1745314785; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rJTrLJsWBAygM6/+ONh0vr3tYiSRbueh43nL89KqoeI=; b=eX694eIdm6Ek67WUBenqWtyf4DkmZ8clWksuyhKxu2Fu/QnHVtqPXMncRFBE55XXJz kj44EQtZh9+3eJxpiZKQkAuFTL5uQCqyNJSqTJK/NbgsXRy1pT7EI5RSqUJMzyzF5o46 pbqJmGQt4pRpjORDR91PaT/Vfm89yGnl+rU8i+YClzOp6nQ5QFuarfTWyx6Aa0H/9Trs DpsqoPxVGMLQdDbC+KeP65+EKK5YcpVFGrNjzyj4mDNZc6s1du6gqbT2Bppcis7ijCqy RK362hiERx0rP/N/whKpvG/gdkCz2y3fbEUv+bMm87ndj4+3nO8Qj4ZkBQy12YI/yt/c vd7g== X-Forwarded-Encrypted: i=1; AJvYcCWD5TWskxjXNGC3sQ3qeGSv7inAqwDg3YdL1rT4h0vgRdNs/9t6AcHfFa1tO1Fs00QtV5/92bUccraY6Zk=@vger.kernel.org X-Gm-Message-State: AOJu0YxKHozwKbPxJgoubZdmnqm+jEbR7gcFZRUqHbkII6yO3qh3WDsp 4u0W5WEj6x75G3ufpkPoHx0/W7nei/x3XnSB5mruZ0MZjFThg17xt1mJ1U7jI+0mcsxkaXuXG94 rodFc92X1RzjfsL9vPijUuLHES2WadxTgTS1/5mdIr8u45TfGDCtLmHd7uKcFmhc= X-Gm-Gg: ASbGncsO2zJlA8UewcJLfc9+rnGr4N9lAm9UbhmMDQAduOKjWyAFE/+2JzdMDJpZI/G jCwUWq8oqY4e5EZMl5tSZ72butMJfAMHugXKD72TIf5zmeB4AYnriDFbUFFPM8IITsmAaW4o7cH a6SLkREirtcM0Uxiq4vrEoxapzhOunksHRWCrwUsf6OkVXrfX3eRpOWQhlXc8tnWYGnHk+krqq1 vC2jrFydw/NuvyYvMmLEFjh4a/FIdph3ETrlluO1MQu6jSqlA3lKVEm5ZuHgKP148CTGo5migK+ kyv1pEevb25o6xUwk6uh1eg3Ok2opP1QJEGDx7iHVeV6Ti3SSbGhHgLJuzUYZTpWEZWA1VEtsIx aLBKNHAdalj6EeMrYMSFK3T0n X-Received: by 2002:a05:620a:1a91:b0:7c7:a5e6:d287 with SMTP id af79cd13be357-7c7af12a31bmr2168953985a.52.1744709985184; Tue, 15 Apr 2025 02:39:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+dYTWo9NYCDq3k17wFUFhLrpxoNnBz9sk5MqXgGK080OnZZQwUk2cwHjT0c+469o/ZTllyw== X-Received: by 2002:a05:620a:1a91:b0:7c7:a5e6:d287 with SMTP id af79cd13be357-7c7af12a31bmr2168949285a.52.1744709984659; Tue, 15 Apr 2025 02:39:44 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:43 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:33 +0300 Subject: [PATCH v3 05/10] dt-bindings: display/msm: Add Qualcomm SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-5-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14907; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=mhVUBuasCeOBkqrxG/5PgGqIfKxDHldHx8QOIkjyyg4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilWyB0IH9WLeMZ1SByTf6u7l9X6VjEuWoE8Q NzEJ/hDC2CJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVgAKCRCLPIo+Aiko 1UG2CACaO97KCWNDtuqr6tHOQ/0z9XkUjF2P4XS/sPWkkj+J63jbAPxPbptDrcTnnxAwZDkYIsY y1nlnoKH2FDFqsT16WKYjkJGNt0E2JnablySPz5vA7u6dJZrUloEsyLmrijQdS5VihXVdbeIltV mJeUBdMxiQ9dzlSCzv3IT/ePJrsxuSZbBTmjp5otVw8ZXIji7nZdXeJNJKB80njRQ3PQhxZ1Zv+ jnHIB6KiW2YHW9YZ/qD/1wsFh0wyGvmVGtYxOhhKNxhacZMafF/KZwSRimqcdhIaA1/8oUmdVL7 oqeb9gR3DO8dibbd+uOUc/xNAy/4l3AawYG+ZFXxCc1Xsu04 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: D6DFROABeAt7AemlQFS61JKU9Ac7DvkG X-Authority-Analysis: v=2.4 cv=PruTbxM3 c=1 sm=1 tr=0 ts=67fe2962 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=-YBHemuPtO_JcOlGpNkA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: D6DFROABeAt7AemlQFS61JKU9Ac7DvkG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Describe the Mobile Display SubSystem (MDSS) device present on the Qualcomm SAR2130P platform. It looks pretty close to SM8550 on the system level. SAR2130P features two DSI hosts and single DisplayPort controller. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 439 +++++++++++++++++= ++++ 1 file changed, 439 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..870144b53cec9d3e0892276e14b= 49b745d021879 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -0,0 +1,439 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SAR2130P Display MDSS + +maintainers: + - Dmitry Baryshkov + +description: + SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-bloc= ks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dsi-phy-5nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sar2130p-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc_master_mdp &mc_virt_slave_ebi1>, + <&gem_noc_master_appss_proc &config_noc_slave_disp= lay_cfg>; + interconnect-names =3D "mdp0-mem", "cpu-cfg"; + + resets =3D <&dispcc_disp_cc_mdss_core_bcr>; + + power-domains =3D <&dispcc_mdss_gdsc>; + + clocks =3D <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sar2130p-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_mdp_lut_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>, + <&dispcc_disp_cc_mdss_vsync_clk>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc_disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible =3D "qcom,sar2130p-dp", + "qcom,sm8350-dp"; + reg =3D <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + clocks =3D <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_dptx0_aux_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK= _CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DI= V_CLK>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dp0_out: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc_disp_cc_mdss_byte0_clk>, + <&dispcc_disp_cc_mdss_byte0_intf_clk>, + <&dispcc_disp_cc_mdss_pclk0_clk>, + <&dispcc_disp_cc_mdss_esc0_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc_disp_cc_mdss_byte0_clk_src>, + <&dispcc_disp_cc_mdss_pclk0_clk_src>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sar2130p-dsi-phy-5nm"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names =3D "iface", "ref"; + }; + + dsi@ae96000 { + compatible =3D "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc_disp_cc_mdss_byte1_clk>, + <&dispcc_disp_cc_mdss_byte1_intf_clk>, + <&dispcc_disp_cc_mdss_pclk1_clk>, + <&dispcc_disp_cc_mdss_esc1_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc_disp_cc_mdss_byte1_clk_src>, + <&dispcc_disp_cc_mdss_pclk1_clk_src>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sar2130p-dsi-phy-5nm"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.39.5 From nobody Fri Dec 19 17:36:42 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD82C28DF07 for ; Tue, 15 Apr 2025 09:39:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709990; cv=none; b=DpbQTzEm63+z9d57hK5U+w7at5kCb1tMm39r016Tj8AV0vxQC3CDTj5rQmZhbFQJ1epQ6DYJX7BUw4uTJIKD8SRoGXmXIwD/9dJfHuZc71BY/PJdrCvQr/on1AxQ4pN5164ngDYY1nPCuzs7qQG14XZnKXQL1xg7+cbjBtFw7xY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709990; c=relaxed/simple; bh=lQQh8ylJrHtWLQoXqKNrrnmkQhqGnX3390KtwvC0ink=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CRyOP+XuSHzbwaqvQxIpSoiQUvNfMFKqRk8fsx8WFlUR+mfYpRyU0bsqRqwoPCjtm3n4JbcuwI6EuTTOrHWHzxnbmHZbjaDQBXctKzRfAeiNV/uCeNr2oMIeJua2j1uQYgLUoh6zGOGrunDGzg/s3AVf1dhsjSPULPJPB+Gxmoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VEKy+Dij; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VEKy+Dij" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tIxF031773 for ; Tue, 15 Apr 2025 09:39:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= f9AgmbDCtg5twjkdaU8ecsDLSo+5QAUYUantq6/JrfI=; b=VEKy+Dijiq3D2HS9 CttI6+q/ldNvecUyGFgk+PBDZd+y1COnsv091oUDpau4C70e4fnZyfbm47wUfPRb 5nqukibWXYS8Ak/Ok6BuKz/PusuXH8vX32lNBK9J45KoY9WPx+1fIuiz+usA0B+W +sGsuE1kXRfhGo2oEVDT/iEYNmaFeUXtb8xR6ct8rw7qxFuU2RufPOH4v5uDEeLC Rx8t7Yo2f2TE096mF7X4OF34zfNhHSlb38eVL4lVhR2shNf4lo5mjuPjueSD5Dh3 Bvju9vlAPU9wR+4z05sT3D7Yg7Z73KV1zjthK8mGqN0xUSBHTIBiqK4WfMc4WlRh varBSA== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yfs17j0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:47 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-7c54e7922a1so1084892385a.2 for ; Tue, 15 Apr 2025 02:39:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709987; x=1745314787; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f9AgmbDCtg5twjkdaU8ecsDLSo+5QAUYUantq6/JrfI=; b=DlVtvG2WT2AwDncTiOudkdFcFqGCbLcwnlS8YtrzQRHcgk1mDekFVcz+OcoG0c89jq Qda7CYbpniLp8HQ+1GxRdqrYIxNkboxtCIZNaNj9Anci8I4IIbIilRpuJVxxNAhe35f0 y+r1HhCck0nd/1GndTSVz42PkmxEwQVRgY2OhmVHNeTxrkIJJXDB8Xq8RuWsMSwooDlb a0g/V/etdNXtgTummk6m9rRDZ9ly01aR2oW+ECqdnkVvhik/zIPXBM12rXkxXKqIOKfz 7ZOH7Y9QsqkdNuNsRqPitIU9647pnG1cKjsU1DraQrxldq+3+eyNTTiRlqlsUJLlzzeY urtA== X-Forwarded-Encrypted: i=1; AJvYcCXKWKoPZ5EaRUgFUgC/W9t9sRcg2HNxNr6+18rtYyr6qUv5+kvb0cpOJgbQlmJtUXlLOC0SRMaIiPBmGXo=@vger.kernel.org X-Gm-Message-State: AOJu0YwXEYdHvAQUBdmZaD7Kr42Q313xQGniUBdwAkckWg1DwVAlIbFg nHXqRMDBLYjgDN3lYAx7iWu8sVhqJ9Xxq4CcHD0cX9d8nz6ISLNs8fiA2zRFRaqZyNRnmHkoEsu LS+8n0ku1aLb7Mk/cJSZDb6NF+PPO2gnvOerDSOPWLUrLP3MbtTae/EXofH1sbUU= X-Gm-Gg: ASbGnctyk1fpXgTJnL/yGciJnnhpWjgLWisbiYwxaYHbKAhZu0a6MhawsEqzgowcLoI ULlSBIBXWvVCMWoB6lPP7b3RN1bk7eKJqro1eTHc1eB6aO9MvHOdg8LuaLWtIsguDATybOdXHWl UaiLgsxD56wygKnPIX+NOLEtG+qvdlMO33CmqApKzTITVJl/WbH6/JsfUTQ1MWHUFjTVHG7urpz v64NJGMQcMz35skHKXXqPemTcETze0GkIxCtvmpUuuviyVQ65U9T2yFP9G0ILucp0HIK45hgBhB qNPn4Ur040b9a+R3P8YRzElGpF7Bh8TjaZiVjsFBpdcJ8RcCQh7CVq0JCAOqaEOdMj2sJrpoq// QxYfMBAT9hr64uaQK/2En46Wy X-Received: by 2002:a05:620a:811c:b0:7c7:bbc9:aba0 with SMTP id af79cd13be357-7c7bbc9abbemr966509285a.35.1744709986959; Tue, 15 Apr 2025 02:39:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFNnFLA5vT9LBSCJYCI3wYTMJxns+5i+5nNMjNTaaqHqu7WIdEd0lcCu19hVoYSlOsP/K6bQg== X-Received: by 2002:a05:620a:811c:b0:7c7:bbc9:aba0 with SMTP id af79cd13be357-7c7bbc9abbemr966507185a.35.1744709986634; Tue, 15 Apr 2025 02:39:46 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:45 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:34 +0300 Subject: [PATCH v3 06/10] drm/msm/mdss: add SAR2130P device configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-6-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1520; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=/w/74iYrKtAn6Ezwjelu2gFTZwiy2nDMAwTnc7sQiaY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilWDQOXj32DrIB5f1c8i1fbFrhMbXUgwFwuJ rK+IaXWOZGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVgAKCRCLPIo+Aiko 1VumB/93BM4l4rNb1vaPru2JaZuDFAsHysckNuR6nbScwRoFXGKP3DshlAILzwors9FN9+qfY3I FPMgJHcrKuzX7MfYGB37yKDkW84JsFXofe177vif7emU+yNciQcpFCt2OMLEC4YicOKMg/YwRLR JKkTp1+cbbuZyyTjX83GT332xV0oVphd3hdH+mBpR1yO/kOf8ngxeKlkxLes3AwPo9UYoODfly8 2OYFQBakGA8BC2JN5bg0t2E/i6gkbgNB793qiSr/CvSn6sZLdWYpODgNu4P2C3BPyYB8535ahbb HGAKYIM52l/E67bm+FTgxudqZ8MMZZMjz+R1o4U01fhNfCYx X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=P9I6hjAu c=1 sm=1 tr=0 ts=67fe2963 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=Zo32ic80xGYl86IK4a4A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: fifIc0lhe4fa9j1URvIrspd6iYFJhkxH X-Proofpoint-ORIG-GUID: fifIc0lhe4fa9j1URvIrspd6iYFJhkxH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Add compatible and device configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index dcb49fd30402b80edd2cb5971f95a78eaad6081f..f706e44231a9c360ac4abe26e40= 50e416d8c3940 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -592,6 +592,16 @@ static const struct msm_mdss_data sa8775p_data =3D { .reg_bus_bw =3D 74000, }; =20 +static const struct msm_mdss_data sar2130p_data =3D { + .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 0, + .macrotile_mode =3D 1, + .reg_bus_bw =3D 74000, +}; + static const struct msm_mdss_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, @@ -738,6 +748,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &qcm2290_data }, { .compatible =3D "qcom,sa8775p-mdss", .data =3D &sa8775p_data }, + { .compatible =3D "qcom,sar2130p-mdss", .data =3D &sar2130p_data }, { .compatible =3D "qcom,sdm670-mdss", .data =3D &sdm670_data }, { .compatible =3D "qcom,sdm845-mdss", .data =3D &sdm845_data }, { .compatible =3D "qcom,sc7180-mdss", .data =3D &sc7180_data }, --=20 2.39.5 From nobody Fri Dec 19 17:36:42 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58A9528F522 for ; Tue, 15 Apr 2025 09:39:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709993; cv=none; b=TuHFGAmfg1LYOrqPhZ+PwboGdmSNnjyggX1dmwuubP629uqzAKl4/onTHXpHnT8wYsUjKYxrs3R3T9cTXyvqDQHFUnmTATi6Ivyy1xBIpGl7erb70vRzxCEXpEr90Tuv6m0GHUsePo/yf+ZJQuOdRq9avwyleAKupwKO/3qCjx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709993; c=relaxed/simple; bh=uyn6rjWTDHITUowJs0zdqs419FlfeMOd6EA+lSArPGs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=anZB+I+3/6gVUpJw84LUSf/1COV5iTsKmKnVC0owD9prwuWH+OO9rvuDyTXGJAy6gM4T5T8PdsrOyBi7u5fCEbicrzKL7d34oKATggfVZ78FDpHF4iJ89+0INKm1LH1yj2s+unH65/qNp+QeS3O24tojsPPx+vWBhGxxzWnpPdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GxPMCufq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GxPMCufq" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tODW023401 for ; Tue, 15 Apr 2025 09:39:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= YjXjlNJQjaowHbkG3YqM6O2XdQTkytP/jZ3dM3LDh3o=; b=GxPMCufqNj1yNkQL rqcaw+cuLilECb62T0LZOrN/kBBE7h+mmoGkFDmM6rJJDMTbJ2cNnHCR8iCFNMgn eCNmzHY6htQ1tjDaOVyTdJ+QeqLaowwJEXREwEe226o24czNnh+CjR1bl5UikSm8 X8pe61YJyS685xEd40xRgFQEyOVmtzaCuvnSTZWVz+3YRYq0V+bc4/bVKyEFr5QY TCFalDrGaqj0wPJErN+jsueAXu8hcrFT9BMl60878CtrySsZVnzEGeSGh4fbOr4u xuPc0KJURnFGJZ7lqgA48abnkPvDZopAe98r2w1oSGe8NhHTYByuOs/7E6v3gwHE doKwzw== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45ygj97gmj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:49 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-7c5750ca8b2so804877085a.0 for ; Tue, 15 Apr 2025 02:39:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709989; x=1745314789; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YjXjlNJQjaowHbkG3YqM6O2XdQTkytP/jZ3dM3LDh3o=; b=EIS/DOuzsfMuU58amSx5zokyZDFz6xOLVoY1aiY72mxjVhObHnVAFpIGofyaLBFgQa 0VtOhjz99lCMtuJUWY2rOxp/Eqwk6isovZ9BztsnbraWrrRQAJTJFcJ2rsrfO1cV7Xll e97qdc+3MyTehwM6xpVDb7Ska2cqN6C9dSg2jzfBWp4xd7B0cgaCAAtz1vaVwEGU1UjV oaoGkx8htuAYwz2G/u41YGFsmdXskLfqPcuXNjZMLLTo13CdYuTyb+6/yY1SPb512mge jyNxggJ0N3BpXV4mwW9MjkEk2ntUkCseUcBLdjCBs4BDNd4MCoKgFie+x/iuf3xPSzsd +x5A== X-Forwarded-Encrypted: i=1; AJvYcCWMbemyCeVUWXKSipNAw2B3q89ge2jjpNulDV1e2vAy73OuUWi5aXZRR5LOJLvJHna3lCw1aMLjXCXY1Xg=@vger.kernel.org X-Gm-Message-State: AOJu0YyGitPOadLNnGAWJpbsXZQ/DBmzA7O0s4ZqopfV8DsDxUIq0bdU SiXfg4PaEt7jxCJ9PQupPFVkDPQs/3t3q7vYwTDyU4SuMLG82p9MXVFoUfDxrgBSDRU3EkWjCcW NBaHKtNKp145dlfmUc2I80iz9p1nBphXoMI3ZdhhxqBsFAGDXTjsIxRF6qit7mMo= X-Gm-Gg: ASbGncvOd6o8cSsg3H4LEYAwuVZGBexBmnIJpQdM0A2enhf5+fuuBH7hnjOx48hzoix GxAuxZwHrvTU1a0W6OQ1xG/hPAIHYL1AhQonzte6C0yIJ0bAtBx2rQKya4DdPyLQGeluC0bsYeR bkSCenDQ7sh+oEnJxrohIhSt+av+aZy9R2fSi2pg3ZaqR0VmOeWwna++6jVHcFSvDyRzXR4kjnm P4Y8ErN/7DnrQVN2toV1wIGFB8qTX9FU3zWk3emRgukfk3Uj6fZsULRgbPlC6raHnKUildNEkuR czNliPZ7P+8IYAP82I2FynudXarb9YoslSBPQyI62IodEl+TkobqDypDI24NP+xAsdOKoNvGY/j RjNFDb1xeA6ibSx5Yz5ZROjWh X-Received: by 2002:a05:620a:3185:b0:7c5:6cf5:9439 with SMTP id af79cd13be357-7c7af115a65mr2232293485a.37.1744709989249; Tue, 15 Apr 2025 02:39:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGTt3VU9M5DSQiZNLKLDNX7P+6oRMR/cwV9Qvdh22sv/7Dpfg/hivv4ML/QFqiWfEQYSonzGQ== X-Received: by 2002:a05:620a:3185:b0:7c5:6cf5:9439 with SMTP id af79cd13be357-7c7af115a65mr2232285985a.37.1744709988296; Tue, 15 Apr 2025 02:39:48 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:47 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:35 +0300 Subject: [PATCH v3 07/10] drm/msm/dsi/phy: add configuration for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-7-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3195; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=VXFGPbLULr+xGELX+USGVkfaqafdytyi08lrC/x1doQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilXA1DFE9LR6Dw8AVasEoRLrlP+3oPztAgJB 53drEbQdyaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVwAKCRCLPIo+Aiko 1ULTB/4mLzW4sxSigYkdzsjo5a65yIkeJB+3gZhK5UceQi1MBNqYKOjyKpn3l2rYMueGWV5Ff16 f4XRGcSW1UF++CMTjmTCD7j8m+NYpHVx9m7XH02aBVgvLTVr17cnx0j5+g1rgDqPhxejLr9MyjW gjQMuidNq6D2duf77r08jJ4MhFCL2tze4ZByyKqJG3ygifvZSCypxv/ZQ5nPbNMHg2b6UIGt4hE QiNyO+puz769Vgu5yjLk4zIFmg9fD+nb+SDNF+W8vK5qgrVzkyIuLCGuRTyIuWH5WiCx33Pp1iS GOv0Bx05Bj+guv8a3F01idqXSzynkEOuyDUvBTdBjkU9y1nt X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: ZeTvJOXlzpJjml6CmroG-9u6Lo4IU51q X-Authority-Analysis: v=2.4 cv=PruTbxM3 c=1 sm=1 tr=0 ts=67fe2966 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=WWvJJprN3eueWNfT7O0A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: ZeTvJOXlzpJjml6CmroG-9u6Lo4IU51q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It is a 5nm PHY (like SM8450), so supplies are the same, but the rest of the configuration is the same as SM8550 DSI PHY. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index c0bcc68289633fd7506ce4f1f963655d862e8f08..a58bafe9fe8635730cb82e8c82e= c1ded394988cd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_7nm_cfgs }, { .compatible =3D "qcom,dsi-phy-7nm-8150", .data =3D &dsi_phy_7nm_8150_cfgs }, + { .compatible =3D "qcom,sar2130p-dsi-phy-5nm", + .data =3D &dsi_phy_5nm_sar2130p_cfgs }, { .compatible =3D "qcom,sc7280-dsi-phy-7nm", .data =3D &dsi_phy_7nm_7280_cfgs }, { .compatible =3D "qcom,sm6375-dsi-phy-7nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 1925418d9999a24263d6621299cae78f1fb9455c..1ed08b56e056094bc0096d07d44= 70b89d9824060 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; =20 diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index a92decbee5b5433853ed973747f7705d9079068d..cad55702746b8d35949d2209079= 6cca60f03b9e1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1289,6 +1289,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V4_3, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_97800uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000, 0xae97000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_98400uA_regulators, --=20 2.39.5 From nobody Fri Dec 19 17:36:42 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA8C128F53B for ; Tue, 15 Apr 2025 09:39:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709995; cv=none; b=crOIrXUoHY5pyh+OESuqxEFzoUnVpJkH+xTlKlwq5/J+tBLR4GQZr/mzeEgzOKU9iHQTCbZnz95/UX6XsbXfzz8xuZ2MN65nQEvG/nQ43odnqMlJW9vy3hlpZPMRHyasABXmQFqmy9gtGulLhrZUNfTXtvhJIy80YyEtiOba2kY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709995; c=relaxed/simple; bh=2FfeI9/zloaxLlD/BA6gayC7nPOA2US7kt0sensuhnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mBoDADC0DlHpP/pysqy+cVzl9NG7OtC8fPdRZH9wKAueTtFVXHtjB92VqvNxm1lxiaPjNGT2H0B3rFWcr7Bb2LmkQXlxSAdJQefBXw/jmq6TJB2nzRjrE5VnaSn+Aop7CMceJpxSc675W7Af19fyv4wUCIsn2DrOXt0ohHIR/9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=iG95cnq3; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="iG95cnq3" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tFGH005833 for ; Tue, 15 Apr 2025 09:39:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= OWWUFIeMvrorqCokTrFFXFD6d7u7BATQB18JH/bmYHE=; b=iG95cnq3io4lstx4 njASUEjWxvBTs5qjGF2ioHr8VgmevcCX3AU0q++PVJMLwLbOmxBWPPYLCCGjFWIl 9444Rv4xaXGS03E8YCr3pwWf8gbZBdJti7P8g5SpWYaNAi3miJC0DifUA3k1mwGW hHP0AxupjG0cUM3/cZj9rD+NJD6Onv9f0etYwwvOwCFtj1MG3/ysYAA9QFhdRFeJ kdkFZMxPROIM+3pK9F1rheBGWI/j7w5/SIb7CkAsTHBMTCzzejXerqhR3jhScjkf iyEKoEDV5H4uCeSj5Bo5L5n7Q8K0UwVlmibtnA1ElYGPWnU85hDwUL+n+BIXnIbK idW1vw== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45ydvj7qgf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:51 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-6e900f6dcadso111977426d6.3 for ; Tue, 15 Apr 2025 02:39:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709990; x=1745314790; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OWWUFIeMvrorqCokTrFFXFD6d7u7BATQB18JH/bmYHE=; b=TQ78TXwINCjdFko6cPA64Owbds/Rhmzf5dgKhhPhZxTyKmPAN2yxhj+KjOrpFsOXyw G9ODwhDBb5qt48LMKRW3nv7WW7VqyDXYCnp5wPdusEFz+TodEpdymohYtlMFIT3iItNG 9JDGVXKSesRfBKV4puiYF9a8RVxwlt8VOZuDh6X7FGrqKRxBaF2pThTKnVA0ZNiN1iwE OrC1TKXyQtxAvZ1HMIvKuCrrTeh5LjMcfBkDqC+nIEtDZ0UoW5GLUHiJE9z1Uo1NQ8l4 hjamx0Pz8xJLteM8D2CuHUczO9BBYB+TUUMwj42xDiOt0BMwByoHtKFmXlijclZLcQ8l kV+g== X-Forwarded-Encrypted: i=1; AJvYcCVK4rH+k/T06msHXApwOeGVa7VGhXpfMvWHiGVkpYQuAafuvyeoJC+peMhyBr5GYKyVzgHNRBCuI2pt5Uo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/K4vIksZmCkIzw2h0K8vPKCmd5QVQGiEy9YLrhTFAGRsXtFC+ GusHF2x3+twGsqzILZ75PFHATZSTIq4i99E3UwSdb3oazq2ImA8w1kS9MkDhaSNW5+NLZw+g6Su sqD878yBHKAmj9oHjLejpilC/pHtfRdPFE8jkFdsXDUovz20wPJaUsr9VBAqtuag= X-Gm-Gg: ASbGncvRugOpw5G9TDVgFUTkAXDJMFqn/MFH4nM3ljJLfbZzKSl5bUCkp7Lp9/ixjbn L+i9RF+1YKxDVWHb2lZYkZR5yVEGK7bgpBJPatHjl5WsjCsY1oGCu+4q1q+sb9042U/nGp50QfK NgowWZn34wlwgwcDRLVxA0WyRbMF0wFyS9rUL00Ep6KK7nivBu8HReWk+M1L7dDG0+RFzudMNr6 kIE27xzcPKEO0ir/Z7W9/Leq5t6ejoGKlnAUY3Yyu3lOnDl4xCGYflM4GpLKiK5k9srBONML2Me 9anQwBZY5YJ0mBUgnSHdYjPsGYUCH+r3WfBgWCXvmZ/RieSQEGZ21LXWQuFrkBCScEM3qWRZPz3 hoeb7Bps8oOvFspe1IVeu8RSy X-Received: by 2002:a05:6214:b62:b0:6e8:86d3:be73 with SMTP id 6a1803df08f44-6f23f14fd7bmr176034086d6.37.1744709990258; Tue, 15 Apr 2025 02:39:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGcWqTv+BPnsDLYvWkiWk9i4nD3woakGEBBr3cP4PDdQV0KXOdLeelwCXZ4Y9CH2oQfdv7hVg== X-Received: by 2002:a05:6214:b62:b0:6e8:86d3:be73 with SMTP id 6a1803df08f44-6f23f14fd7bmr176033786d6.37.1744709989834; Tue, 15 Apr 2025 02:39:49 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:48 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:36 +0300 Subject: [PATCH v3 08/10] drm/msm/dpu: add catalog entry for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-8-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15989; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=slW0LiFb1vChUp3iURdTYj1X8k/a4ZENojPRYgLtgrA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilXpb3QhZZukBMPpfNiIggWr7EvCwp9NTNzv gz5onSo4KOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVwAKCRCLPIo+Aiko 1aNNCAC0JgHWgE9gMwGrw/i5n9pNOhQiKMaMLjo+m/IDsCAWBPbB0iDDH71EF0wcyVyi6E+nswp OyiMdMO83sjIKrl/Z146FZPVj9gWzPva8M2G+M83a2c42d9lNQOmiUp94NpZXap/WeYYtW8YDSf PqSYe7gjJgF+lXc+b8GncQ2a/EL4sCLXK/NoGS8vLXjIEwct9jDNlfIMgFfFAjlY41soRanB38S pBx5mVcd6xoJR6SbQxDe1LP2TMYjZZ31J2vQfDXlPQOb6sPcQzNqXz7RGYPB5ottxM8A2kN/K8W BfzThOdO0ac1XeDmCuQ/KY7+dUycnC5V6BVmciohT4rAkPGc X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=ZIrXmW7b c=1 sm=1 tr=0 ts=67fe2967 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=eC8vNvCAv7fLf3zHfyMA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: FDTnR6RxdKMVoUnNV35-wXFNbTK3It_B X-Proofpoint-ORIG-GUID: FDTnR6RxdKMVoUnNV35-wXFNbTK3It_B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 mlxlogscore=871 spamscore=0 impostorscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Add DPU driver support for the Qualcomm SAR2130P platform. It is mostly the same as SM8550, minor differences in the CDP configuration. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 434 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 437 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h new file mode 100644 index 0000000000000000000000000000000000000000..22dd16c6e210e9520ecb7a851be= e402032fa1ee2 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_9_1_SAR2130P_H +#define _DPU_9_1_SAR2130P_H + +static const struct dpu_caps sar2130p_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 5120, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sar2130p_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +static const struct dpu_ctl_cfg sar2130p_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x290, + .features =3D CTL_SM8550_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sar2130p_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_2, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_2, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_2, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg sar2130p_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x320, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, +}; + +static const struct dpu_dspp_cfg sar2130p_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; +static const struct dpu_pingpong_cfg sar2130p_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, +}; + +static const struct dpu_merge_3d_cfg sar2130p_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x8, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x8, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x8, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x66700, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sar2130p_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sar2130p_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SM8250_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_intf_cfg sar2130p_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg sar2130p_perf_data =3D { + .max_bw_low =3D 13600000, + .max_bw_high =3D 18200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 0, .wr_enable =3D 0}, + {.rd_enable =3D 0, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sar2130p_mdss_ver =3D { + .core_major_ver =3D 9, + .core_minor_ver =3D 1, +}; + +const struct dpu_mdss_cfg dpu_sar2130p_cfg =3D { + .mdss_ver =3D &sar2130p_mdss_ver, + .caps =3D &sar2130p_dpu_caps, + .mdp =3D &sar2130p_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(sar2130p_ctl), + .ctl =3D sar2130p_ctl, + .sspp_count =3D ARRAY_SIZE(sar2130p_sspp), + .sspp =3D sar2130p_sspp, + .mixer_count =3D ARRAY_SIZE(sar2130p_lm), + .mixer =3D sar2130p_lm, + .dspp_count =3D ARRAY_SIZE(sar2130p_dspp), + .dspp =3D sar2130p_dspp, + .pingpong_count =3D ARRAY_SIZE(sar2130p_pp), + .pingpong =3D sar2130p_pp, + .dsc_count =3D ARRAY_SIZE(sar2130p_dsc), + .dsc =3D sar2130p_dsc, + .merge_3d_count =3D ARRAY_SIZE(sar2130p_merge_3d), + .merge_3d =3D sar2130p_merge_3d, + .wb_count =3D ARRAY_SIZE(sar2130p_wb), + .wb =3D sar2130p_wb, + .intf_count =3D ARRAY_SIZE(sar2130p_intf), + .intf =3D sar2130p_intf, + .vbif_count =3D ARRAY_SIZE(sm8550_vbif), + .vbif =3D sm8550_vbif, + .perf =3D &sar2130p_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 64265ca4656a04d8c5a1d9582d7124c7eb897099..ce8d88e1d8b8bc6dea893f13a04= 49315ac8d2841 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -759,7 +759,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_8_4_sa8775p.h" =20 #include "catalog/dpu_9_0_sm8550.h" - +#include "catalog/dpu_9_1_sar2130p.h" #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..e9b627e02c8996c8fb611e8e333= a35e7ce9b8373 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -841,6 +841,7 @@ extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; extern const struct dpu_mdss_cfg dpu_msm8996_cfg; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; +extern const struct dpu_mdss_cfg dpu_sar2130p_cfg; extern const struct dpu_mdss_cfg dpu_sdm630_cfg; extern const struct dpu_mdss_cfg dpu_sdm660_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 3305ad0623ca41882db0172e65a9beb7ebe00b6c..1fd82b6747e9058ce11dc262072= 9921492d5ebdd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1512,6 +1512,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, { .compatible =3D "qcom,sa8775p-dpu", .data =3D &dpu_sa8775p_cfg, }, + { .compatible =3D "qcom,sar2130p-dpu", .data =3D &dpu_sar2130p_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, { .compatible =3D "qcom,sdm660-mdp5", .data =3D &dpu_sdm660_cfg, }, { .compatible =3D "qcom,sdm670-dpu", .data =3D &dpu_sdm670_cfg, }, --=20 2.39.5 From nobody Fri Dec 19 17:36:42 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1DB29115C for ; Tue, 15 Apr 2025 09:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709996; cv=none; b=LrXGEwIPOeAxwAUwX0+U5zW5KQOOhyVQ8TbwTI4FvZbsWshesLaYk6FpF3VeenL0+IWlldudjFR0oMir+8e9gRKLP1w/ClWlOhsVKmGPFVHTrDJXvQMqdZunVTL0cVDASOYMWDd3w2W8fx5+GEiTLoC+pQGoI494SJVd93RNwY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709996; c=relaxed/simple; bh=QKe0w7hPSSum9QIzowcfFL2ZOQ2kKQJeinyQFxWQ3qU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CcA+mBtWpk6raJFrOLi3oEiJZTeZSvcFUHreGXHeViyDsA2H/+NdwqTfhTTSzKXwiIfOloKv5/47AswQjvIoeGefwQ4XmKF0N5V1uU2XlwYtD8mOMpYCPXhiWskWFtfiG0D5AixlpGG7B1esJV/YVn2uQK9yGiwXwAnx/doNiOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dNigE9nw; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dNigE9nw" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tvVT025669 for ; Tue, 15 Apr 2025 09:39:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XZFldRXNlH8KDu+WC2sgkeRrWTmxXWr9px7jq0yAmCk=; b=dNigE9nwGZFwViS2 a5PF8fqzQQ01yz2+aaC5LlQQpKSOlliG7r7MX3ioTC6X8Utc0SslzkhCGGU9PuX1 r6T635CkS/R8FTSdmLTDQYi3tGQDOH6KRj7U7oxX6GbR49pj6qVL7XQYvhppJWTQ TBy8KDDHG/Q3VZPeBHHjpyfxoZFrCiY+eufX2BW4ZMALcmsoqOMquMJzgF4tlfW7 wY48ipUZ3dQyIfRd4NCCZ+e0tRefArFxtanEIoQLXhHoN+xs7wUDl3jSVbz7VWUt IyyC3QHFBh9zTmHxTuv/rE6YizrE8zsmyZZsbCpqupkuLexE1Aeks/oCcy2qKVJk 9R9tOA== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yf69qjrk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:52 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-7c5c9abdbd3so498448185a.1 for ; Tue, 15 Apr 2025 02:39:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709992; x=1745314792; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XZFldRXNlH8KDu+WC2sgkeRrWTmxXWr9px7jq0yAmCk=; b=pq6v6Yu4q+ouPFANI7N3BLbpg3lTLgFvfD+BoCv4CRey6M8ZNmslQVPyRp1ZE5d325 tt0UwACXjjicreLpyPDvxXfxfWXKaOt0mOCBfZCa5QY3Y52DaVbhRWrxbLTlvyRHAtsg PcmtrSSDvYjTBP99dHib3pRO7P3Dpt3FGFOGJlz5CspHAjPONjXvD45Vod9uCSzAFuWy jC0LF3ud2cXqrgENkXWICoiFnIWU3IpIOMZjFk2WYM2su9ts2K9Xc6j66BDrrFXtQB8L b0sev4dEzehn9bM+4bhcTm3VyNms0nMYbBgWDcMr+T3NXPIOyr/G9FXXNAvJGK79oA72 kfwQ== X-Forwarded-Encrypted: i=1; AJvYcCV23c5KpaTbqtl2sMj9E+QwHmzk/Rx5FZuWCJwFtV7YD4MlaR/RyhBa3rGRAeH0/fzrDaicyHoFcpC4VLY=@vger.kernel.org X-Gm-Message-State: AOJu0Yz3QScUPRz1LAQpwkMwPXfRRxzoJjy6xpPhgmzjKDfNmsb9IlYs rQezGDRjP2ADKew0nb9xuAIp/v48RwVe327V9NVvyASjhWmxucmBzFUbsE1A3fIGmG+jDdxgBWx KhU73iaubTHHE11efGVA+Tvs5aNzwOK6TyX6K6cp7yk22pR7llQkso5Yj1oVX/r8= X-Gm-Gg: ASbGnctQZwmJPQvq747Ia9cbldK4FauEX+Uc8yF2wCVdHoFGfRfVH2fZU19V98xDJjn fJc9HYliL55suRTQeFps+Moakh5kzzPyc1y4U7SZbY4GWbpSUvgig/bTPV0fZxQxw7s7FET9kZC f9ZezNf2ZRm7K10hWfCS71+oSskzn/0pIfTyGQSBKTecmojLO61j38faCfBF6BplId7rHsQk2vY e9AvNTSuXuEI4V58r9x7b0T3az9VZvbyRouzu/LpxFLRCxnpS9gZ16xHyuNV37QSGWxaTKsNbmE +oMIY9yeE+x1aV6AQ4U7j19dRz9lKJzFFKp87RuYtqC8M93OZBq6aBKTBJ11a+CImiK1wdJEW+o EuDNPIPi0gcCxgD0Sdd18Y7qF X-Received: by 2002:a05:620a:462a:b0:7c5:5670:bd77 with SMTP id af79cd13be357-7c7af1238b2mr2775899385a.55.1744709992262; Tue, 15 Apr 2025 02:39:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH60ouhfu37ZbUCCdaM4Wu6LIXI6BjqbTNDAqrORBs8MMR78mEaAc58RFd2noqZlts0YKJvpQ== X-Received: by 2002:a05:620a:462a:b0:7c5:5670:bd77 with SMTP id af79cd13be357-7c7af1238b2mr2775894585a.55.1744709991825; Tue, 15 Apr 2025 02:39:51 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:50 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:37 +0300 Subject: [PATCH v3 09/10] iommu/arm-smmu-qcom: Add SAR2130P MDSS compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-9-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=944; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=j/LGXpgnuRffqJSRqVOkk/ZdY8s1uzD2F9Jjdwztl/s=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilXhJKvBRqpk7CsNPZqkpAehg4pITVdiFpes BoRKdFHXJ+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVwAKCRCLPIo+Aiko 1YP/B/48+nZbO6Et4YDrFWvGyDoqZpKmhOtKcHu0rNlck5OXzpwD7f7PaaYn0iNa4VhranUrM05 BA9wH1/Bhcadows98Uc/YJBciKXZzDXfGPzPX1NlE4svSULFT6UXGKCnKbJ3k7tzysLk4VokMuD pyUm5fuw71OpydRmXg63Rr0cj91Kf5zroL6qfw1mxGCTv+r6R0V/YT6Z1NhK3wT0XKYnBpKEGOO IIlTK9qGbb/8lgNiHyyKt39Jk8f7iuhRdI9s/6awWqwdJx45NMB5RoIZX2omEfj6b/kW4MYjAs4 5Lsn7TNDh9esapdQGOlGifx4ljoLqB/ocUsddivk1Pger+N5 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 0h75g19CfWmCHOyFp3FS2YbupJtQitSq X-Authority-Analysis: v=2.4 cv=JNc7s9Kb c=1 sm=1 tr=0 ts=67fe2969 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=VUTEsYOwyNIbN2ghz4EA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 0h75g19CfWmCHOyFp3FS2YbupJtQitSq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Add the SAR2130P compatible to clients compatible list, the device require identity domain. Signed-off-by: Dmitry Baryshkov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 59d02687280e8d37b5e944619fcfe4ebd1bd6926..ecc4a1bc9477b766f317a58ef8b= 5dbcfe448afa9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -356,6 +356,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,mdp4" }, { .compatible =3D "qcom,mdss" }, { .compatible =3D "qcom,qcm2290-mdss" }, + { .compatible =3D "qcom,sar2130p-mdss" }, { .compatible =3D "qcom,sc7180-mdss" }, { .compatible =3D "qcom,sc7180-mss-pil" }, { .compatible =3D "qcom,sc7280-mdss" }, --=20 2.39.5 From nobody Fri Dec 19 17:36:42 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3D5E29117C for ; Tue, 15 Apr 2025 09:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709999; cv=none; b=JG1kxR47rkb3YyzHIOkMnshJA/sGkGsTYPO7jvlwD5Y9u8TkbcgJUf7U7brU06xF+hKcaSnrqYiLpWrvzmO8D81HteSLs1yruwTpsYiKXyZN/WKyTlf5jl/TL212URxFs1OJyRG0vcQ9Bl4g6QllTr3tiVUNdEm0sLhQFYpA2Wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744709999; c=relaxed/simple; bh=jaKQo/tCjKokY1uC7q+CT6lVIBJ+umoz8JRUUn+uT78=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gEtM1x0mY+2QLbWR3sJ+D6z3SNLwmEdEesRgsjrR5imiQ+vEL2kHp3aUSiFL1MtdQRWt2aKxWM6SZGKNRdzXZzy78qqVOlkXCuf+paVlhkLo4z38H8Yii2B1fYhtC7Eya6hqyaLvAiNI+bL0EPHgPJLxYyKWlpfEjQ/pBEWEn48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LGcQfTJH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LGcQfTJH" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53F8tEuk018856 for ; Tue, 15 Apr 2025 09:39:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= X3DP1KuIzXvoheUhhkp4eN5f13XfN3f7+MsTSdIWyo4=; b=LGcQfTJHBmYG2QdE qeYWeXPXjbcoKwlvTiM+xVu/pdCcWfrdd8egsWLMq8/nSni3LbKFgs3Ct4GxuFuf yl0apaJAuYexeL3cBT5qkkui0Eyp/6EGozL8WtglKnSQ5Po9OEshthLyDfi7BNY0 AZedUs42Ci6nHuGqlrG+gMd6GQLmPaLw1UPWaso5EXTz1WyYQtG+A1SH3iMA+PXG 30SNp9VdqSDisqNS+x/inANwxzWkaacyyRcK+mgm22YrkjzeZx3JT/RoTrwQMfOh O8+ylBc8rB2vPehT3VWHGOlL/LdkR/PyV8NZpgeyO3BGdyzfgSFpJKrT08RDmuIo cUwgSw== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yfgjfgby-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 15 Apr 2025 09:39:54 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-7c5b9333642so607396085a.3 for ; Tue, 15 Apr 2025 02:39:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744709994; x=1745314794; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3DP1KuIzXvoheUhhkp4eN5f13XfN3f7+MsTSdIWyo4=; b=W79U//ijwDrHbLdgNpbTk2datUOUV+YEWI1sa5gsoGd0nFnBPkxBT2W4av+7EMzAV9 /ZLcCgZOeQn91gyzpTBWNeQJ66IQVWXPOf9EbHiXqqY8g7uJJRLcADiGLr8WJTfw9bpO f4lMcbkh/Yl4ND4eo59H5A9a22KjmPtA9eKeU0SnDbsqA+/JrZYzfFbF9GOYfNFGnQwm 7Vvr40Zs/OE27haMw1dPjSwRVs0eMYRwCQ5pr2Swy0EpVhBu/KdFBJ4nCshiqfyK5ocg wRHw/FNqG2He01UnM/ByBBAFC613rCRKH6HouQY0kcwoCEOr3vVVSc4ZoF2k8ntd8vhe 4mkg== X-Forwarded-Encrypted: i=1; AJvYcCWsoeqxsSoWO/ABi5Hd6IANQ52MFi1nqB4aPWzolc8N9FCN8EJkkDS2+8eruPtdtF1TMeE4ScOWRbE6ZwM=@vger.kernel.org X-Gm-Message-State: AOJu0YxU7bum8YzoVNQIqYlH+fiJBv1UUCgOM2EnlzBUdkNUyaoODo49 dif74FZRpQ+dd34sZI0yBBAXIdxgN9lq2gBq6B8vOQaMpxKo93WwBZXForCL9PiMW+/aeEkFylk dVSh5Bro1jW9IJDYyQCEoJDDXG2hfAf2Cl2QESAsCK3q4Wf87mW1UZk59thzVOJ8= X-Gm-Gg: ASbGnctw1D8nd+qArqLpBgXLtksiH7K/LEmpNZ7BMRfpDEYR0DlWWgkcEhveMJqzDN/ CxGFuPrvH+Q0XSFdDRAnfUs52qoa/O7qUXPEj90J2kz75KlmLHRzuIMdsh/cGQGLCujER7enNEy IBzADZvLOzVPtEvOukzdWSSGtupb339buBVE7Vp1EI2gPWFNxv+KRe7kz8oN9yv0ND0X5MmNjhb O2KmheVHdywxN5C48W/x7MPkeV8pRWQrQ7qyX/XLo6O4UsmDsh7bNeIFPBaQGS3ipsV1L5L4ZY2 fQJaEL2vaBXHqX8l21EakDCDB07Y9Y6RaJX7GldN9D2TmLpteZFuAkQogOIJvlbadu6iCyTRELH DHhhz2S5jPcY94H+MVc//gORN X-Received: by 2002:a05:620a:3941:b0:7c5:e370:5b1 with SMTP id af79cd13be357-7c7af0b983cmr2584764385a.7.1744709993812; Tue, 15 Apr 2025 02:39:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHhEsUrI9JGMcHJIQdLPzJECRSXMuxZIkBQvKi6yorXhuvCGWRbam2l8IoOqe1Oztk24ed2mg== X-Received: by 2002:a05:620a:3941:b0:7c5:e370:5b1 with SMTP id af79cd13be357-7c7af0b983cmr2584761885a.7.1744709993355; Tue, 15 Apr 2025 02:39:53 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464cbc60sm20141901fa.24.2025.04.15.02.39.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 02:39:52 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 12:39:38 +0300 Subject: [PATCH v3 10/10] arm64: dts: qcom: sar2130p: add display nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-sar2130p-display-v3-10-62314b1c9023@oss.qualcomm.com> References: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> In-Reply-To: <20250415-sar2130p-display-v3-0-62314b1c9023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Krishna Manikandan , Jonathan Marek , Bjorn Andersson , Neil Armstrong , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11504; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=/eDiGUtPG1uX9BDXZTrPxa9llmv6JxW6//ctZSlL0vM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn/ilXDx6ZjMcbTyJOW308myXwjAo0FFIqlU2Wu AE47wVJ1VaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/4pVwAKCRCLPIo+Aiko 1XXRCACkdlcEh6NwjmRmdnbjxiCjwZt/TqiGQWExprZZy2xDis406JOxryE/aHxoHhs0tAYAH3F Is8Op3v1V9yMz54WNDIwneMPbaAzXh1iuR9Y0T/izjkkT9JE4hZp433oxLrKi2LjzuK4lUL03lD JMOIvD+CtbLUxFGtkYGenns8AmqrotCH0rXaJXNcQ7+7qdAuWnVtOFJ7lzrQFfZ8n/IfmxhuLWA M7Rqk0oKXXYKPf+yQBqmaKYSHQ6KNBbed0R+6pR6HlhJKwmhtxaocLvcmmF+IOEGeDNynTiuzcU nNTUtt9YJygBsSiQ61kTq3IrNSjcZh66e2rGVKWqELiL5UiC X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: Jz46oA4Ov69GSlmvqXZJ16LvyFeUMGog X-Proofpoint-ORIG-GUID: Jz46oA4Ov69GSlmvqXZJ16LvyFeUMGog X-Authority-Analysis: v=2.4 cv=Cve/cm4D c=1 sm=1 tr=0 ts=67fe296a cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=qobt-ayf5lTqXTu-rvoA:9 a=APn_b-CA19tBE8nr:21 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150067 From: Dmitry Baryshkov Add display controller, two DSI hosts, two DSI PHYs and a single DP controller. Link DP to the QMP Combo PHY. Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 395 +++++++++++++++++++++++++++++= ++++ 1 file changed, 395 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/q= com/sar2130p.dtsi index b45e9e2ae0357bd0c7d719eaf4fc1faa1cf913f2..1bd0eace87e0bf171270b411391= aee2e1a136dd4 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -3,9 +3,11 @@ * Copyright (c) 2024, Linaro Limited */ =20 +#include #include #include #include +#include #include #include #include @@ -1915,6 +1917,7 @@ port@2 { reg =3D <2>; =20 usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; }; }; }; @@ -2012,6 +2015,398 @@ usb_1_dwc3_ss: endpoint { }; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sar2130p-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", "cpu-cfg"; + + iommus =3D <&apps_smmu 0x2000 0x402>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sar2130p-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sar2130p-dp", + "qcom,sm8350-dp"; + reg =3D <0x0 0xae90000 0x0 0x200>, + <0x0 0xae90200 0x0 0x200>, + <0x0 0xae90400 0x0 0xc00>, + <0x0 0xae91000 0x0 0x400>, + <0x0 0xae91400 0x0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dp0_out: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sar2130p-dsi-phy-5nm"; + reg =3D <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x280>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible =3D "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae96000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sar2130p-dsi-phy-5nm"; + reg =3D <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x280>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sar2130p-dispcc"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sar2130p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; --=20 2.39.5