From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D0BA21171C; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; cv=none; b=G4p/LwXnj26VPWTlbdPLpCw8ycayVLSwL1FdgLPg/OX9OPSC8R1gmbTOkWmG2YjaY/ELlkcq0oOq22F7WDmlap8GsNkzOU9s3W/gjrUPpGP3rNYiGwQEqPoUZCCRWLlQDlfx1gJ5do+saykQ62+GGSWbGsNdf1fNlLcaBPzk3jQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; c=relaxed/simple; bh=xj1/d4nkyU14Uz0z2ygXiCJS8S9VEH7Pg1iUVkAGGlY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GCwlYqDpK4UvbrgMDGpnPIDo7/TC6ZuK7t+E436mr+/NVrNoCqaunVabzGSwnz3+yqM+Dr2ozGRFyhFBn0Bfn2kWyUXXhazEk5QsM9HfWNnXPVwCJLPDO/zkkpAyaycgzk8X1L0aAaU3wZ1CYA+FoArYD7EnlyQcfAxKk3Ag/0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PcA0pFHS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PcA0pFHS" Received: by smtp.kernel.org (Postfix) with ESMTPS id E37C5C4CEEB; Tue, 15 Apr 2025 06:54:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=xj1/d4nkyU14Uz0z2ygXiCJS8S9VEH7Pg1iUVkAGGlY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PcA0pFHS3ONR5KsMUsVVXJUR3F7Xsr6rf7BUYP868zzzuhGcLFTkCwS8WJn8c7q0+ xe8heMLwm1V4aMpJrVc6PMbC8SHt/+Lx71R0dzVixQEtv6+tyDWGx1azlSzD/C1Oej Dl0tFTD3oMQNf7+PNrkjRbGE+oVzyc5IUE77m0GcMGzUH7XvshsEdXFpUUE6++5PN+ KZaJRCR+h0eueUfaD+yVvWq+4bttJL+qH43AS/S1InxcXWBhX13eLA5NYMvnqC1/dJ 7DVk9sFZfvdi9UDuEQY1w1LUqjPy9NctweMbHL80LeQcUyBoJ0E2veWiW9//mt94Qk rq+pE490OoZnA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3DB6C369B9; Tue, 15 Apr 2025 06:54:27 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:24 +0200 Subject: [PATCH v5 1/8] dt-bindings: arm: fsl: Add GOcontroll Moduline Display Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-1-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=1206; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=7LK5io9tXyJrf5fT7pNPykcX/YAUSsMUIEqjia8Pbmw=; b=ACiLF+8gGRCfbw7wNIsrQyjR31okP/EFz6jYkJhE9Irn3cvQ0nAW0nJATvJXFrWurXbpc/JAl MyI6Aj/fSxtDNEBweBCOLj1WEOkryULUPMxyZeOP9GXUKTLJEjEm6tj X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Document the compatible strings for the Moduline Display controller. Acked-by: Rob Herring (Arm) Signed-off-by: Maud Spierings --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 1b90870958a22e49355dd1f932bf3d84cd864b5f..ecde2123ea0fae38ef233929c7a= d343812851a58 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1095,6 +1095,7 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - gocontroll,moduline-display # GOcontroll Moduline Display = controller - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without fr= ontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control = without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control w= ith 7=E2=80=9D panel --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90B722749D3; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; cv=none; b=sgHdgC+OPdVJ490NZSG0/iJfLxKXgryoeELz5g43bjJZaKYH6muL7vFsKm4LKwb256AYJ78LAo4vy4l3OBp5ir6jt0b6a+z4zG0ZwPBPLQbzrlBAH3zwqOvAb2ik7q943Em1KqQVSzZA4ve0GJ9jgE1H0U7tz0X//oTJLTn9+VQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; c=relaxed/simple; bh=6Ng+hdOoNno07pilCVpRF8PT7c6ejjDq52moQll8qjg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VRO3I5OVO3+yrNX+nTl0lklY5A4Uuh6RDd9g1ADjQiL4YyPiYo4CanntuuYwA4pC+kJN3XPxYr/0vJJ0H1Nn2JdhdmqI+PROAasTuZlJizd5lHP627NYoVOQ4PXF7xAFRzs4mvq+RB+VJgZbVHPKGW1LHchuF23rB0/AZT4fd2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AG1wHHKz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AG1wHHKz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0A538C4CEEC; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=6Ng+hdOoNno07pilCVpRF8PT7c6ejjDq52moQll8qjg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AG1wHHKzuGOEjyHcTQDTEFApRy/xKYRs28PlxpM4fuZqdwXQrUZ499YXz0jgwGD2Z BA5ikTX3qDboHCEDgQcsLXSpAFU5T+twmz6x9LTxzDYRw4imLEgaAJLFm0Gu6i9Nvm +yv7oZoTEBgHxjchTrNb3UZtGDlE2kL8B3HH/VdNBgUS/yDGSRs+/IovKc9ZcGx5gm aaDt7pe39sfDN1zehKZAhVQd6GdaICCtJnAJ/6B2krno2ZFcGx0vEXYX6l9zDTbk+k uP4C9qKAVed6NNwHD87WC+3McZGF/VXPL1pZuLvH4xKjCw+2+7RySbvCGudxEwxPkE CnEdb9cw9wYhA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE637C369BA; Tue, 15 Apr 2025 06:54:27 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:25 +0200 Subject: [PATCH v5 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-2-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings , Frank Li X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=2170; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=mrxqwhYhMzGSTJWlhyHKyT15kZQ0Bh3K/pqX9Brfdms=; b=l5cWkOZkli2C/r5xy/aAJZkM5QY2YmOLj+0m+NcfzHpH+7mgP6BP6lJ5fKaSIarfDpUL0YgEm wC06Q9YnXKjDoZc/fBWqriIXTIIVUWzo1vf2WhDLhocT+tJ+iini13o X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) Signed-off-by: Maud Spierings --- This patch has already been sent in a different group of patches: [1] It was requested there to submit it along with a user, this series also includes some users for it. [1]: https://lore.kernel.org/all/20250218-pinctrl_defines-v2-2-c554cad0e1d2= @gocontroll.com/ --- arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 33 ++++++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/bo= ot/dts/freescale/imx8mp-pinfunc.h index 0fef066471ba607be02d0ab15da5a048a8a213a7..19a23d148246f4fb990050a9d06= d20b6e769f254 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -6,6 +6,39 @@ #ifndef __DTS_IMX8MP_PINFUNC_H #define __DTS_IMX8MP_PINFUNC_H =20 +/* Drive Strength */ +#define MX8MP_DSE_X1 0x0 +#define MX8MP_DSE_X2 0x4 +#define MX8MP_DSE_X4 0x2 +#define MX8MP_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MP_FSEL_FAST 0x10 +#define MX8MP_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MP_ODE_ENABLE 0x20 +#define MX8MP_ODE_DISABLE 0x0 + +#define MX8MP_PULL_DOWN 0x0 +#define MX8MP_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MP_HYS_CMOS 0x0 +#define MX8MP_HYS_SCHMITT 0x80 + +#define MX8MP_PULL_ENABLE 0x100 +#define MX8MP_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MP_SION 0x40000000 + +/* long defaults */ +#define MX8MP_USDHC_DATA_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | \ + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) +#define MX8MP_I2C_DEFAULT (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMIT= T | \ + MX8MP_PULL_ENABLE | MX8MP_SION) + /* * The pin function ID is a tuple of * --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90B0F2741AC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-3-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=931; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=45G3DurvF3CmLAxUTF3brxzwuPgV1THWsW5gIgc1doQ=; b=nGJd77N9KMAhYG/bxN87/liFszpFCA+IAx/lg6GciwYCsSRdSBfUL0jsOF9uAOF+NttgxcF/8 PDbRCxyupOtCg3H08tIlLmBBqMp6zl5+eQLgGD+zbwjTraFC/uKOeiv X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add GOcontroll as unofficial maintainers of the Ka-Ro tx8p-ml81 COM module bindings. This support is not officially done by Ka-Ro electronics, if they at some point will supporting mainline, this should be changed to them. Signed-off-by: Maud Spierings --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b5acf50fc6af4322dec0dad2169b46c6a1903e3c..1ca022081bcf564c8ec91fb6431= 570045495ec23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12779,6 +12779,12 @@ S: Maintained F: Documentation/hwmon/k8temp.rst F: drivers/hwmon/k8temp.c =20 +KA-RO TX8P COM MODULE +M: Maud Spierings +L: imx@lists.linux.dev +S: Maintained +F: arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi + KASAN M: Andrey Ryabinin R: Alexander Potapenko --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5D9A274FDE; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; cv=none; b=J2WBJn5TJgMtdTsMtfZ2aNUb5HTKy9eHu0jNBqPCefsHD7yTfs5cLvxXUN1wJmOz/85y08qoYySXam8/pAMz+Q+1KcLkOnwUVMsj7jSoEy+bHyJpC8kw2mtV4Udd+yxFqTWuNTeAfuj/K8lsI1VRSU0VYwzox3ii0UcvvGvtP1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; c=relaxed/simple; bh=hrPSQeENU4uIDE2eHQ2o1WCsLDaulSSH1VdJmPvBaVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gpgJraNIe+v4XTd4rwxcw8oy+mEVwwXkSHYg1o46JIxnHP26Y/YXIwzPsYnwoz3/fxC83HoecnEyTS1SK+lmDj0m5Uhz+ar9I5SeC6e/hE3labyR9eqtTV1yTDuYJd05Nm/rjL0S4b0qL5IdMok0TMB+o7VzMswA4T4Ir1y7CP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oJW3BvVr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oJW3BvVr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 291EEC4CEEF; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=hrPSQeENU4uIDE2eHQ2o1WCsLDaulSSH1VdJmPvBaVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oJW3BvVrZjK63rHZrFWVLPrVFAcoBh17mEQ0AdKUDZVThtcfz7PVJ1DhedSfmJo9C 8r5t3FNynBnwGNZ83V29a3Bjh3NxIK4nCMlx21qx41xZTqeo6L78jN/4YgXGKSM8hz zUMGYXGlCPMYfmACaDba5t2TqWAJrv24pjNflZaJiCDD4ul+P0+ZMm/BefAAe9k6GM CZqtUv5/CKVCAxSRd9SiRP/h93N0f72HQoQfJffAH6Q5QnAUFiSQZJazGXTjADLZ1w tAgbjDMEnW6oHYdHUDbqcxQ3AfKB6cyo+Q/yLniHZBat7nFphGPrIiPlAhbOle+CEy WjzajXZK7YWHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A984C369B9; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:27 +0200 Subject: [PATCH v5 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-4-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=777; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=U+cI301uttTYTg6gAR1QRerlXekISKPf4H+SFf8T4EI=; b=8R9Qv7eVCATXQybZcqW6FXRKqRe/5yNEdrsJZ2Dv122cIscipOZULbmyu5hncag/7FC6wiRFU 4Q3S6elRmxGAGTbtD7d1bbI5Ul4TawZXTjlgiu/oY7L6oTvB9fD6Vv3 X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add a maintainer for the GOcontroll Moduline series of controllers. Signed-off-by: Maud Spierings --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1ca022081bcf564c8ec91fb6431570045495ec23..3c94e530d0784d90b50109d4f9e= 7e6ced40f08b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10060,6 +10060,12 @@ L: linux-media@vger.kernel.org S: Maintained F: drivers/media/usb/go7007/ =20 +GOCONTROLL MODULINE CONTROLLERS +M: Maud Spierings +L: imx@lists.linux.dev +S: Maintained +F: arch/arm64/boot/dts/freescale/*moduline*.dts* + GOCONTROLL MODULINE MODULE SLOT M: Maud Spierings S: Maintained --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDECA279780; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; cv=none; b=j4Bo0ShbT49b5Hy+pkz1ATfDzZqw2CvpjR3UtBAFuwpxGUAmmPBS0GwTJGSaBZhAX3ghRFK+D0lEKJeqgTAJHFo6z+zccmoDG+dry/VWowfeR7HRZbaxOpUuxtvDCN1Rmw4gRvzfBc15MTZJttwj4WrZ7ichEinDQSTwejm/xXQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; c=relaxed/simple; bh=xFfh4x0jeLFKxwa57YYqoMwIhm4bE4pQbP82dWCzBbM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CzRNvInkBbI/CLhUVqMxGM3jNOFjBqQIMwEEM5/iTThawiT+e34drRL4F0WB5cPPXS07lWegFfOikXNcXb/kQQrUrQNqUWTgh2hs6opiFyLpK6qqDnYRq0XbJ3t9X3myB0PM9VfcCaY8hL3XdTo+vBHW92ewtgWmx+/sq27eQHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dhrt3IHj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dhrt3IHj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 362F5C4CEF4; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=xFfh4x0jeLFKxwa57YYqoMwIhm4bE4pQbP82dWCzBbM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dhrt3IHjHxi9VMHuzsydx3Fj+7KBl6JgpYCz7t3ce5ly5FW/Tf/XPyF5uuhhKXAj5 ZX3V7jNKhd4Emo+KWInmvLkt7ucNNQXuJMJnx6wjmaXZgMmJp6C7FSrx7mQYJ9I78+ qqkjyD/OBYtnm8jdpHIImaY5nJnKZJwP3usSRL1QwmKDkfINl68JDlKRr17/UmNNtS up/3u+Loti8CdOjRglCXZVm4norvlOh50kZG5OY4IBIb91+Y7V+6Ly3uWhEjdTxvLK Rxft6kzMVmd67DeQofpAu3vqMLlqlm+2KJijj0LssHG30A0tBjA/YrBD876/6dtNPm fyWXsCbKmOyMA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C8AFC369BA; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:28 +0200 Subject: [PATCH v5 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-5-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=15241; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=HoacdWWZItP6AN+UwVPtJOiCna22FcYulzq7UyzHVo4=; b=lV9rVCfyobILASDnDQhT/7zIPgENC0vSV2CLpda+NGfueT1TcWFfCHJhSDya7xBQx5O7HRTIY 0IptHYhtJyDA5vf3JhbwxFB+r8e2tIXKstdH+ds3Gb+kNfWmCA2y8gj X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has 2 GB or ram and 8 GB of eMMC storage on board. Add it to enable boards based on this Module Signed-off-by: Maud Spierings --- .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 548 +++++++++++++++++= ++++ 1 file changed, 548 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm= 64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4c9d010cfd40009a7cc0816a304= 3434b1ca2c982 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Wa=C3=9Fmann + * 2025 Maud Spierings + */ + +#include "imx8mp.dtsi" + +/ { + /* PHY regulator */ + regulator-3v3-etn { + compatible =3D "regulator-fixed"; + gpios =3D <&gpio1 23 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_reg_3v3_etn>; + pinctrl-names =3D "default"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3-etn"; + vin-supply =3D <®_vdd_3v3>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_vdd_arm>; +}; + +&eqos { + assigned-clocks =3D <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates =3D <266000000>, <100000000>, <50000000>; + phy-handle =3D <ðphy0>; + phy-mode =3D "rmii"; + pinctrl-0 =3D <&pinctrl_eqos>; + pinctrl-1 =3D <&pinctrl_eqos_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_ethphy_rst_b>; + pinctrl-names =3D "default"; + reset-delay-us =3D <25000>; + reset-gpios =3D <&gpio4 22 GPIO_ACTIVE_LOW>; + + ethphy0: ethernet-phy@0 { + reg =3D <0>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <21 IRQ_TYPE_EDGE_FALLING>; + clocks =3D <&clk IMX8MP_CLK_ENET_QOS>; + pinctrl-0 =3D <&pinctrl_ethphy_int_b>; + pinctrl-names =3D "default"; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names =3D "SODIMM_152", + "SODIMM_42", + "PMIC_WDOG_B SODIMM_153", + "PMIC_IRQ_B", + "SODIMM_154", + "SODIMM_155", + "SODIMM_156", + "SODIMM_157", + "SODIMM_158", + "SODIMM_159", + "SODIMM_161", + "SODIMM_162", + "SODIMM_34", + "SODIMM_36", + "SODIMM_27", + "SODIMM_28", + "ENET_MDC", + "ENET_MDIO", + "", + "ENET_XTAL1/CLKIN", + "ENET_TXD1", + "ENET_TXD0", + "ENET_TXEN", + "ENET_POWER", + "ENET_COL/CRS_DV", + "ENET_RXER", + "ENET_RXD0", + "ENET_RXD1", + "", + "", + "", + ""; +}; + +&gpio2 { + gpio-line-names =3D "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_51", + "SODIMM_57", + "SODIMM_56", + "SODIMM_52", + "SODIMM_53", + "SODIMM_54", + "SODIMM_55", + "SODIMM_15", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio3 { + gpio-line-names =3D "", + "", + "EMMC_DS", + "EMMC_DAT5", + "EMMC_DAT6", + "EMMC_DAT7", + "", + "", + "", + "", + "EMMC_DAT0", + "EMMC_DAT1", + "EMMC_DAT2", + "EMMC_DAT3", + "", + "EMMC_DAT4", + "", + "EMMC_CLK", + "EMMC_CMD", + "SODIMM_75", + "SODIMM_145", + "SODIMM_163", + "SODIMM_164", + "SODIMM_165", + "SODIMM_143", + "SODIMM_144", + "SODIMM_72", + "SODIMM_73", + "SODIMM_74", + "SODIMM_93", + "", + ""; +}; + +&gpio4 { + gpio-line-names =3D "SODIMM_98", + "SODIMM_99", + "SODIMM_100", + "SODIMM_101", + "SODIMM_45", + "SODIMM_43", + "SODIMM_105", + "SODIMM_106", + "SODIMM_107", + "SODIMM_108", + "SODIMM_104", + "SODIMM_103", + "SODIMM_115", + "SODIMM_114", + "SODIMM_113", + "SODIMM_112", + "SODIMM_109", + "SODIMM_110", + "SODIMM_95", + "SODIMM_96", + "SODIMM_97", + "ENET_nINT", + "ENET_nRST", + "SODIMM_84", + "SODIMM_87", + "SODIMM_86", + "SODIMM_85", + "SODIMM_83", + "", + "SODIMM_66", + "SODIMM_65", + ""; +}; + +&gpio5 { + gpio-line-names =3D "", + "", + "", + "SODIMM_76", + "SODIMM_81", + "SODIMM_146", + "SODIMM_48", + "SODIMM_46", + "SODIMM_47", + "SODIMM_44", + "SODIMM_49", + "", + "SODIMM_70", + "SODIMM_69", + "PMIC_SCL", + "PMIC_SDA", + "SODIMM_41", + "SODIMM_40", + "SODIMM_148", + "SODIMM_149", + "SODIMM_150", + "SODIMM_151", + "SODIMM_60", + "SODIMM_59", + "SODIMM_64", + "SODIMM_63", + "SODIMM_62", + "SODIMM_61", + "SODIMM_68", + "SODIMM_67", + "", + ""; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 =3D <&pinctrl_pmic>; + pinctrl-names =3D "default"; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <900000>; + regulator-min-microvolt =3D <805000>; + regulator-name =3D "vdd-soc"; + regulator-ramp-delay =3D <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <950000>; + regulator-min-microvolt =3D <805000>; + regulator-name =3D "vdd-core"; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3"; + }; + + reg_nvcc_nand: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "nvcc-nand"; + }; + + reg_nvcc_dram: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + regulator-name =3D "nvcc-dram"; + }; + + reg_snvs_1v8: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "snvs-1v8"; + }; + + ldo2_reg: LDO2 { + regulator-always-on; + regulator-max-microvolt =3D <1150000>; + regulator-min-microvolt =3D <800000>; + regulator-name =3D "LDO2"; + }; + + reg_vdda_1v8: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vdda-1v8"; + }; + + ldo4_reg: LDO4 { + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <800000>; + regulator-name =3D "LDO4"; + }; + + ldo5_reg: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "LDO5"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION) + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER + (MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + >; + }; + + pinctrl_eqos_sleep: eqos-sleep-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_ethphy_int_b: ethphy-int-bgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst_b: ethphy-rst-bgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; +}; + +&usdhc3 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates =3D <200000000>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + vmmc-supply =3D <®_vdd_3v3>; + voltage-ranges =3D <3300 3300>; + vqmmc-supply =3D <®_nvcc_nand>; + status =3D "okay"; +}; --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDE1F27587D; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700068; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=nFLcCxtjPajV4K6nKMZsoDSF6ba4hBX8t30OvlQ4nJM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cAO2rKKbckPbJin5bIQnkd/vsWwrhwGHYNlacKGV8yi675tiWdJZSOj5roeDoTjR4 X2T4NFR/MfREgMCvCw1o88DHrPWH1LkNx52I8ffGBBCVs4yl1tBbLCaJAH8UI0Fi+v zGyZXOzsDHE9kSSbsSgMYFKeszNZQ3zNE2LC76bfHcQV/FDU06h4Jbr6EjUbvxlfc/ 0YsiyajDOv2K1eIKfvir+LomvlxZLUxucyVLpfQnB1hftXm+Oc+B7IgKaBpaj592dY bcAWRXWmG0ar6D+V+87SX//ny7PdfMQtJ7eN/LrN0ZYqrCdjTubqGuP62hOK2kGwId m0cOD7N0cL4wg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49058C369B8; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:29 +0200 Subject: [PATCH v5 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-6-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=14933; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=FbElz7h9Q9+Rezp4sqeRAQ+rTOuCMOZi7wWzuak62ws=; b=LnNRBwsKme0uVjvPsFAiuhoyWEwtAsMVJE5VMuhW9icGtCElzTDIUwSdpZo+w0Xc8UGedd0OM 5k7ZEymegdQAaQwxvrGIpiWXhgJE7est0mLNEqkfbIP2ig5TLdY/2gJ X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Moduline Display platform is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. The base Moduline Display board includes a board-to-board connector with various busses to enable adding new display types required by the application. It includes 2 Moduline IO module slots, a simple mono codec/amplifier, a four channel adc, 2 CAN busses, an RTC and optional wifi/bluetooth. busses to the display adapter include: - 4 lane LVDS - 4 lane MIPI-DSI - 4 lane MIPI-CSI - HDMI 2.0a - USB 2.0 - I2S - I2C - SPI Also a couple of GPIO and PWM pins for controlling various ICs on the display adapter board. Signed-off-by: Maud Spierings --- .../imx8mp-tx8p-ml81-moduline-display-106.dts | 525 +++++++++++++++++= ++++ 1 file changed, 525 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display= -106.dts new file mode 100644 index 0000000000000000000000000000000000000000..0de49775a0bb2879d60956f8135= dd263eaab6c69 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.d= ts @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +/dts-v1/; + +#include "imx8mp-tx8p-ml81.dtsi" + +/ { + compatible =3D "gocontroll,moduline-display", "fsl,imx8mp"; + chassis-type =3D "embedded"; + hardware =3D "Moduline Display V1.06"; + + aliases { + can0 =3D &flexcan1; + can1 =3D &flexcan2; + ethernet0 =3D &eqos; + mmc0 =3D &usdhc3; + mmc1 =3D &usdhc2; + rtc0 =3D &rtc_pcf; /* i2c rtc is the main rtc */ + rtc1 =3D &snvs_rtc; + spi0 =3D &ecspi2; /* spidev number compatibility */ + spi1 =3D &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + external-sensor-supply { + compatible =3D "regulator-output"; + vout-supply =3D <®_5v0_sensor>; + }; + + reg_1v8_per: regulator-1v8-per { + compatible =3D "regulator-fixed"; + pinctrl-0 =3D <&pinctrl_reg_1v8>; + pinctrl-names =3D "default"; + power-supply =3D <®_3v3_per>; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "1v8-per"; + gpio =3D <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3v3_per: regulator-3v3-per { + compatible =3D "regulator-fixed"; + power-supply =3D <®_6v4>; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3-per"; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + power-supply =3D <®_6v4>; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "5v0"; + }; + + reg_5v0_sensor: regulator-5v0-sensor { + compatible =3D "regulator-fixed"; + pinctrl-0 =3D <&pinctrl_reg_5v0_sensor>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "5v0-supply-external-sensor"; + gpio =3D <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_6v4: regulator-6v4 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <6400000>; + regulator-min-microvolt =3D <6400000>; + regulator-name =3D "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible =3D "regulator-fixed"; + pinctrl-0 =3D <&pinctrl_flexcan1_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can1-stby"; + gpio =3D <&gpio4 3 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + pinctrl-0 =3D <&pinctrl_flexcan2_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can2-stby"; + gpio =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-master =3D <&cpudai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&cpudai>; + simple-audio-card,name =3D "tas2505-audio"; + simple-audio-card,routing =3D "Speaker", "DAC"; + simple-audio-card,widgets =3D "Speaker", "Speaker External"; + + simple-audio-card,codec { + sound-dai =3D <&tas2505>; + }; + + cpudai: simple-audio-card,cpu { + sound-dai =3D <&sai6>; + }; + }; + + wifi_powerseq: wifi-powerseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-0 =3D <&pinctrl_wl_reg>; + pinctrl-names =3D "default"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <500000>; + reset-gpios =3D <&gpio2 19 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + cs-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>, + <&gpio1 11 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_ecspi1>; + pinctrl-names =3D "default"; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <5 IRQ_TYPE_EDGE_FALLING>; + i2c-bus =3D <&i2c2>; + reset-gpios =3D <&gpio5 10 GPIO_ACTIVE_LOW>; + slot-number =3D <1>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio4 16 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_3v3_per>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + i2c-bus =3D <&i2c2>; + reset-gpios =3D <&gpio1 8 GPIO_ACTIVE_LOW>; + slot-number =3D <2>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio4 16 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_3v3_per>; + }; + + adc@2 { + compatible =3D "microchip,mcp3004"; + reg =3D <2>; + spi-max-frequency =3D <2300000>; + vref-supply =3D <®_vdd_3v3>; + }; +}; + +&flexcan1 { + pinctrl-0 =3D <&pinctrl_flexcan1>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_can1_stby>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-0 =3D <&pinctrl_flexcan2>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_can2_stby>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c4>; + pinctrl-1 =3D <&pinctrl_i2c4_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + tas2505: audio-codec@18 { + compatible =3D "ti,tas2505"; + reg =3D <0x18>; + clocks =3D <&clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>; + clock-names =3D "mclk"; + #sound-dai-cells =3D <0>; + aic32x4-gpio-func =3D <0xff 0xff 0xff 0xff 0xff>; + av-supply =3D <®_1v8_per>; + dv-supply =3D <®_1v8_per>; + iov-supply =3D <®_vdd_3v3>; + pinctrl-0 =3D <&pinctrl_tas_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio3 24 GPIO_ACTIVE_LOW>; + }; + + rtc_pcf: rtc@51 { + compatible =3D "nxp,pcf85063a"; + reg =3D <0x51>; + quartz-load-femtofarads =3D <7000>; + + clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 + MX8MP_DSE_X1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI + MX8MP_DSE_X4 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO + (MX8MP_DSE_X4 | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK + MX8MP_DSE_X4 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 + MX8MP_DSE_X1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART3_TXD__CAN2_RX + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART3_RXD__CAN2_TX + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 + MX8MP_I2C_DEFAULT + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 + MX8MP_I2C_DEFAULT + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_reg_1v8: reg-1v8-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 + MX8MP_DSE_X1 + >; + }; + + pinctrl_reg_5v0_sensor: reg-5v0-sensorgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 + MX8MP_DSE_X1 + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_tas_reset: tasresetgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 + MX8MP_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B + (MX8MP_DSE_X6 | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 + MX8MP_DSE_X1 + >; + }; +}; + +&sai6 { + assigned-clocks =3D <&clk IMX8MP_CLK_SAI6>; + assigned-clock-parents =3D <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates =3D <12288000>; + pinctrl-0 =3D <&pinctrl_sai6>; + pinctrl-names =3D "default"; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&pinctrl_uart1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&pinctrl_uart2>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + interrupt-parent =3D <&gpio1>; + interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + interrupt-names =3D "host-wakeup"; + device-wakeup-gpios =3D <&gpio1 15 GPIO_ACTIVE_HIGH>; + max-speed =3D <921600>; + pinctrl-0 =3D <&pinctrl_bt>; + pinctrl-names =3D "default"; + shutdown-gpios =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + vbat-supply =3D <®_3v3_per>; + vddio-supply =3D <®_3v3_per>; + }; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb3_phy1 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + dr_mode =3D "peripheral"; +}; + +&usdhc2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TIokKPYK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6050AC4AF16; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744700068; bh=t81Qw4Tdq4zyeXM0XoGcLedwtexGRTgw9YTa5p4hlw4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TIokKPYKzdIES7LeXP29mDsm5n5p7xYJblY/c+wpKozb+CYnNScGRUlo+cd1G5hD8 Jwjlq52Hg34hylva+JbMcEstRnOYanLVh7gJizIH96g1TxhL8mWniIffExaoUb62C5 rXkhhpQ+OZVg98t0v5RXJ5nMLae9QeLrtydx00N9kkRkQyPpdezkY15v2Un44qIF/D 2lmtX3v4vZTb9GvWauwSz1HPAr0JS2Mk9ZmkZQ34jybf8YF++rwQbfmIgDQ0T1k+sd i0o4j9OxZf6fSyUfsPFKgPdh8cXoltmxgJvsKuiPsaFKVFTPueZ67b9aoindGnzlGl EkkNcAeVWNdtA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 571E5C369B9; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Tue, 15 Apr 2025 08:54:30 +0200 Subject: [PATCH v5 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-7-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=4109; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=s+YSWWHZ/qWjR5g3Aj0fP/WU0u7E8mEW6X2vsCVzyKY=; b=w4aTIeB1PGcNKrtNZlrn6+QEL/R5AfdfAIuUND5G1muYX3zbuwVOEzhx+wpxdqp9p+b8FUr8l DjcCsD8C7JrBCvpsCUa/O8OVCvqIMPByAIPUVXLtpm0Hj1iKWrb6ZyF X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add the BOE av101hdt-a10 variant of the Moduline Display, this variant comes with a 10.1 1280x720 display with a touchscreen (not working in mainline). Signed-off-by: Maud Spierings Reviewed-by: Frank Li --- Currently the backlight driver is not available, this will be upstreamed in a future patch series. It is a Maxim max25014atg. The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as I know is not supported upstream, the driver we currently use for this is a mess and I doubt we will be able to get it in an upstreamable state. --- arch/arm64/boot/dts/freescale/Makefile | 5 ++ ...x8p-ml81-moduline-display-106-av101hdt-a10.dtso | 94 ++++++++++++++++++= ++++ 2 files changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index b6d3fe26d621234ab84353165d20af9d2536f839..ca3255aa9e18187b33d54c83699= 2aca5dd5d0465 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -214,6 +214,11 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revc-bd500.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revc-tian-g07017.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mp-ras314.dtb + +imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs +=3D imx8mp-tx8p-m= l81-moduline-display-106.dtb \ + imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tx8p-ml81-moduline-display-106-av101hdt= -a10.dtb + dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw72xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106-av101hdt-a10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-mo= duline-display-106-av101hdt-a10.dtso new file mode 100644 index 0000000000000000000000000000000000000000..b3bbbd69f671493c809bbf04380= 7a22adda5024a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-a= v101hdt-a10.dtso @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +#include +#include + +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + model =3D "GOcontroll Moduline Display with BOE av101hdt-a10 display"; + + panel { + compatible =3D "boe,av101hdt-a10"; + enable-gpios =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_panel>; + pinctrl-names =3D "default"; + power-supply =3D <®_3v3_per>; + reset-gpios =3D <&gpio1 9 GPIO_ACTIVE_LOW>; + + port { + panel_lvds_in: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + }; + + reg_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + power-supply =3D <®_6v4>; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "usb-c-vbus"; + }; +}; + +&iomuxc { + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 + MX8MP_DSE_X1 + >; + }; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + /* IMX8MP_VIDEO_PLL1 =3D IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates =3D <0>, <1054620000>; + status =3D "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint =3D <&panel_lvds_in>; + }; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + + connector { + compatible =3D "usb-c-connector"; + data-role =3D "host"; + pd-disable; + vbus-supply =3D <®_vbus>; + + port { + high_speed_ep: endpoint { + remote-endpoint =3D <&usb1_hs_ep>; + }; + }; + }; + + port { + usb1_hs_ep: endpoint { + remote-endpoint =3D <&high_speed_ep>; + }; + }; +}; --=20 2.49.0 From nobody Fri Dec 19 16:05:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017A02797A8; Tue, 15 Apr 2025 06:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744700069; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250415-initial_display-v5-8-f309f8d71499@gocontroll.com> References: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> In-Reply-To: <20250415-initial_display-v5-0-f309f8d71499@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings , Frank Li X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744700066; l=4676; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=LByPw/mrn8RNYJR8lwlP3ksUPIStEdKRG9cNVPBNlbg=; b=Haprc5ZGPJdAK4aRf7mhxTyB9H52YbUECVB0FoeaKrXsOtQKJQAoxvateeFNFNKwTJCy+gWDs /B7sHT+lityA4pdvwzlHx3zC+IZfDmbE0PZWSKKFUNQVg336hNz5ZLc X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add the BOE av123z7m-n17 variant of the Moduline Display, this variant comes with a 12.3" 1920x720 display. Reviewed-by: Frank Li Signed-off-by: Maud Spierings --- Currently the backlight driver is not available, this will be upstreamed in a future patch series. It is a Maxim max25014atg. --- arch/arm64/boot/dts/freescale/Makefile | 3 + ...x8p-ml81-moduline-display-106-av123z7m-n17.dtso | 139 +++++++++++++++++= ++++ 2 files changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index ca3255aa9e18187b33d54c836992aca5dd5d0465..c821f9eda332abd1db1867dab19= 6c09929316728 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -217,7 +217,10 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mp-ra= s314.dtb =20 imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs +=3D imx8mp-tx8p-m= l81-moduline-display-106.dtb \ imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo +imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17-dtbs +=3D imx8mp-tx8p-m= l81-moduline-display-106.dtb \ + imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tx8p-ml81-moduline-display-106-av101hdt= -a10.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tx8p-ml81-moduline-display-106-av123z7m= -n17.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw71xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106-av123z7m-n17.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-mo= duline-display-106-av123z7m-n17.dtso new file mode 100644 index 0000000000000000000000000000000000000000..c723d13b95a61fa5ff0e41516f8= a053f9d0b7768 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-a= v123z7m-n17.dtso @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +#include + +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + model =3D "GOcontroll Moduline Display with BOE av123z7m-n17 display"; + + panel { + compatible =3D "boe,av123z7m-n17"; + enable-gpios =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_panel>; + pinctrl-names =3D "default"; + power-supply =3D <®_3v3_per>; + reset-gpios =3D <&gpio1 9 GPIO_ACTIVE_LOW>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dual-lvds-odd-pixels; + + panel_in0: endpoint { + remote-endpoint =3D <&lvds1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dual-lvds-even-pixels; + + panel_in1: endpoint { + remote-endpoint =3D <&lvds0_out>; + }; + }; + }; + }; +}; + +&i2c4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* sn65dsi85 */ + bridge@2d { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2d>; + enable-gpios =3D <&gpio4 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_lvds_bridge>; + pinctrl-names =3D "default"; + vcc-supply =3D <®_1v8_per>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + + port@2 { + reg =3D <2>; + + lvds0_out: endpoint { + remote-endpoint =3D <&panel_in1>; + }; + }; + + port@3 { + reg =3D <3>; + + lvds1_out: endpoint { + remote-endpoint =3D <&panel_in0>; + }; + }; + }; + }; + + /* max25014 @ 0x6f */ +}; + +&iomuxc { + pinctrl_lvds_bridge: lvdsbridgegrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 + MX8MP_DSE_X1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 + MX8MP_DSE_X1 + >; + }; +}; + +&lcdif1 { + status =3D "okay"; +}; + +&mipi_dsi { + /* + * burst has to be at least 2x dsi clock that the sn65dsi85 expects + * display pixelclock * bpp / lanes / 2 =3D dsi clock + * 88.000.000 * 24 / 4 / 2 =3D 264.000.000 + * range gets rounded up to 265.000.000 - 270.000.000 + * 267.500.000 * 2 =3D 535.000.000 + */ + samsung,burst-clock-frequency =3D <535000000>; + samsung,esc-clock-frequency =3D <12000000>; + status =3D "okay"; + + ports { + port@1 { + mipi_dsi_out: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D < &dsi_lvds_bridge_in>; + }; + }; + }; +}; --=20 2.49.0