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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eae9780a0sm11003166f8f.50.2025.04.14.05.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Apr 2025 05:35:54 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE), linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST FRAMEWORK) Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Shuah Khan , Andrew Jones , Samuel Holland Subject: [PATCH 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Date: Mon, 14 Apr 2025 14:34:42 +0200 Message-ID: <20250414123543.1615478-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250414123543.1615478-1-cleger@rivosinc.com> References: <20250414123543.1615478-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We can safely reenable IRQs if they were enabled in the previous context. This allows to access user memory that could potentially trigger a page fault. Fixes: b686ecdeacf6 ("riscv: misaligned: Restrict user access to kernel mem= ory") Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/traps.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 55d9f3450398..3eecc2addc41 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -206,6 +206,11 @@ enum misaligned_access_type { static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_acces= s_type type) { irqentry_state_t state =3D irqentry_enter(regs); + bool enable_irqs =3D !regs_irqs_disabled(regs); + + /* Enable interrupts if they were enabled in the interrupted context. */ + if (enable_irqs) + local_irq_enable(); =20 if (type =3D=3D MISALIGNED_LOAD) { if (handle_misaligned_load(regs)) @@ -217,6 +222,9 @@ static void do_trap_misaligned(struct pt_regs *regs, en= um misaligned_access_type "Oops - store (or AMO) address misaligned"); } =20 + if (enable_irqs) + local_irq_disable(); + irqentry_exit(regs, state); } =20 --=20 2.49.0