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client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF00000209.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Mon, 14 Apr 2025 03:23:28 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 13 Apr 2025 22:23:26 -0500 Received: from xhdlc201369.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Sun, 13 Apr 2025 22:23:14 -0500 From: Sai Krishna Musham To: , , , , , , , CC: , , , , , , Subject: [RESEND PATCH v7 1/2] dt-bindings: PCI: xilinx-cpm: Add `cpm_crx` and `cpm5nc_fw_attr` properties Date: Mon, 14 Apr 2025 08:53:03 +0530 Message-ID: <20250414032304.862779-2-sai.krishna.musham@amd.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20250414032304.862779-1-sai.krishna.musham@amd.com> References: <20250414032304.862779-1-sai.krishna.musham@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: sai.krishna.musham@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|SA1PR12MB7341:EE_ X-MS-Office365-Filtering-Correlation-Id: bc404962-353b-4e12-9521-08dd7b03b965 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 03:23:28.0632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc404962-353b-4e12-9521-08dd7b03b965 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7341 Content-Type: text/plain; charset="utf-8" Add the `cpm_crx` property to manage the PCIe IP reset, and `cpm5nc_fw_attr` property to clear firewall after link reset, while maintaining backward compatibility with existing device trees. Also, incorporate `reset-gpios` in example for GPIO-based handling of the PCIe Root Port (RP) PERST# signal for enabling assert and deassert control. The `reset-gpios` and `cpm_crx` properties must be provided for CPM, CPM5 and CPM5_HOST1. For CPM5NC, all three properties - `reset-gpios`, `cpm_crx` and `cpm5nc_fw_attr` must be explicitly defined to ensure proper functionality. Include an example DTS node and complete the binding documentation for CPM5NC. Also, fix the bridge register address size in the example for CPM5. Signed-off-by: Sai Krishna Musham --- Changes for v7: - Update CPM5NC device tree binding. - Add CPM5NC device tree example node. - Update commit message. Changes for v6: - Resolve ABI break. - Update commit message. Changes for v5: - Remove `reset-gpios` property from required as it is already present in pci-bus-common.yaml - Update commit message Changes for v4: - Add CPM clock and reset control registers base to handle PCIe IP reset. - Update commit message. Changes for v3: - None Changes for v2: - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity - Update commit message --- .../bindings/pci/xilinx-versal-cpm.yaml | 129 +++++++++++++++--- 1 file changed, 109 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b= /Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index d674a24c8ccc..ed07896f763e 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -9,9 +9,6 @@ title: CPM Host Controller device tree for Xilinx Versal So= Cs maintainers: - Bharat Kumar Gogada =20 -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - properties: compatible: enum: @@ -21,18 +18,12 @@ properties: - xlnx,versal-cpm5nc-host =20 reg: - items: - - description: CPM system level control and status registers. - - description: Configuration space region and bridge registers. - - description: CPM5 control and status registers. minItems: 2 + maxItems: 4 =20 reg-names: - items: - - const: cpm_slcr - - const: cfg - - const: cpm_csr minItems: 2 + maxItems: 4 =20 interrupts: maxItems: 1 @@ -64,18 +55,94 @@ properties: required: - reg - reg-names - - "#interrupt-cells" - - interrupts - - interrupt-map - - interrupt-map-mask - bus-range - msi-map - - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-cpm-host-1.00 + then: + properties: + reg: + items: + - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. + - description: CPM clock and reset control registers. + minItems: 2 + reg-names: + items: + - const: cpm_slcr + - const: cfg + - const: cpm_crx + minItems: 2 + required: + - "#interrupt-cells" + - interrupts + - interrupt-map + - interrupt-map-mask + - interrupt-controller + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-cpm5-host + - xlnx,versal-cpm5-host1 + then: + properties: + reg: + items: + - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. + - description: CPM5 control and status registers. + - description: CPM clock and reset control registers. + minItems: 3 + reg-names: + items: + - const: cpm_slcr + - const: cfg + - const: cpm_csr + - const: cpm_crx + minItems: 3 + required: + - "#interrupt-cells" + - interrupts + - interrupt-map + - interrupt-map-mask + - interrupt-controller + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-cpm5nc-host + then: + properties: + reg: + items: + - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. + - description: CPM clock and reset control registers. + - description: CPM5NC Firewall attribute register. + minItems: 2 + reg-names: + items: + - const: cpm_slcr + - const: cfg + - const: cpm_crx + - const: cpm5nc_fw_attr + minItems: 2 =20 unevaluatedProperties: false =20 examples: - | + #include =20 versal { #address-cells =3D <2>; @@ -98,8 +165,10 @@ examples: <0x43000000 0x80 0x00000000 0x80 0x0000000= 0 0x0 0x80000000>; msi-map =3D <0x0 &its_gic 0x0 0x10000>; reg =3D <0x0 0xfca10000 0x0 0x1000>, - <0x6 0x00000000 0x0 0x10000000>; - reg-names =3D "cpm_slcr", "cfg"; + <0x6 0x00000000 0x0 0x10000000>, + <0x0 0xfca00000 0x0 10000>; + reg-names =3D "cpm_slcr", "cfg", "cpm_crx"; + reset-gpios =3D <&gpio1 38 GPIO_ACTIVE_LOW>; pcie_intc_0: interrupt-controller { #address-cells =3D <0>; #interrupt-cells =3D <1>; @@ -126,8 +195,10 @@ examples: msi-map =3D <0x0 &its_gic 0x0 0x10000>; reg =3D <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, - <0x00 0xfce20000 0x00 0x1000000>; - reg-names =3D "cpm_slcr", "cfg", "cpm_csr"; + <0x00 0xfce20000 0x00 0x10000>, + <0x00 0xfcdc0000 0x00 0x10000>; + reg-names =3D "cpm_slcr", "cfg", "cpm_csr", "cpm_cr= x"; + reset-gpios =3D <&gpio1 38 GPIO_ACTIVE_LOW>; =20 pcie_intc_1: interrupt-controller { #address-cells =3D <0>; @@ -136,4 +207,22 @@ examples: }; }; =20 + cpm5nc_pcie: pcie@e4a10000 { + compatible =3D "xlnx,versal-cpm5nc-host"; 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Sun, 13 Apr 2025 22:23:30 -0500 Received: from xhdlc201369.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Sun, 13 Apr 2025 22:23:27 -0500 From: Sai Krishna Musham To: , , , , , , , CC: , , , , , , Subject: [RESEND PATCH v7 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal Date: Mon, 14 Apr 2025 08:53:04 +0530 Message-ID: <20250414032304.862779-3-sai.krishna.musham@amd.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20250414032304.862779-1-sai.krishna.musham@amd.com> References: <20250414032304.862779-1-sai.krishna.musham@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: sai.krishna.musham@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000205:EE_|CH2PR12MB4152:EE_ X-MS-Office365-Filtering-Correlation-Id: dd3db3e8-fa1d-4db2-6812-08dd7b03bbc5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 03:23:32.0467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd3db3e8-fa1d-4db2-6812-08dd7b03bbc5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000205.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4152 Content-Type: text/plain; charset="utf-8" Add support for handling the PCIe Root Port (RP) PERST# signal using the GPIO framework, along with the PCIe IP reset. This reset is managed by the driver and occurs after the Initial Power Up sequence (PCIe CEM r6.0, 2.2.1) is handled in hardware before the driver's probe function is called. This reset mechanism is particularly useful in warm reset scenarios, where the power rails remain stable and only PERST# signal is toggled through the driver. Applying both the PCIe IP reset and the PERST# improves the reliability of the reset process by ensuring that both the Root Port controller and the Endpoint are reset synchronously and avoid lane errors. Adapt the implementation to use the GPIO framework for reset signal handling and make this reset handling optional, along with the `cpm_crx` property, to maintain backward compatibility with existing device tree binaries (DTBs). Additionally, clear Firewall after the link reset for CPM5NC to allow further PCIe transactions. Signed-off-by: Sai Krishna Musham --- Changes for v7: - Use platform_get_resource_byname() to make cpm_crx and cpm5nc_fw_attr optional - Use 100us delay T_PERST as per PCIe spec before PERST# deassert. Changes for v6: - Correct version check condition of CPM5NC_HOST. Changes for v5: - Handle probe defer for reset_gpio. - Resolve ABI break. Changes for v4: - Add PCIe PERST# support for CPM5NC. - Add PCIe IP reset along with PERST# to avoid Link Training Errors. - Remove PCIE_T_PVPERL_MS define and PCIE_T_RRS_READY_MS after PERST# deassert. - Move PCIe PERST# assert and deassert logic to xilinx_cpm_pcie_init_port() before cpm_pcie_link_up(), since Interrupts enable and PCIe RP bridge enable should be done after Link up. - Update commit message. Changes for v3: - Use PCIE_T_PVPERL_MS define. Changes for v2: - Make the request GPIO optional. - Correct the reset sequence as per PERST# - Update commit message --- drivers/pci/controller/pcie-xilinx-cpm.c | 97 +++++++++++++++++++++++- 1 file changed, 94 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/control= ler/pcie-xilinx-cpm.c index 13ca493d22bd..c46642417d52 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -6,6 +6,8 @@ */ =20 #include +#include +#include #include #include #include @@ -21,6 +23,13 @@ #include "pcie-xilinx-common.h" =20 /* Register definitions */ +#define XILINX_CPM_PCIE0_RST 0x00000308 +#define XILINX_CPM5_PCIE0_RST 0x00000318 +#define XILINX_CPM5_PCIE1_RST 0x0000031C +#define XILINX_CPM5NC_PCIE0_RST 0x00000324 + +#define XILINX_CPM5NC_PCIE0_FRWALL 0x00000140 + #define XILINX_CPM_PCIE_REG_IDR 0x00000E10 #define XILINX_CPM_PCIE_REG_IMR 0x00000E14 #define XILINX_CPM_PCIE_REG_PSCR 0x00000E1C @@ -93,12 +102,16 @@ enum xilinx_cpm_version { * @ir_status: Offset for the error interrupt status register * @ir_enable: Offset for the CPM5 local error interrupt enable register * @ir_misc_value: A bitmask for the miscellaneous interrupt status + * @cpm_pcie_rst: Offset for the PCIe IP reset + * @cpm5nc_fw_rst: Offset for the CPM5NC Firewall */ struct xilinx_cpm_variant { enum xilinx_cpm_version version; u32 ir_status; u32 ir_enable; u32 ir_misc_value; + u32 cpm_pcie_rst; + u32 cpm5nc_fw_rst; }; =20 /** @@ -106,6 +119,8 @@ struct xilinx_cpm_variant { * @dev: Device pointer * @reg_base: Bridge Register Base * @cpm_base: CPM System Level Control and Status Register(SLCR) Base + * @crx_base: CPM Clock and Reset Control Registers Base + * @cpm5nc_fw_base: CPM5NC Firewall Attribute Base * @intx_domain: Legacy IRQ domain pointer * @cpm_domain: CPM IRQ domain pointer * @cfg: Holds mappings of config space window @@ -118,6 +133,8 @@ struct xilinx_cpm_pcie { struct device *dev; void __iomem *reg_base; void __iomem *cpm_base; + void __iomem *crx_base; + void __iomem *cpm5nc_fw_base; struct irq_domain *intx_domain; struct irq_domain *cpm_domain; struct pci_config_window *cfg; @@ -475,12 +492,57 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pci= e *port) * xilinx_cpm_pcie_init_port - Initialize hardware * @port: PCIe port information */ -static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) +static int xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { const struct xilinx_cpm_variant *variant =3D port->variant; + struct device *dev =3D port->dev; + struct gpio_desc *reset_gpio; + bool do_reset =3D false; + + if (port->crx_base && (variant->version < CPM5NC_HOST || + (variant->version =3D=3D CPM5NC_HOST && + port->cpm5nc_fw_base))) { + /* Request the GPIO for PCIe reset signal and assert */ + reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset_gpio)) + return dev_err_probe(dev, PTR_ERR(reset_gpio), + "Failed to request reset GPIO\n"); + if (reset_gpio) + do_reset =3D true; + } + + if (do_reset) { + /* Assert the PCIe IP reset */ + writel_relaxed(0x1, port->crx_base + variant->cpm_pcie_rst); + + /* + * "PERST# active time", as per Table 2-10: Power Sequencing + * and Reset Signal Timings of the PCIe Electromechanical + * Specification, Revision 6.0, symbol "T_PERST". + */ + udelay(100); + + /* Deassert the PCIe IP reset */ + writel_relaxed(0x0, port->crx_base + variant->cpm_pcie_rst); + + /* Deassert the reset signal */ + gpiod_set_value(reset_gpio, 0); + mdelay(PCIE_T_RRS_READY_MS); + + if (variant->version =3D=3D CPM5NC_HOST && + port->cpm5nc_fw_base) { + /* Clear Firewall */ + writel_relaxed(0x00, port->cpm5nc_fw_base + + variant->cpm5nc_fw_rst); + writel_relaxed(0x01, port->cpm5nc_fw_base + + variant->cpm5nc_fw_rst); + writel_relaxed(0x00, port->cpm5nc_fw_base + + variant->cpm5nc_fw_rst); + } + } =20 if (variant->version =3D=3D CPM5NC_HOST) - return; + return 0; =20 if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); @@ -512,6 +574,8 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm= _pcie *port) pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | XILINX_CPM_PCIE_REG_RPSC_BEN, XILINX_CPM_PCIE_REG_RPSC); + + return 0; } =20 /** @@ -552,6 +616,24 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_= pcie *port, port->reg_base =3D port->cfg->win; } =20 + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpm_crx"); + if (res) { + port->crx_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(port->crx_base)) + return PTR_ERR(port->crx_base); + } + + if (port->variant->version =3D=3D CPM5NC_HOST) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, + "cpm5nc_fw_attr"); + if (res) { + port->cpm5nc_fw_base =3D + devm_ioremap_resource(dev, res); + if (IS_ERR(port->cpm5nc_fw_base)) + return PTR_ERR(port->cpm5nc_fw_base); + } + } + return 0; } =20 @@ -603,7 +685,11 @@ static int xilinx_cpm_pcie_probe(struct platform_devic= e *pdev) goto err_free_irq_domains; } =20 - xilinx_cpm_pcie_init_port(port); + err =3D xilinx_cpm_pcie_init_port(port); + if (err) { + dev_err(dev, "Init port failed\n"); + goto err_setup_irq; + } =20 if (port->variant->version !=3D CPM5NC_HOST) { err =3D xilinx_cpm_setup_irq(port); @@ -636,6 +722,7 @@ static int xilinx_cpm_pcie_probe(struct platform_device= *pdev) static const struct xilinx_cpm_variant cpm_host =3D { .version =3D CPM, .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, + .cpm_pcie_rst =3D XILINX_CPM_PCIE0_RST, }; =20 static const struct xilinx_cpm_variant cpm5_host =3D { @@ -643,6 +730,7 @@ static const struct xilinx_cpm_variant cpm5_host =3D { .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, .ir_status =3D XILINX_CPM_PCIE0_IR_STATUS, .ir_enable =3D XILINX_CPM_PCIE0_IR_ENABLE, + .cpm_pcie_rst =3D XILINX_CPM5_PCIE0_RST, }; =20 static const struct xilinx_cpm_variant cpm5_host1 =3D { @@ -650,10 +738,13 @@ static const struct xilinx_cpm_variant cpm5_host1 =3D= { .ir_misc_value =3D XILINX_CPM_PCIE1_MISC_IR_LOCAL, .ir_status =3D XILINX_CPM_PCIE1_IR_STATUS, .ir_enable =3D XILINX_CPM_PCIE1_IR_ENABLE, + .cpm_pcie_rst =3D XILINX_CPM5_PCIE1_RST, }; =20 static const struct xilinx_cpm_variant cpm5n_host =3D { .version =3D CPM5NC_HOST, + .cpm_pcie_rst =3D XILINX_CPM5NC_PCIE0_RST, + .cpm5nc_fw_rst =3D XILINX_CPM5NC_PCIE0_FRWALL, }; =20 static const struct of_device_id xilinx_cpm_pcie_of_match[] =3D { --=20 2.44.1