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Signed-off-by: Melody Olvera Acked-by: Conor Dooley --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index e5effbb4a606b1ba2d9507b6ca72cd1bdff51344..37e3ebd554874f0fbbb8956a718= dcb717ee82155 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc - qcom,x1e80100-llcc =20 reg: @@ -274,6 +275,7 @@ allOf: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc then: properties: reg: --=20 2.48.1 From nobody Fri Dec 19 16:10:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC5C41FDE0E for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b02a3221c7bsm9746298a12.71.2025.04.14.16.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Apr 2025 16:22:15 -0700 (PDT) From: Melody Olvera Date: Mon, 14 Apr 2025 16:21:51 -0700 Subject: [PATCH v4 2/4] soc: qcom: llcc-qcom: Add support for LLCC V6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250414-sm8750_llcc_master-v4-2-e007f035380c@oss.qualcomm.com> References: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> In-Reply-To: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Satya Durga Srinivasu Prabhala , Trilok Soni Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744672932; l=10510; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=xw9iTAYW3wAWgA6jz5SdeA8HGg3RiSjVSAOIj/JJ6IA=; b=KTsnT/65d7GETxZPC3aZ+QwA8hI3dQ3hFSXoTm+xOd5h7zWLAcgYKlSuBidRNBNNetKl/NQez bFWlotYr/fHAVVrHKLD4iXS6jq71Mnf7Ux0iWBc/iRiJBM3afW5YgW/ X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-ORIG-GUID: d_5ycgY62s0ZRsQvvz9gpI9ULsERBAtv X-Proofpoint-GUID: d_5ycgY62s0ZRsQvvz9gpI9ULsERBAtv X-Authority-Analysis: v=2.4 cv=ANaQCy7k c=1 sm=1 tr=0 ts=67fd98a9 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=kuZnfz22bkT2hUSTrGIA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140168 Add support for LLCC V6. V6 adds several additional usecase IDs, rearrages several registers and offsets, and supports slice IDs over 31, so add a new function for programming LLCC V6. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/llcc-qcom.c | 224 +++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 220 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 56823b6a2facc4345265e29b60da24a391e3707d..cadf7e70ee03cd65d125276eccd= e5c9f0851e111 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -35,6 +35,11 @@ #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) #define ATTR0_BONUS_WAYS_SHIFT 16 +#define ATTR2_PROBE_TARGET_WAYS_MASK BIT(4) +#define ATTR2_FIXED_SIZE_MASK BIT(8) +#define ATTR2_PRIORITY_MASK GENMASK(14, 12) +#define ATTR2_PARENT_SCID_MASK GENMASK(21, 16) +#define ATTR2_IN_A_GROUP_MASK BIT(24) #define LLCC_STATUS_READ_DELAY 100 =20 #define CACHE_LINE_SIZE_SHIFT 6 @@ -49,6 +54,10 @@ #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) +#define LLCC_V6_TRP_ATTR0_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR0_CFG]= + SZ_64 * n) +#define LLCC_V6_TRP_ATTR1_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR1_CFG]= + SZ_64 * n) +#define LLCC_V6_TRP_ATTR2_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR2_CFG]= + SZ_64 * n) +#define LLCC_V6_TRP_ATTR3_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR3_CFG]= + SZ_64 * n) =20 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 @@ -66,6 +75,7 @@ #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 +#define LLCC_VERSION_6_0_0_0 0X06000000 =20 /** * struct llcc_slice_config - Data associated with the llcc slice @@ -106,6 +116,7 @@ * ovcap_en. * @vict_prio: When current scid is under-capacity, allocate over other * lower-than victim priority-line threshold scid. + * @parent_slice_id: For grouped slices, specifies the slice id of the par= ent. */ struct llcc_slice_config { u32 usecase_id; @@ -130,6 +141,7 @@ struct llcc_slice_config { bool ovcap_en; bool ovcap_prio; bool vict_prio; + u32 parent_slice_id; }; =20 struct qcom_llcc_config { @@ -153,6 +165,21 @@ struct qcom_sct_config { enum llcc_reg_offset { LLCC_COMMON_HW_INFO, LLCC_COMMON_STATUS0, + LLCC_TRP_ATTR0_CFG, + LLCC_TRP_ATTR1_CFG, + LLCC_TRP_ATTR2_CFG, + LLCC_TRP_ATTR3_CFG, + LLCC_TRP_SID_DIS_CAP_ALLOC, + LLCC_TRP_ALGO_STALE_EN, + LLCC_TRP_ALGO_STALE_CAP_EN, + LLCC_TRP_ALGO_MRU0, + LLCC_TRP_ALGO_MRU1, + LLCC_TRP_ALGO_ALLOC0, + LLCC_TRP_ALGO_ALLOC1, + LLCC_TRP_ALGO_ALLOC2, + LLCC_TRP_ALGO_ALLOC3, + LLCC_TRP_WRS_EN, + LLCC_TRP_WRS_CACHEABLE_EN, }; =20 static const struct llcc_slice_config ipq5424_data[] =3D { @@ -3161,6 +3188,33 @@ static const struct llcc_edac_reg_offset llcc_v2_1_e= dac_reg_offset =3D { .drp_ecc_db_err_syn0 =3D 0x52120, }; =20 +static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset =3D { + .trp_ecc_error_status0 =3D 0x47448, + .trp_ecc_error_status1 =3D 0x47450, + .trp_ecc_sb_err_syn0 =3D 0x47490, + .trp_ecc_db_err_syn0 =3D 0x474d0, + .trp_ecc_error_cntr_clear =3D 0x47444, + .trp_interrupt_0_status =3D 0x47600, + .trp_interrupt_0_clear =3D 0x47604, + .trp_interrupt_0_enable =3D 0x47608, + + /* LLCC Common registers */ + .cmn_status0 =3D 0x6400c, + .cmn_interrupt_0_enable =3D 0x6401c, + .cmn_interrupt_2_enable =3D 0x6403c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg =3D 0x80000, + .drp_ecc_error_cntr_clear =3D 0x80004, + .drp_interrupt_status =3D 0x80020, + .drp_interrupt_clear =3D 0x80028, + .drp_interrupt_enable =3D 0x8002c, + .drp_ecc_error_status0 =3D 0x820f4, + .drp_ecc_error_status1 =3D 0x820f8, + .drp_ecc_sb_err_syn0 =3D 0x820fc, + .drp_ecc_db_err_syn0 =3D 0x82120, +}; + /* LLCC register offset starting from v1.0.0 */ static const u32 llcc_v1_reg_offset[] =3D { [LLCC_COMMON_HW_INFO] =3D 0x00030000, @@ -3173,6 +3227,27 @@ static const u32 llcc_v2_1_reg_offset[] =3D { [LLCC_COMMON_STATUS0] =3D 0x0003400c, }; =20 +/* LLCC register offset starting from v6.0.0 */ +static const u32 llcc_v6_reg_offset[] =3D { + [LLCC_COMMON_HW_INFO] =3D 0x00064000, + [LLCC_COMMON_STATUS0] =3D 0x0006400c, + [LLCC_TRP_ATTR0_CFG] =3D 0x00041000, + [LLCC_TRP_ATTR1_CFG] =3D 0x00041008, + [LLCC_TRP_ATTR2_CFG] =3D 0x00041010, + [LLCC_TRP_ATTR3_CFG] =3D 0x00041014, + [LLCC_TRP_SID_DIS_CAP_ALLOC] =3D 0x00042000, + [LLCC_TRP_ALGO_STALE_EN] =3D 0x00042008, + [LLCC_TRP_ALGO_STALE_CAP_EN] =3D 0x00042010, + [LLCC_TRP_ALGO_MRU0] =3D 0x00042018, + [LLCC_TRP_ALGO_MRU1] =3D 0x00042020, + [LLCC_TRP_ALGO_ALLOC0] =3D 0x00042028, + [LLCC_TRP_ALGO_ALLOC1] =3D 0x00042030, + [LLCC_TRP_ALGO_ALLOC2] =3D 0x00042038, + [LLCC_TRP_ALGO_ALLOC3] =3D 0x00042040, + [LLCC_TRP_WRS_EN] =3D 0x00042080, + [LLCC_TRP_WRS_CACHEABLE_EN] =3D 0x00042088, +}; + static const struct qcom_llcc_config qcs615_cfg[] =3D { { .sct_data =3D qcs615_data, @@ -3869,6 +3944,139 @@ static int _qcom_llcc_cfg_program(const struct llcc= _slice_config *config, return ret; } =20 +static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *confi= g, + const struct qcom_llcc_config *cfg) +{ + u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover; + u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio; + u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg; + u32 attr0_val, attr1_val, attr2_val, attr3_val; + u32 slice_offset, reg_offset; + struct llcc_slice_desc *desc; + u32 wren, wr_cache_en; + int ret; + + attr0_cfg =3D LLCC_V6_TRP_ATTR0_CFGn(config->slice_id); + attr1_cfg =3D LLCC_V6_TRP_ATTR1_CFGn(config->slice_id); + attr2_cfg =3D LLCC_V6_TRP_ATTR2_CFGn(config->slice_id); + attr3_cfg =3D LLCC_V6_TRP_ATTR3_CFGn(config->slice_id); + + attr0_val =3D config->res_ways; + attr1_val =3D config->bonus_ways; + attr2_val =3D config->cache_mode; + attr2_val |=3D FIELD_PREP(ATTR2_PROBE_TARGET_WAYS_MASK, config->probe_tar= get_ways); + attr2_val |=3D FIELD_PREP(ATTR2_FIXED_SIZE_MASK, config->fixed_size); + attr2_val |=3D FIELD_PREP(ATTR2_PRIORITY_MASK, config->priority); + + if (config->parent_slice_id && config->fixed_size) { + attr2_val |=3D FIELD_PREP(ATTR2_PARENT_SCID_MASK, config->parent_slice_i= d); + attr2_val |=3D ATTR2_IN_A_GROUP_MASK; + } + + attr3_val =3D MAX_CAP_TO_BYTES(config->max_cap); + attr3_val /=3D drv_data->num_banks; + attr3_val >>=3D CACHE_LINE_SIZE_SHIFT; + + ret =3D regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); + if (ret) + return ret; + + ret =3D regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); + if (ret) + return ret; + + ret =3D regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); + if (ret) + return ret; + + ret =3D regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val); + if (ret) + return ret; + + slice_offset =3D config->slice_id % 32; + reg_offset =3D (config->slice_id / 32) * 4; + + wren =3D config->write_scid_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_WRS_EN] + reg_offset, + BIT(slice_offset), wren); + if (ret) + return ret; + + wr_cache_en =3D config->write_scid_cacheable_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_WRS_CACHEABLE_EN] + reg_offset, + BIT(slice_offset), wr_cache_en); + if (ret) + return ret; + + stale_en =3D config->stale_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_STALE_EN] + reg_offset, + BIT(slice_offset), stale_en); + if (ret) + return ret; + + stale_cap_en =3D config->stale_cap_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_STALE_CAP_EN] + reg_offset, + BIT(slice_offset), stale_cap_en); + if (ret) + return ret; + + mru_uncap_en =3D config->mru_uncap_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_MRU0] + reg_offset, + BIT(slice_offset), mru_uncap_en); + if (ret) + return ret; + + mru_rollover =3D config->mru_rollover << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_MRU1] + reg_offset, + BIT(slice_offset), mru_rollover); + if (ret) + return ret; + + alloc_oneway_en =3D config->alloc_oneway_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC0] + reg_offset, + BIT(slice_offset), alloc_oneway_en); + if (ret) + return ret; + + ovcap_en =3D config->ovcap_en << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC1] + reg_offset, + BIT(slice_offset), ovcap_en); + if (ret) + return ret; + + ovcap_prio =3D config->ovcap_prio << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC2] + reg_offset, + BIT(slice_offset), ovcap_prio); + if (ret) + return ret; + + vict_prio =3D config->vict_prio << slice_offset; + ret =3D regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC3] + reg_offset, + BIT(slice_offset), vict_prio); + if (ret) + return ret; + + if (config->activate_on_init) { + desc =3D llcc_slice_getd(config->usecase_id); + if (PTR_ERR_OR_ZERO(desc)) + return -EINVAL; + + ret =3D llcc_slice_activate(desc); + } + + return ret; +} + static int qcom_llcc_cfg_program(struct platform_device *pdev, const struct qcom_llcc_config *cfg) { @@ -3880,10 +4088,18 @@ static int qcom_llcc_cfg_program(struct platform_de= vice *pdev, sz =3D drv_data->cfg_size; llcc_table =3D drv_data->cfg; =20 - for (i =3D 0; i < sz; i++) { - ret =3D _qcom_llcc_cfg_program(&llcc_table[i], cfg); - if (ret) - return ret; + if (drv_data->version >=3D LLCC_VERSION_6_0_0_0) { + for (i =3D 0; i < sz; i++) { + ret =3D _qcom_llcc_cfg_program_v6(&llcc_table[i], cfg); + if (ret) + return ret; + } + } else { + for (i =3D 0; i < sz; i++) { + ret =3D _qcom_llcc_cfg_program(&llcc_table[i], cfg); + if (ret) + return ret; + } } =20 return ret; --=20 2.48.1 From nobody Fri Dec 19 16:10:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A32C2202C2D for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b02a3221c7bsm9746298a12.71.2025.04.14.16.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Apr 2025 16:22:16 -0700 (PDT) From: Melody Olvera Date: Mon, 14 Apr 2025 16:21:52 -0700 Subject: [PATCH v4 3/4] soc: qcom: llcc-qcom: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250414-sm8750_llcc_master-v4-3-e007f035380c@oss.qualcomm.com> References: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> In-Reply-To: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Satya Durga Srinivasu Prabhala , Trilok Soni Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744672932; l=8532; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=dVTafZM7nNrW0odwI9sCmW7II903oWKn/0+UscbW7lY=; b=SJbH+tgiqm/keD73jUs2xRJ/EpUHPbQafH4AOaev8RXaNpHvRGhz0u3CEANPZR091k7WmCWK0 svZNkh4AJ7xD9rFyCq+vVZfs4AdFbyvUjBczm1/6W1syU7FOI7iFu0Y X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Authority-Analysis: v=2.4 cv=E9TNpbdl c=1 sm=1 tr=0 ts=67fd98ab cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=zHNgQWnGFwCULUzyGxAA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: aGwFf6eJvQn0CX33wU_EeZrSsZHtJTuz X-Proofpoint-GUID: aGwFf6eJvQn0CX33wU_EeZrSsZHtJTuz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140168 Add system cache table and configs for SM8750 SoCs. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/llcc-qcom.c | 273 +++++++++++++++++++++++++++++++++= ++++ include/linux/soc/qcom/llcc-qcom.h | 8 ++ 2 files changed, 281 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index cadf7e70ee03cd65d125276eccde5c9f0851e111..b5290655d181f9d3579386eb4fc= 7cce41c4a349d 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -2689,6 +2689,263 @@ static const struct llcc_slice_config sm8650_data[]= =3D { }, }; =20 +static const struct llcc_slice_config sm8750_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 5120, + .priority =3D 1, + .bonus_ways =3D 0xffffffff, + .activate_on_init =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MDMHPFX, + .slice_id =3D 24, + .max_cap =3D 1024, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 512, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 35, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_MDMHPGRW, + .slice_id =3D 25, + .max_cap =3D 1024, + .priority =3D 5, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_MODHW, + .slice_id =3D 26, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 34, + .max_cap =3D 4096, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 9, + .max_cap =3D 5632, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .write_scid_en =3D true, + .write_scid_cacheable_en =3D true + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 18, + .max_cap =3D 768, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 7168, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .cache_mode =3D 2, + .stale_en =3D true, + }, { + .usecase_id =3D LLCC_VIDFW, + .slice_id =3D 17, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_CAMFW, + .slice_id =3D 20, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_MDMPNG, + .slice_id =3D 27, + .max_cap =3D 256, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0xf0000000, + }, { + .usecase_id =3D LLCC_AUDHW, + .slice_id =3D 22, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_CVP, + .slice_id =3D 8, + .max_cap =3D 800, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .vict_prio =3D true, + }, { + .usecase_id =3D LLCC_MODPE, + .slice_id =3D 29, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xf0000000, + .alloc_oneway_en =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_CVPFW, + .slice_id =3D 19, + .max_cap =3D 64, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_CMPTHCP, + .slice_id =3D 15, + .max_cap =3D 256, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_LCPDARE, + .slice_id =3D 30, + .max_cap =3D 128, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .activate_on_init =3D true, + .alloc_oneway_en =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 3, + .max_cap =3D 3072, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .cache_mode =3D 2, + }, { + .usecase_id =3D LLCC_ISLAND1, + .slice_id =3D 12, + .max_cap =3D 7936, + .priority =3D 7, + .fixed_size =3D true, + .bonus_ways =3D 0x7fffffff, + }, { + .usecase_id =3D LLCC_DISP_WB, + .slice_id =3D 23, + .max_cap =3D 512, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_VIDVSP, + .slice_id =3D 4, + .max_cap =3D 256, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + }, { + .usecase_id =3D LLCC_VIDDEC, + .slice_id =3D 5, + .max_cap =3D 6144, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .cache_mode =3D 2, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CAMOFE, + .slice_id =3D 33, + .max_cap =3D 6144, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .stale_en =3D true, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CAMRTIP, + .slice_id =3D 13, + .max_cap =3D 1024, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .stale_en =3D true, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CAMSRTIP, + .slice_id =3D 14, + .max_cap =3D 6144, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .stale_en =3D true, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CAMRTRF, + .slice_id =3D 7, + .max_cap =3D 3584, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .stale_en =3D true, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CAMSRTRF, + .slice_id =3D 21, + .max_cap =3D 6144, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .stale_en =3D true, + .ovcap_prio =3D true, + .parent_slice_id =3D 33, + }, { + .usecase_id =3D LLCC_CPUSSMPAM, + .slice_id =3D 6, + .max_cap =3D 2048, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0xffffffff, + .activate_on_init =3D true, + .write_scid_en =3D true, + }, +}; + static const struct llcc_slice_config qcs615_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -3454,6 +3711,16 @@ static const struct qcom_llcc_config sm8650_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config sm8750_cfg[] =3D { + { + .sct_data =3D sm8750_data, + .size =3D ARRAY_SIZE(sm8750_data), + .skip_llcc_cfg =3D false, + .reg_offset =3D llcc_v6_reg_offset, + .edac_reg_offset =3D &llcc_v6_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config x1e80100_cfg[] =3D { { .sct_data =3D x1e80100_data, @@ -3564,6 +3831,11 @@ static const struct qcom_sct_config sm8650_cfgs =3D { .num_config =3D ARRAY_SIZE(sm8650_cfg), }; =20 +static const struct qcom_sct_config sm8750_cfgs =3D { + .llcc_config =3D sm8750_cfg, + .num_config =3D ARRAY_SIZE(sm8750_cfg), +}; + static const struct qcom_sct_config x1e80100_cfgs =3D { .llcc_config =3D x1e80100_cfg, .num_config =3D ARRAY_SIZE(x1e80100_cfg), @@ -4318,6 +4590,7 @@ static const struct of_device_id qcom_llcc_of_match[]= =3D { { .compatible =3D "qcom,sm8450-llcc", .data =3D &sm8450_cfgs }, { .compatible =3D "qcom,sm8550-llcc", .data =3D &sm8550_cfgs }, { .compatible =3D "qcom,sm8650-llcc", .data =3D &sm8650_cfgs }, + { .compatible =3D "qcom,sm8750-llcc", .data =3D &sm8750_cfgs }, { .compatible =3D "qcom,x1e80100-llcc", .data =3D &x1e80100_cfgs }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 8e5d78fb4847a232ab17a66c2775552dcb287752..7a69210a250c4646b7fd6cf4009= 95e35d3f00493 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -24,6 +24,7 @@ #define LLCC_CMPTDMA 15 #define LLCC_DISP 16 #define LLCC_VIDFW 17 +#define LLCC_CAMFW 18 #define LLCC_MDMHPFX 20 #define LLCC_MDMPNG 21 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b02a3221c7bsm9746298a12.71.2025.04.14.16.22.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Apr 2025 16:22:18 -0700 (PDT) From: Melody Olvera Date: Mon, 14 Apr 2025 16:21:53 -0700 Subject: [PATCH v4 4/4] arm64: dts: qcom: sm8750: Add LLCC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250414-sm8750_llcc_master-v4-4-e007f035380c@oss.qualcomm.com> References: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> In-Reply-To: <20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Satya Durga Srinivasu Prabhala , Trilok Soni Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Melody Olvera , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744672932; l=1338; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=2/EMhU+NqxnUmU9I5ZqfEP5bIJvKe/ALVnWTmcXBqHI=; b=WrCHrXytUYfg6wuQFRnksvJi9qMbAAOpEezYN6gaBkFoGLhRN0EyuB5g80zakzMaeXqtBBVPp hXGPY6YArK+Cv9kIH8hSzZ6mqu5f+LIfVvsmb7pv19L1PFywwezQMpZ X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-ORIG-GUID: 8hNLjDPvqbau_4-L8hMmxpUC1BAj0RjC X-Proofpoint-GUID: 8hNLjDPvqbau_4-L8hMmxpUC1BAj0RjC X-Authority-Analysis: v=2.4 cv=ANaQCy7k c=1 sm=1 tr=0 ts=67fd98ab cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=Gx2GX35Bv4c8b2S2wRcA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=694 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140168 Add LLCC node for SM8750 SoC. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 612b99dc3c55495d06b3577531ec6996554bbbb6..5d3a96c6412095fd89ab1fd9a58= 6fe9ad4dd7ee9 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3310,6 +3310,24 @@ gem_noc: interconnect@24100000 { #interconnect-cells =3D <2>; }; =20 + system-cache-controller@24800000 { + compatible =3D "qcom,sm8750-llcc"; + reg =3D <0x0 0x24800000 0x0 0x200000>, + <0x0 0x25800000 0x0 0x200000>, + <0x0 0x24c00000 0x0 0x200000>, + <0x0 0x25c00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, + <0x0 0x26c00000 0x0 0x200000>; + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts =3D ; + }; + nsp_noc: interconnect@320c0000 { compatible =3D "qcom,sm8750-nsp-noc"; reg =3D <0x0 0x320c0000 0x0 0x13080>; --=20 2.48.1