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Sun, 13 Apr 2025 22:39:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+lYfmeZMaTl0r2O67Ucz8nxsn68aq9IJaHKygatFb1SaohIdf3+BadqPqlWPTBdX0qfzpFQ== X-Received: by 2002:a05:6a00:3a01:b0:736:69aa:112c with SMTP id d2e1a72fcca58-73bd11e26d6mr13140929b3a.9.1744609169438; Sun, 13 Apr 2025 22:39:29 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd23332d2sm5824559b3a.159.2025.04.13.22.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 22:39:29 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Mon, 14 Apr 2025 11:09:12 +0530 Subject: [PATCH v2 1/3] dt-bindings: PCI: qcom: Move phy, wake & reset gpio's to root port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250414-perst-v2-1-89247746d755@oss.qualcomm.com> References: <20250414-perst-v2-0-89247746d755@oss.qualcomm.com> In-Reply-To: <20250414-perst-v2-0-89247746d755@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744609160; l=2982; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=FMVSfgXqB99+cHL2kSSq0wS1EX1F8w0XxVP3cHPwGl4=; b=3C6xcR4XSNkH7x/vws5locFq2tigeUCUHcg4HCvd+X7j6iSUJkkYeER3JLT/ihKKsO+GzRScS hXMo4W+F/l/CFvGQHRJ1qZOjKSwACFoEWOz3kPUYaCgicCtDU/y/02x X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: 886P2PQXeRiNGKtfhNNLkKK_UBGiiODv X-Authority-Analysis: v=2.4 cv=PruTbxM3 c=1 sm=1 tr=0 ts=67fc9f93 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=stmhjgsGwY9JSZftE7EA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: 886P2PQXeRiNGKtfhNNLkKK_UBGiiODv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140039 Move the phy, phy-names, wake-gpio's to the pcie root port node instead of the bridge node, as agreed upon in multiple places one instance is[1]. Update the qcom,pcie-common.yaml to include the phy, phy-names, and wake-gpios properties in the root port node. There is already reset-gpio defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. For backward compatibility, do not remove any existing properties in the bridge node. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 18 ++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 17 +++++++++++++-= --- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0480c58f7d998adbac4c6de20cdaec945b3bab21..16e9acba1559b457da8a8a9dda4= a22b226808f86 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -85,6 +85,24 @@ properties: opp-table: type: object =20 +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476fb0412217c68bd8db44a51c7d236..beb092f53019c31861460570cd2= 142506e05d8ef 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -162,9 +162,6 @@ examples: iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; =20 - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie1_clkreq_n>; =20 @@ -173,7 +170,19 @@ examples: resets =3D <&gcc GCC_PCIE_1_BCR>; reset-names =3D "pci"; =20 - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply =3D <&pp3300_ssd>; + pcie1_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + }; + }; }; --=20 2.34.1