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Sun, 13 Apr 2025 15:50:17 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li , Chen Wang Subject: [PATCH v4 4/4] irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller Date: Mon, 14 Apr 2025 06:49:15 +0800 Message-ID: <20250413224922.69719-5-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224922.69719-1-inochiama@gmail.com> References: <20250413224922.69719-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Sophgo SG2044 MSI interrupt controller. Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Tested-by: Chen Wang # SG2042 --- drivers/irqchip/irq-sg2042-msi.c | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 1001c1117b00..2935ca213306 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -94,6 +94,35 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = =3D { .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, }; =20 +static void sg2044_msi_irq_ack(struct irq_data *d) +{ + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + + writel(0, (unsigned int *)data->reg_clr + d->hwirq); + irq_chip_ack_parent(d); +} + +static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_= msg *msg) +{ + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + phys_addr_t doorbell =3D data->doorbell_addr + 4 * (d->hwirq / 32); + + msg->address_lo =3D lower_32_bits(doorbell); + msg->address_hi =3D upper_32_bits(doorbell); + msg->data =3D d->hwirq % 32; +} + +static struct irq_chip sg2044_msi_middle_irq_chip =3D { + .name =3D "SG2044 MSI", + .irq_ack =3D sg2044_msi_irq_ack, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_compose_msi_msg =3D sg2044_msi_irq_compose_msi_msg, +}; + static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsig= ned int virq, int hwirq) { struct sg204x_msi_chipdata *data =3D domain->host_data; @@ -173,6 +202,22 @@ static const struct msi_parent_ops sg2042_msi_parent_o= ps =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX) + +static const struct msi_parent_ops sg2044_msi_parent_ops =3D { + .required_flags =3D SG2044_MSI_FLAGS_REQUIRED, + .supported_flags =3D SG2044_MSI_FLAGS_SUPPORTED, + .chip_flags =3D MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, + .bus_select_mask =3D MATCH_PCI_MSI, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .prefix =3D "SG2044-", + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, +}; + static int sg204x_msi_init_domains(struct sg204x_msi_chipdata *data, struct irq_domain *plic_domain, struct device *dev) { @@ -267,8 +312,14 @@ static const struct sg204x_msi_chip_info sg2042_chip_i= nfo =3D { .parent_ops =3D &sg2042_msi_parent_ops, }; =20 +static const struct sg204x_msi_chip_info sg2044_chip_info =3D { + .irqchip =3D &sg2044_msi_middle_irq_chip, + .parent_ops =3D &sg2044_msi_parent_ops, +}; + static const struct of_device_id sg2042_msi_of_match[] =3D { { .compatible =3D "sophgo,sg2042-msi", .data =3D &sg2042_chip_info }, + { .compatible =3D "sophgo,sg2044-msi", .data =3D &sg2044_chip_info }, { } }; =20 --=20 2.49.0