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Sun, 13 Apr 2025 15:50:07 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li , Conor Dooley , Chen Wang Subject: [PATCH v4 1/4] dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller Date: Mon, 14 Apr 2025 06:49:12 +0800 Message-ID: <20250413224922.69719-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224922.69719-1-inochiama@gmail.com> References: <20250413224922.69719-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Like SG2042, SG2044 also uses an external msi controller to provide MSI interrupt for PCIe controllers. The difference between these two msi controlling are summary as follows: 1. SG2044 acks the interrupt by writing 0, as on SG2042 by setting related bit. 2. SG2044 uses interrupt number mod 32 as msi message data, but SG2042 uses setting related bit. Add support for the SG2044 msi controller. Signed-off-by: Inochi Amaoto Acked-by: Conor Dooley Reviewed-by: Chen Wang Tested-by: Chen Wang # SG2042 --- .../bindings/interrupt-controller/sophgo,sg2042-msi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,= sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/so= phgo,sg2042-msi.yaml index e1ffd55fa7bf..f6b8b1d92f79 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml @@ -18,7 +18,9 @@ allOf: =20 properties: compatible: - const: sophgo,sg2042-msi + enum: + - sophgo,sg2042-msi + - sophgo,sg2044-msi =20 reg: items: --=20 2.49.0 From nobody Fri Dec 19 06:18:32 2025 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B36931AE875; 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Sun, 13 Apr 2025 15:50:11 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id d75a77b69052e-47983cc92c6sm29498771cf.6.2025.04.13.15.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 15:50:11 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li , Chen Wang Subject: [PATCH v4 2/4] irqchip/sg2042-msi: rename generic function and structure Date: Mon, 14 Apr 2025 06:49:13 +0800 Message-ID: <20250413224922.69719-3-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224922.69719-1-inochiama@gmail.com> References: <20250413224922.69719-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the driver logic can be used in both SG2042 and SG2044, it will be better to have a generic name. Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Tested-by: Chen Wang # SG2042 --- drivers/irqchip/irq-sg2042-msi.c | 46 ++++++++++++++++---------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 375b55aa0acd..c9bff7ba693d 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -21,7 +21,7 @@ =20 #define SG2042_MAX_MSI_VECTOR 32 =20 -struct sg2042_msi_chipdata { +struct sg204x_msi_chipdata { void __iomem *reg_clr; // clear reg, see TRM, 10.1.33, GP_INTR0_CLR =20 phys_addr_t doorbell_addr; // see TRM, 10.1.32, GP_INTR0_SET @@ -33,7 +33,7 @@ struct sg2042_msi_chipdata { struct mutex msi_map_lock; // lock for msi_map }; =20 -static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int= num_req) +static int sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int= num_req) { int first; =20 @@ -43,7 +43,7 @@ static int sg2042_msi_allocate_hwirq(struct sg2042_msi_ch= ipdata *data, int num_r return first >=3D 0 ? first : -ENOSPC; } =20 -static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, int hw= irq, int num_req) +static void sg204x_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hw= irq, int num_req) { guard(mutex)(&data->msi_map_lock); bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req)); @@ -51,7 +51,7 @@ static void sg2042_msi_free_hwirq(struct sg2042_msi_chipd= ata *data, int hwirq, i =20 static void sg2042_msi_irq_ack(struct irq_data *d) { - struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); int bit_off =3D d->hwirq; =20 writel(1 << bit_off, data->reg_clr); @@ -61,7 +61,7 @@ static void sg2042_msi_irq_ack(struct irq_data *d) =20 static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_= msg *msg) { - struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); =20 msg->address_hi =3D upper_32_bits(data->doorbell_addr); msg->address_lo =3D lower_32_bits(data->doorbell_addr); @@ -79,9 +79,9 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = =3D { .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, }; =20 -static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsig= ned int virq, int hwirq) +static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsig= ned int virq, int hwirq) { - struct sg2042_msi_chipdata *data =3D domain->host_data; + struct sg204x_msi_chipdata *data =3D domain->host_data; struct irq_fwspec fwspec; struct irq_data *d; int ret; @@ -99,18 +99,18 @@ static int sg2042_msi_parent_domain_alloc(struct irq_do= main *domain, unsigned in return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); } =20 -static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, unsig= ned int virq, +static int sg204x_msi_middle_domain_alloc(struct irq_domain *domain, unsig= ned int virq, unsigned int nr_irqs, void *args) { - struct sg2042_msi_chipdata *data =3D domain->host_data; + struct sg204x_msi_chipdata *data =3D domain->host_data; int hwirq, err, i; =20 - hwirq =3D sg2042_msi_allocate_hwirq(data, nr_irqs); + hwirq =3D sg204x_msi_allocate_hwirq(data, nr_irqs); if (hwirq < 0) return hwirq; =20 for (i =3D 0; i < nr_irqs; i++) { - err =3D sg2042_msi_parent_domain_alloc(domain, virq + i, hwirq + i); + err =3D sg204x_msi_parent_domain_alloc(domain, virq + i, hwirq + i); if (err) goto err_hwirq; =20 @@ -121,25 +121,25 @@ static int sg2042_msi_middle_domain_alloc(struct irq_= domain *domain, unsigned in return 0; =20 err_hwirq: - sg2042_msi_free_hwirq(data, hwirq, nr_irqs); + sg204x_msi_free_hwirq(data, hwirq, nr_irqs); irq_domain_free_irqs_parent(domain, virq, i); =20 return err; } =20 -static void sg2042_msi_middle_domain_free(struct irq_domain *domain, unsig= ned int virq, +static void sg204x_msi_middle_domain_free(struct irq_domain *domain, unsig= ned int virq, unsigned int nr_irqs) { struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); - struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); =20 irq_domain_free_irqs_parent(domain, virq, nr_irqs); - sg2042_msi_free_hwirq(data, d->hwirq, nr_irqs); + sg204x_msi_free_hwirq(data, d->hwirq, nr_irqs); } =20 -static const struct irq_domain_ops sg2042_msi_middle_domain_ops =3D { - .alloc =3D sg2042_msi_middle_domain_alloc, - .free =3D sg2042_msi_middle_domain_free, +static const struct irq_domain_ops sg204x_msi_middle_domain_ops =3D { + .alloc =3D sg204x_msi_middle_domain_alloc, + .free =3D sg204x_msi_middle_domain_free, .select =3D msi_lib_irq_domain_select, }; =20 @@ -158,14 +158,14 @@ static const struct msi_parent_ops sg2042_msi_parent_= ops =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 -static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data, +static int sg204x_msi_init_domains(struct sg204x_msi_chipdata *data, struct irq_domain *plic_domain, struct device *dev) { struct fwnode_handle *fwnode =3D dev_fwnode(dev); struct irq_domain *middle_domain; =20 middle_domain =3D irq_domain_create_hierarchy(plic_domain, 0, data->num_i= rqs, fwnode, - &sg2042_msi_middle_domain_ops, data); + &sg204x_msi_middle_domain_ops, data); if (!middle_domain) { pr_err("Failed to create the MSI middle domain\n"); return -ENOMEM; @@ -182,13 +182,13 @@ static int sg2042_msi_init_domains(struct sg2042_msi_= chipdata *data, static int sg2042_msi_probe(struct platform_device *pdev) { struct fwnode_reference_args args =3D { }; - struct sg2042_msi_chipdata *data; + struct sg204x_msi_chipdata *data; struct device *dev =3D &pdev->dev; struct irq_domain *plic_domain; struct resource *res; int ret; =20 - data =3D devm_kzalloc(dev, sizeof(struct sg2042_msi_chipdata), GFP_KERNEL= ); + data =3D devm_kzalloc(dev, sizeof(struct sg204x_msi_chipdata), GFP_KERNEL= ); if (!data) return -ENOMEM; =20 @@ -232,7 +232,7 @@ static int sg2042_msi_probe(struct platform_device *pde= v) =20 mutex_init(&data->msi_map_lock); =20 - return sg2042_msi_init_domains(data, plic_domain, dev); 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Sun, 13 Apr 2025 15:50:14 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li , Chen Wang Subject: [PATCH v4 3/4] irqchip/sg2042-msi: introduce configurable chipinfo for sg2042 Date: Mon, 14 Apr 2025 06:49:14 +0800 Message-ID: <20250413224922.69719-4-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224922.69719-1-inochiama@gmail.com> References: <20250413224922.69719-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the controller on SG2044 uses different msi_parent_ops and irq_chip, it is necessary to add a structure to hold the configuration across controllers. Add the chipinfo structure and implement necessary logic for it. Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Tested-by: Chen Wang # SG2042 --- drivers/irqchip/irq-sg2042-msi.c | 52 ++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index c9bff7ba693d..1001c1117b00 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -19,18 +19,33 @@ =20 #include "irq-msi-lib.h" =20 -#define SG2042_MAX_MSI_VECTOR 32 +struct sg204x_msi_chip_info { + const struct irq_chip *irqchip; + const struct msi_parent_ops *parent_ops; +}; =20 +/** + * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller + * @reg_clr: clear reg, see TRM, 10.1.33, GP_INTR0_CLR + * @doorbell_addr: see TRM, 10.1.32, GP_INTR0_SET + * @irq_first: First vectors number that MSIs starts + * @num_irqs: Number of vectors for MSIs + * @msi_map: mapping for allocated MSI vectors. + * @msi_map_lock: Lock for msi_map + * @chip_info: chip specific infomations + */ struct sg204x_msi_chipdata { - void __iomem *reg_clr; // clear reg, see TRM, 10.1.33, GP_INTR0_CLR + void __iomem *reg_clr; =20 - phys_addr_t doorbell_addr; // see TRM, 10.1.32, GP_INTR0_SET + phys_addr_t doorbell_addr; =20 - u32 irq_first; // The vector number that MSIs starts - u32 num_irqs; // The number of vectors for MSIs + u32 irq_first; + u32 num_irqs; =20 - DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR); - struct mutex msi_map_lock; // lock for msi_map + unsigned long *msi_map; + struct mutex msi_map_lock; + + const struct sg204x_msi_chip_info *chip_info; }; =20 static int sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int= num_req) @@ -115,7 +130,7 @@ static int sg204x_msi_middle_domain_alloc(struct irq_do= main *domain, unsigned in goto err_hwirq; =20 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, - &sg2042_msi_middle_irq_chip, data); + data->chip_info->irqchip, data); } =20 return 0; @@ -174,7 +189,7 @@ static int sg204x_msi_init_domains(struct sg204x_msi_ch= ipdata *data, irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS); =20 middle_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; - middle_domain->msi_parent_ops =3D &sg2042_msi_parent_ops; + middle_domain->msi_parent_ops =3D data->chip_info->parent_ops; =20 return 0; } @@ -192,6 +207,12 @@ static int sg2042_msi_probe(struct platform_device *pd= ev) if (!data) return -ENOMEM; =20 + data->chip_info =3D device_get_match_data(&pdev->dev); + if (!data->chip_info) { + dev_err(&pdev->dev, "Failed to get irqchip\n"); + return -EINVAL; + } + data->reg_clr =3D devm_platform_ioremap_resource_byname(pdev, "clr"); if (IS_ERR(data->reg_clr)) { dev_err(dev, "Failed to map clear register\n"); @@ -232,11 +253,22 @@ static int sg2042_msi_probe(struct platform_device *p= dev) =20 mutex_init(&data->msi_map_lock); =20 + data->msi_map =3D devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERN= EL); + if (!data->msi_map) { + dev_err(&pdev->dev, "Unable to allocate msi mapping\n"); + return -ENOMEM; + } + return sg204x_msi_init_domains(data, plic_domain, dev); } =20 +static const struct sg204x_msi_chip_info sg2042_chip_info =3D { + .irqchip =3D &sg2042_msi_middle_irq_chip, + .parent_ops =3D &sg2042_msi_parent_ops, +}; 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Sun, 13 Apr 2025 15:50:17 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li , Chen Wang Subject: [PATCH v4 4/4] irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller Date: Mon, 14 Apr 2025 06:49:15 +0800 Message-ID: <20250413224922.69719-5-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224922.69719-1-inochiama@gmail.com> References: <20250413224922.69719-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Sophgo SG2044 MSI interrupt controller. Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Tested-by: Chen Wang # SG2042 --- drivers/irqchip/irq-sg2042-msi.c | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 1001c1117b00..2935ca213306 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -94,6 +94,35 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = =3D { .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, }; =20 +static void sg2044_msi_irq_ack(struct irq_data *d) +{ + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + + writel(0, (unsigned int *)data->reg_clr + d->hwirq); + irq_chip_ack_parent(d); +} + +static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_= msg *msg) +{ + struct sg204x_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + phys_addr_t doorbell =3D data->doorbell_addr + 4 * (d->hwirq / 32); + + msg->address_lo =3D lower_32_bits(doorbell); + msg->address_hi =3D upper_32_bits(doorbell); + msg->data =3D d->hwirq % 32; +} + +static struct irq_chip sg2044_msi_middle_irq_chip =3D { + .name =3D "SG2044 MSI", + .irq_ack =3D sg2044_msi_irq_ack, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_compose_msi_msg =3D sg2044_msi_irq_compose_msi_msg, +}; + static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsig= ned int virq, int hwirq) { struct sg204x_msi_chipdata *data =3D domain->host_data; @@ -173,6 +202,22 @@ static const struct msi_parent_ops sg2042_msi_parent_o= ps =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX) + +static const struct msi_parent_ops sg2044_msi_parent_ops =3D { + .required_flags =3D SG2044_MSI_FLAGS_REQUIRED, + .supported_flags =3D SG2044_MSI_FLAGS_SUPPORTED, + .chip_flags =3D MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, + .bus_select_mask =3D MATCH_PCI_MSI, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .prefix =3D "SG2044-", + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, +}; + static int sg204x_msi_init_domains(struct sg204x_msi_chipdata *data, struct irq_domain *plic_domain, struct device *dev) { @@ -267,8 +312,14 @@ static const struct sg204x_msi_chip_info sg2042_chip_i= nfo =3D { .parent_ops =3D &sg2042_msi_parent_ops, }; =20 +static const struct sg204x_msi_chip_info sg2044_chip_info =3D { + .irqchip =3D &sg2044_msi_middle_irq_chip, + .parent_ops =3D &sg2044_msi_parent_ops, +}; + static const struct of_device_id sg2042_msi_of_match[] =3D { { .compatible =3D "sophgo,sg2042-msi", .data =3D &sg2042_chip_info }, + { .compatible =3D "sophgo,sg2044-msi", .data =3D &sg2044_chip_info }, { } }; =20 --=20 2.49.0