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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464e9812sm13345431fa.49.2025.04.13.09.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 09:32:59 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 13 Apr 2025 19:32:55 +0300 Subject: [PATCH 1/7] drm/msm: move wq handling to KMS code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250413-msm-gpu-split-v1-1-1132f4b616c7@oss.qualcomm.com> References: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> In-Reply-To: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3644; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=OXKR8Bekin1jml/eRU8BDlgsy1eZQ5R/fWSgssRh70w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn++c539kpkZcgiwYj8YBtJ6U0W2bhkdYpBMw/v o5tB6Y2aWKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/vnOQAKCRCLPIo+Aiko 1aPsB/9fRlpj+FblmlkY+PCOG4ByEVp4sWFeaROnjT2dfgoK3+QwyU/Llyo9oHzj8HactL4XoYq miaDayv3LVoxjcYvJeamoUAKf1zbIHcvs7Ld6nQuDU26dpaaH0iAD2sC5e1FWMGoCTI7x1w3z4I CpocIXGNsIPQAzcJkfd/wJYYJWk/+rw9VpGIQ50fA1BZ+j72jON015Hhl8xMcSgF8Wz9zVp3VBv c/jp9L/WphXV+pIhSouvXlFsarXX8HWMv1aCXHOPjpNtKjsUKo04/gF5InsNOvxRAu82hfqgi+e PVHtnO3PPWtW0u9oWzJXef04tRenRJLyUwpNS11wASpwI2S9 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=P9I6hjAu c=1 sm=1 tr=0 ts=67fbe73f cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=4zMMb90fMlmLdFOEXiAA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: 9UBwCE_fPcraqdSumvVyeduQL33xbcvN X-Proofpoint-ORIG-GUID: 9UBwCE_fPcraqdSumvVyeduQL33xbcvN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-13_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504130127 The global workqueue is only used for vblanks inside KMS code. Move allocation / flushing / deallcation of it to msm_kms.c Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_drv.c | 21 ++------------------- drivers/gpu/drm/msm/msm_kms.c | 16 +++++++++++++++- 2 files changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index c3588dc9e53764a27efda1901b094724cec8928a..02beb40eb9146941aa43862d07a= 6d82ae21c965e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -82,13 +82,6 @@ static int msm_drm_uninit(struct device *dev) drm_atomic_helper_shutdown(ddev); } =20 - /* We must cancel and cleanup any pending vblank enable/disable - * work before msm_irq_uninstall() to avoid work re-enabling an - * irq after uninstall has disabled it. - */ - - flush_workqueue(priv->wq); - msm_gem_shrinker_cleanup(ddev); =20 msm_perf_debugfs_cleanup(priv); @@ -104,8 +97,6 @@ static int msm_drm_uninit(struct device *dev) ddev->dev_private =3D NULL; drm_dev_put(ddev); =20 - destroy_workqueue(priv->wq); - return 0; } =20 @@ -227,12 +218,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ddev->dev_private =3D priv; priv->dev =3D ddev; =20 - priv->wq =3D alloc_ordered_workqueue("msm", 0); - if (!priv->wq) { - ret =3D -ENOMEM; - goto err_put_dev; - } - INIT_LIST_HEAD(&priv->objects); mutex_init(&priv->obj_lock); =20 @@ -253,12 +238,12 @@ static int msm_drm_init(struct device *dev, const str= uct drm_driver *drv) if (priv->kms_init) { ret =3D drmm_mode_config_init(ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; } =20 ret =3D msm_init_vram(ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; =20 dma_set_max_seg_size(dev, UINT_MAX); =20 @@ -304,8 +289,6 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) =20 err_deinit_vram: msm_deinit_vram(ddev); -err_destroy_wq: - destroy_workqueue(priv->wq); err_put_dev: drm_dev_put(ddev); =20 diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 35d5397e73b4c5cb90b1770e8570277e782be7ec..821f0b9f968fc3d448e612bfae0= 4639ceb770353 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -227,6 +227,13 @@ void msm_drm_kms_uninit(struct device *dev) =20 BUG_ON(!kms); =20 + /* We must cancel and cleanup any pending vblank enable/disable + * work before msm_irq_uninstall() to avoid work re-enabling an + * irq after uninstall has disabled it. + */ + + flush_workqueue(priv->wq); + /* clean up event worker threads */ for (i =3D 0; i < priv->num_crtcs; i++) { if (priv->event_thread[i].worker) @@ -243,6 +250,8 @@ void msm_drm_kms_uninit(struct device *dev) =20 if (kms && kms->funcs) kms->funcs->destroy(kms); + + destroy_workqueue(priv->wq); } =20 int msm_drm_kms_init(struct device *dev, const struct drm_driver *drv) @@ -258,10 +267,14 @@ int msm_drm_kms_init(struct device *dev, const struct= drm_driver *drv) if (ret) return ret; =20 + priv->wq =3D alloc_ordered_workqueue("msm", 0); + if (!priv->wq) + return -ENOMEM; + ret =3D priv->kms_init(ddev); if (ret) { DRM_DEV_ERROR(dev, "failed to load kms\n"); - return ret; + goto err_msm_uninit; } =20 /* Enable normalization of plane zpos */ @@ -319,6 +332,7 @@ int msm_drm_kms_init(struct device *dev, const struct d= rm_driver *drv) return 0; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_drv.c | 9 +++------ drivers/gpu/drm/msm/msm_kms.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/msm_kms.h | 2 ++ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 02beb40eb9146941aa43862d07a6d82ae21c965e..b296d1315aa249638e073d08d43= e8d41a4354f3b 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -11,7 +11,6 @@ #include #include =20 -#include #include #include #include @@ -79,7 +78,7 @@ static int msm_drm_uninit(struct device *dev) if (ddev->registered) { drm_dev_unregister(ddev); if (priv->kms) - drm_atomic_helper_shutdown(ddev); + msm_drm_kms_unregister(dev); } =20 msm_gem_shrinker_cleanup(ddev); @@ -275,10 +274,8 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) if (ret) goto err_msm_uninit; =20 - if (priv->kms_init) { - drm_kms_helper_poll_init(ddev); - drm_client_setup(ddev, NULL); - } + if (priv->kms_init) + msm_drm_kms_post_init(dev); =20 return 0; =20 diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 821f0b9f968fc3d448e612bfae04639ceb770353..fdb22c41bdc1a772b45c6940dda= 787dd96879bc2 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "disp/msm_disp_snapshot.h" #include "msm_drv.h" @@ -217,6 +218,15 @@ struct msm_gem_address_space *msm_kms_init_aspace(stru= ct drm_device *dev) return aspace; } =20 +void msm_drm_kms_unregister(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + struct drm_device *ddev =3D priv->dev; + + drm_atomic_helper_shutdown(ddev); +} + void msm_drm_kms_uninit(struct device *dev) { struct platform_device *pdev =3D to_platform_device(dev); @@ -373,3 +383,13 @@ void msm_kms_shutdown(struct platform_device *pdev) if (drm && drm->registered && priv->kms) drm_atomic_helper_shutdown(drm); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464e9812sm13345431fa.49.2025.04.13.09.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 09:33:03 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 13 Apr 2025 19:32:57 +0300 Subject: [PATCH 3/7] drm/msm: make it possible to disable KMS-related code. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250413-msm-gpu-split-v1-3-1132f4b616c7@oss.qualcomm.com> References: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> In-Reply-To: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11059; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=b7aQBivum8PLjThk33cbBnwZSmkIYuDPMqj++mqttyQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn++c5Vo6fgTGrRaMVfNNNQ6hesCZgIlTcDd3f3 6N4S7H4C4mJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/vnOQAKCRCLPIo+Aiko 1RZiCACeKHml970t5zGfV77VMeom3lsbrw3F2HGOEzvJgLmVdetDwLN5tCfcwX16rZhro+CAr2i e+6QWI7LvoAWOj7kV44RZaZMdeDLjWKXXAXeSs+AplJde7N5ziEyuqUXUrE4mHm+fiVN3brgaLN WgnxPmaA0HbNUTU5Bk9xzm08NkklG2FsYjTjsdZYCjjsTP1ChnI49x56B39pri/LhKQ8gUj07gM 8bULuRO/XLvVTgtA8gTenRhv6vTBCpMR6RSd72+tNDFHW3+7ToagiATTUdU7o+casBBhoJBCud7 bXt6nznv7qoalGUJbIy9CiB83D/ZjZdmYwy7rWcQ8hWe9r1s X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: Kk5mUUeneQh5q48oN_C6o_g89g31KGLf X-Authority-Analysis: v=2.4 cv=IZ6HWXqa c=1 sm=1 tr=0 ts=67fbe745 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=N8FS_TdUqCTfgw2huykA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: Kk5mUUeneQh5q48oN_C6o_g89g31KGLf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-13_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504130127 If the Adreno device is used in a headless mode, there is no need to build all KMS components. Build corresponding parts conditionally, only selecting them if modeset support is actually required. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 14 ++++++ drivers/gpu/drm/msm/Makefile | 16 +++---- drivers/gpu/drm/msm/dp/dp_debug.c | 4 ++ drivers/gpu/drm/msm/msm_debugfs.c | 92 ++++++++++++++++++++++-------------= ---- drivers/gpu/drm/msm/msm_drv.h | 7 ++- drivers/gpu/drm/msm/msm_kms.h | 23 ++++++++++ 6 files changed, 108 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 974bc7c0ea761147d3326bdce9039d6f26f290d0..0be31c5acdd1b7ef80f0e820ff4= 30692616122e0 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -66,6 +66,14 @@ config DRM_MSM_VALIDATE_XML Validate XML files with register definitions against rules-fd schema. This option is mostly targeting DRM MSM developers. If unsure, say N. =20 +config DRM_MSM_KMS + def_bool n + depends on DRM_MSM + +config DRM_MSM_KMS_FBDEV + def_bool DRM_FBDEV_EMULATION + depends on DRM_MSM_KMS + config DRM_MSM_MDSS bool depends on DRM_MSM @@ -74,6 +82,7 @@ config DRM_MSM_MDSS config DRM_MSM_MDP4 bool "Enable MDP4 support in MSM DRM driver" depends on DRM_MSM + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v4 (MDP4) in @@ -84,6 +93,7 @@ config DRM_MSM_MDP5 bool "Enable MDP5 support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v5 (MDP5) in @@ -94,6 +104,7 @@ config DRM_MSM_DPU bool "Enable DPU support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS select DRM_DISPLAY_DSC_HELPER default y help @@ -104,6 +115,7 @@ config DRM_MSM_DPU config DRM_MSM_DP bool "Enable DisplayPort support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select RATIONAL default y help @@ -114,6 +126,7 @@ config DRM_MSM_DP config DRM_MSM_DSI bool "Enable DSI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select DRM_PANEL select DRM_MIPI_DSI select DRM_DISPLAY_DSC_HELPER @@ -169,6 +182,7 @@ config DRM_MSM_DSI_7NM_PHY config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS default y select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDMI_STATE_HELPER diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 5df20cbeafb8bf07c825a1fd72719d5a56c38613..3749b0af779e73a93d7c219d3fb= d3865b9296b50 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -101,18 +101,15 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ msm-display-$(CONFIG_DRM_MSM_MDSS) +=3D \ msm_mdss.o \ =20 -msm-display-y +=3D \ +msm-display-$(CONFIG_DRM_MSM_KMS) +=3D \ disp/mdp_format.o \ disp/mdp_kms.o \ disp/msm_disp_snapshot.o \ disp/msm_disp_snapshot_util.o \ =20 msm-y +=3D \ - msm_atomic.o \ - msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ - msm_fb.o \ msm_fence.o \ msm_gem.o \ msm_gem_prime.o \ @@ -123,21 +120,24 @@ msm-y +=3D \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ - msm_kms.o \ msm_perf.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ msm_gpu_tracepoints.o \ =20 -msm-$(CONFIG_DRM_FBDEV_EMULATION) +=3D msm_fbdev.o +msm-$(CONFIG_DRM_MSM_KMS) +=3D \ + msm_atomic.o \ + msm_atomic_tracepoints.o \ + msm_fb.o \ + msm_kms.o \ =20 -msm-display-$(CONFIG_DEBUG_FS) +=3D \ - dp/dp_debug.o +msm-$(CONFIG_DRM_MSM_KMS_FBDEV) +=3D msm_fbdev.o =20 msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_catalog.o \ dp/dp_ctrl.o \ + dp/dp_debug.o \ dp/dp_display.o \ dp/dp_drm.o \ dp/dp_link.o \ diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_= debug.c index 22fd946ee201397b72b43c8499714139deb7ba82..7835d93015b31a69aac824ca04d= c65b374546e5c 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -5,6 +5,8 @@ =20 #define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__ =20 +#ifdef CONFIG_DEBUG_FS + #include #include #include @@ -235,3 +237,5 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp= _panel *panel, =20 return 0; } + +#endif diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 7ab607252d183f78b99c3a8b878c949ed5f99fec..2b12f2851fadbc3c924827e1157= 0352736869614 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -117,6 +117,36 @@ static const struct file_operations msm_gpu_fops =3D { .release =3D msm_gpu_release, }; =20 +#ifdef CONFIG_DRM_MSM_KMS +static int msm_fb_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node =3D m->private; + struct drm_device *dev =3D node->minor->dev; + struct drm_framebuffer *fb, *fbdev_fb =3D NULL; + + if (dev->fb_helper && dev->fb_helper->fb) { + seq_puts(m, "fbcon "); + fbdev_fb =3D dev->fb_helper->fb; + msm_framebuffer_describe(fbdev_fb, m); + } + + mutex_lock(&dev->mode_config.fb_lock); + list_for_each_entry(fb, &dev->mode_config.fb_list, head) { + if (fb =3D=3D fbdev_fb) + continue; + + seq_puts(m, "user "); + msm_framebuffer_describe(fb, m); + } + mutex_unlock(&dev->mode_config.fb_lock); + + return 0; +} + +static struct drm_info_list msm_kms_debugfs_list[] =3D { + { "fb", msm_fb_show }, +}; + /* * Display Snapshot: */ @@ -180,6 +210,27 @@ static const struct file_operations msm_kms_fops =3D { .release =3D msm_kms_release, }; =20 +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; + + drm_debugfs_create_files(msm_kms_debugfs_list, + ARRAY_SIZE(msm_kms_debugfs_list), + minor->debugfs_root, minor); + debugfs_create_file("kms", 0400, minor->debugfs_root, + dev, &msm_kms_fops); + + if (priv->kms->funcs->debugfs_init) + priv->kms->funcs->debugfs_init(priv->kms, minor); + +} +#else /* ! CONFIG_DRM_MSM_KMS */ +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ +} +#endif + /* * Other debugfs: */ @@ -238,40 +289,11 @@ static int msm_mm_show(struct seq_file *m, void *arg) return 0; } =20 -static int msm_fb_show(struct seq_file *m, void *arg) -{ - struct drm_info_node *node =3D m->private; - struct drm_device *dev =3D node->minor->dev; - struct drm_framebuffer *fb, *fbdev_fb =3D NULL; - - if (dev->fb_helper && dev->fb_helper->fb) { - seq_printf(m, "fbcon "); - fbdev_fb =3D dev->fb_helper->fb; - msm_framebuffer_describe(fbdev_fb, m); - } - - mutex_lock(&dev->mode_config.fb_lock); - list_for_each_entry(fb, &dev->mode_config.fb_list, head) { - if (fb =3D=3D fbdev_fb) - continue; - - seq_printf(m, "user "); - msm_framebuffer_describe(fb, m); - } - mutex_unlock(&dev->mode_config.fb_lock); - - return 0; -} - static struct drm_info_list msm_debugfs_list[] =3D { {"gem", msm_gem_show}, { "mm", msm_mm_show }, }; =20 -static struct drm_info_list msm_kms_debugfs_list[] =3D { - { "fb", msm_fb_show }, -}; - static int late_init_minor(struct drm_minor *minor) { int ret; @@ -343,20 +365,12 @@ void msm_debugfs_init(struct drm_minor *minor) if (priv->gpu_pdev) msm_debugfs_gpu_init(minor); =20 - if (priv->kms) { - drm_debugfs_create_files(msm_kms_debugfs_list, - ARRAY_SIZE(msm_kms_debugfs_list), - minor->debugfs_root, minor); - debugfs_create_file("kms", S_IRUSR, minor->debugfs_root, - dev, &msm_kms_fops); - } + if (priv->kms) + msm_debugfs_kms_init(minor); =20 debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root, dev, &shrink_fops); =20 - if (priv->kms && priv->kms->funcs->debugfs_init) - priv->kms->funcs->debugfs_init(priv->kms, minor); - fault_create_debugfs_attr("fail_gem_alloc", minor->debugfs_root, &fail_gem_alloc); fault_create_debugfs_attr("fail_gem_iova", minor->debugfs_root, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index a65077855201746c37ee742364b61116565f3794..5f4d3f050c1fde71c405a1ebf51= 6f4f5a396cfc4 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -88,6 +88,7 @@ struct msm_drm_private { /* subordinate devices, if present: */ struct platform_device *gpu_pdev; =20 +#ifdef CONFIG_DRM_MSM_KMS /* possibly this should be in the kms component, but it is * shared by both mdp4 and mdp5.. */ @@ -97,6 +98,7 @@ struct msm_drm_private { struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; =20 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; +#endif =20 /* when we have more than one 'msm_gpu' these need to be an array: */ struct msm_gpu *gpu; @@ -177,11 +179,13 @@ struct msm_drm_private { struct mutex lock; } lru; =20 +#ifdef CONFIG_DRM_MSM_KMS struct workqueue_struct *wq; =20 unsigned int num_crtcs; =20 struct msm_drm_thread event_thread[MAX_CRTCS]; +#endif =20 /* VRAM carveout, used when no IOMMU: */ struct { @@ -275,7 +279,7 @@ struct drm_framebuffer *msm_framebuffer_create(struct d= rm_device *dev, struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format); =20 -#ifdef CONFIG_DRM_FBDEV_EMULATION +#ifdef CONFIG_DRM_MSM_KMS_FBDEV int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes); #define MSM_FBDEV_DRIVER_OPS \ @@ -360,6 +364,7 @@ static inline const char *msm_dsi_get_te_source(struct = msm_dsi *msm_dsi) } #endif =20 +struct msm_dp; #ifdef CONFIG_DRM_MSM_DP int __init msm_dp_register(void); void __exit msm_dp_unregister(void); diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 057b20367724a4ca60f2d60c038077dbcc1c7abc..aabbe851f0d533cca4a2ca00b79= fbf8603870be3 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -13,6 +13,8 @@ =20 #include "msm_drv.h" =20 +#ifdef CONFIG_DRM_MSM_KMS + #define MAX_PLANE 4 =20 /* As there are different display controller blocks depending on the @@ -196,4 +198,25 @@ void msm_drm_kms_post_init(struct device *dev); void msm_drm_kms_unregister(struct device *dev); void msm_drm_kms_uninit(struct device *dev); =20 +#else /* ! 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Bail out if we are registering a KMS-only device. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_debugfs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 2b12f2851fadbc3c924827e11570352736869614..6e60a74b13d72c47e45cb9dc65e= d67b977e900fa 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -296,11 +296,16 @@ static struct drm_info_list msm_debugfs_list[] =3D { =20 static int late_init_minor(struct drm_minor *minor) { + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; int ret; =20 if (!minor) return 0; =20 + if (!priv->gpu_pdev) + return 0; + ret =3D msm_rd_debugfs_init(minor); if (ret) { DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); --=20 2.39.5 From nobody Tue Dec 16 03:21:26 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36F441EBFE6 for ; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464e9812sm13345431fa.49.2025.04.13.09.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 09:33:06 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 13 Apr 2025 19:32:59 +0300 Subject: [PATCH 5/7] drm/msm: rearrange symbol selection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250413-msm-gpu-split-v1-5-1132f4b616c7@oss.qualcomm.com> References: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> In-Reply-To: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1820; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=TnUzAndi2T1YnSlyFpGeu/Plqylj3xVIJozR04iJiQ4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn++c5zot51bWXjqYm5qRu0xm6DL6T8wScfw9tp x2I8HWLsNWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/vnOQAKCRCLPIo+Aiko 1cr7B/9lhjWA64+i6WMEKng6H1Gjr41aeV+3L9pCQteZeOPJK5kWPokWOND0NMftGAqTLzVGSd6 Q0abSVqr+c2q3U+INZiBD3rvM2Kulbs85KXkqgNcTN0Tqcw/mFgA9+JkyrSOaf8HWICe8BjtDDh v+UN3UXuGskPQIf036Jh3XhAqDFACbyy7E7mKIdZOBI79CniHDIt8LOZgdwErhqo7y2gDDuec1h xnGRpDGBTuJNWRh4TRLND3cUeWa6ijjcx5jkj0Ac2fidIHfu/nVLhvE4q3sJJUk916jn85UUcEB CSbCS5snIDthUkPE+4OqN0k1sZPVDeTC2BS1alv8KwCCFblI X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: qSJmrERt0PP3OXdvqdRWl1gQI7mPosNK X-Authority-Analysis: v=2.4 cv=IZ6HWXqa c=1 sm=1 tr=0 ts=67fbe748 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=Dibrpul-hQ8xFFu5PoYA:9 a=FBDQ_9kEivOruIPM:21 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: qSJmrERt0PP3OXdvqdRWl1gQI7mPosNK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-13_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504130127 Move symbol selection to be more fine grained: select DP helpers only if DP driver is also enabled, move KMS and display helpers to the newly introduced DRM_MSM_KMS. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 0be31c5acdd1b7ef80f0e820ff430692616122e0..b3c6117ab035764d603cc257c28= df651d9c38175 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -15,18 +15,8 @@ config DRM_MSM select IOMMU_IO_PGTABLE select QCOM_MDT_LOADER if ARCH_QCOM select REGULATOR - select DRM_CLIENT_SELECTION - select DRM_DISPLAY_DP_AUX_BUS - select DRM_DISPLAY_DP_HELPER - select DRM_DISPLAY_HELPER - select DRM_BRIDGE_CONNECTOR select DRM_EXEC - select DRM_KMS_HELPER - select DRM_PANEL - select DRM_BRIDGE - select DRM_PANEL_BRIDGE select DRM_SCHED - select FB_SYSMEM_HELPERS if DRM_FBDEV_EMULATION select SHMEM select TMPFS select QCOM_SCM @@ -69,10 +59,18 @@ config DRM_MSM_VALIDATE_XML config DRM_MSM_KMS def_bool n depends on DRM_MSM + select DRM_BRIDGE + select DRM_BRIDGE_CONNECTOR + select DRM_CLIENT_SELECTION + select DRM_DISPLAY_HELPER + select DRM_KMS_HELPER + select DRM_PANEL + select DRM_PANEL_BRIDGE =20 config DRM_MSM_KMS_FBDEV def_bool DRM_FBDEV_EMULATION depends on DRM_MSM_KMS + select FB_SYSMEM_HELPERS =20 config DRM_MSM_MDSS bool @@ -117,6 +115,8 @@ config DRM_MSM_DP depends on DRM_MSM depends on DRM_MSM_KMS select RATIONAL + select DRM_DISPLAY_DP_AUX_BUS + select DRM_DISPLAY_DP_HELPER default y help Compile in support for DP driver in MSM DRM driver. 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464e9812sm13345431fa.49.2025.04.13.09.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 09:33:10 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 13 Apr 2025 19:33:00 +0300 Subject: [PATCH 6/7] drm/msm: rework binding of Imageon GPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250413-msm-gpu-split-v1-6-1132f4b616c7@oss.qualcomm.com> References: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> In-Reply-To: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8539; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=+tAM3ooqqZtm9ZI3U6kdny9KzfBxJCRS3qxH3rotCDc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn++c5WI9aJByr2x0wZXmTIQHI+6HgSgjLo1LPo +v0k8uLJ5aJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/vnOQAKCRCLPIo+Aiko 1SEvB/41Ps0VCv+pXy4GHLVVnv0eq20PQjNvgk2BdO4K5rx8gBZWIWtB+xBRUO4R0gqa6iQ/Cr5 fhX0AvSFBGXViJgffs4iD56vDdciux9Lob7lb0teBdlzTtqdVVGpHBkr5MXGEbReXrdK81HX3yy TBCIKtmFpWAcnw/cnZ7/N/wh4W6/D9GUYWbEozTC2OHOCY8qfhMec7bM1hrjuCjQWamcgZxzNXN kq+UAspNA0qNpRFGNEbXdfQi199devMdTSFR5dPaWS/tU068IoDauSfNDg1c1rXACvZoSQQcjlw Nb08ocWEKnTkCa3XrJMHc3uDYbkXBQOLrBOpwT2I1njRkaET X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: l5E6UUMskCexi9n2rAxP6gMweUlZf0UV X-Proofpoint-GUID: l5E6UUMskCexi9n2rAxP6gMweUlZf0UV X-Authority-Analysis: v=2.4 cv=I+plRMgg c=1 sm=1 tr=0 ts=67fbe749 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=WrGWoQF6NLblfNs28g4A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-13_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504130127 Currently the msm driver creates an extra interim platform device for Imageon GPUs. This is not ideal, as the device doesn't have corresponding OF node. If the headless mode is used for newer GPUs, then the msm_use_mmu() function can not detect corresponding IOMMU devices. Also the DRM device (although it's headless) is created with modesetting flags being set. To solve all these issues, rework the way the Imageon devices are bound. Remove the interim device, don't register a component and instead use a cut-down version of the normal functions to probe or remove the driver. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 36 +++--------- drivers/gpu/drm/msm/msm_drv.c | 91 ++++++++++++++++++++------= ---- drivers/gpu/drm/msm/msm_drv.h | 4 ++ 3 files changed, 72 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 236b25c094cd5d462f4b6653de7b7910985cccb6..325cb710ea08ac8e5c3d9c80c8d= 8e18e1946e994 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -241,42 +241,22 @@ static const struct component_ops a3xx_ops =3D { .unbind =3D adreno_unbind, }; =20 -static void adreno_device_register_headless(void) -{ - /* on imx5, we don't have a top-level mdp/dpu node - * this creates a dummy node for the driver for that case - */ - struct platform_device_info dummy_info =3D { - .parent =3D NULL, - .name =3D "msm", - .id =3D -1, - .res =3D NULL, - .num_res =3D 0, - .data =3D NULL, - .size_data =3D 0, - .dma_mask =3D ~0, - }; - platform_device_register_full(&dummy_info); -} - static int adreno_probe(struct platform_device *pdev) { - - int ret; - - ret =3D component_add(&pdev->dev, &a3xx_ops); - if (ret) - return ret; - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) - adreno_device_register_headless(); + return msm_gpu_probe(pdev, &a3xx_ops); =20 - return 0; + return component_add(&pdev->dev, &a3xx_ops); } =20 static void adreno_remove(struct platform_device *pdev) { - component_del(&pdev->dev, &a3xx_ops); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + + if (priv->kms_init) + component_del(&pdev->dev, &a3xx_ops); + else + msm_gpu_remove(pdev, &a3xx_ops); } =20 static void adreno_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index b296d1315aa249638e073d08d43e8d41a4354f3b..e5c1124d45fa146c91caaad39a3= 9fb9d21e5f5f3 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -62,7 +62,7 @@ module_param(modeset, bool, 0600); DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 -static int msm_drm_uninit(struct device *dev) +static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); struct msm_drm_private *priv =3D platform_get_drvdata(pdev); @@ -91,7 +91,10 @@ static int msm_drm_uninit(struct device *dev) =20 msm_deinit_vram(ddev); =20 - component_unbind_all(dev, ddev); + if (gpu_ops) + gpu_ops->unbind(dev, dev, NULL); + else + component_unbind_all(dev, ddev); =20 ddev->dev_private =3D NULL; drm_dev_put(ddev); @@ -200,7 +203,8 @@ static void msm_deinit_vram(struct drm_device *ddev) attrs); } =20 -static int msm_drm_init(struct device *dev, const struct drm_driver *drv) +static int msm_drm_init(struct device *dev, const struct drm_driver *drv, + const struct component_ops *gpu_ops) { struct msm_drm_private *priv =3D dev_get_drvdata(dev); struct drm_device *ddev; @@ -247,7 +251,10 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) dma_set_max_seg_size(dev, UINT_MAX); =20 /* Bind all our sub-components: */ - ret =3D component_bind_all(dev, ddev); + if (gpu_ops) + ret =3D gpu_ops->bind(dev, dev, NULL); + else + ret =3D component_bind_all(dev, ddev); if (ret) goto err_deinit_vram; =20 @@ -259,11 +266,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ret =3D msm_drm_kms_init(dev, drv); if (ret) goto err_msm_uninit; - } else { - /* valid only for the dummy headless case, where of_node=3DNULL */ - WARN_ON(dev->of_node); - ddev->driver_features &=3D ~DRIVER_MODESET; - ddev->driver_features &=3D ~DRIVER_ATOMIC; } =20 ret =3D drm_dev_register(ddev, 0); @@ -280,7 +282,7 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) return 0; =20 err_msm_uninit: - msm_drm_uninit(dev); + msm_drm_uninit(dev, gpu_ops); =20 return ret; =20 @@ -896,6 +898,28 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_gpu_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_RENDER | + DRIVER_SYNCOBJ_TIMELINE | + DRIVER_SYNCOBJ, + .open =3D msm_open, + .postclose =3D msm_postclose, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + /* * Componentized driver support: */ @@ -1020,12 +1044,12 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver); + return msm_drm_init(dev, &msm_driver, NULL); } =20 static void msm_drm_unbind(struct device *dev) { - msm_drm_uninit(dev); + msm_drm_uninit(dev, NULL); } =20 const struct component_master_ops msm_drm_ops =3D { @@ -1074,29 +1098,34 @@ int msm_drv_probe(struct device *master_dev, return 0; } =20 -/* - * Platform driver: - * Used only for headlesss GPU instances - */ - -static int msm_pdev_probe(struct platform_device *pdev) +int msm_gpu_probe(struct platform_device *pdev, + const struct component_ops *ops) { - return msm_drv_probe(&pdev->dev, NULL, NULL); + struct msm_drm_private *priv; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + /* on all devices that I am aware of, iommu's which can map + * any address the cpu can see are used: + */ + ret =3D dma_set_mask_and_coherent(&pdev->dev, ~0); + if (ret) + return ret; + + return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); } =20 -static void msm_pdev_remove(struct platform_device *pdev) +void msm_gpu_remove(struct platform_device *pdev, + const struct component_ops *ops) { - component_master_del(&pdev->dev, &msm_drm_ops); + msm_drm_uninit(&pdev->dev, ops); } =20 -static struct platform_driver msm_platform_driver =3D { - .probe =3D msm_pdev_probe, - .remove =3D msm_pdev_remove, - .driver =3D { - .name =3D "msm", - }, -}; - static int __init msm_drm_register(void) { if (!modeset) @@ -1111,13 +1140,13 @@ static int __init msm_drm_register(void) adreno_register(); msm_mdp4_register(); msm_mdss_register(); - return platform_driver_register(&msm_platform_driver); + + return 0; } =20 static void __exit msm_drm_unregister(void) { DBG("fini"); - platform_driver_unregister(&msm_platform_driver); msm_mdss_unregister(); msm_mdp4_unregister(); msm_dp_unregister(); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5f4d3f050c1fde71c405a1ebf516f4f5a396cfc4..78c4f0ca689cc93b8dba3fae061= a92923e3115a5 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -558,6 +558,10 @@ extern const struct component_master_ops msm_drm_ops; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464e9812sm13345431fa.49.2025.04.13.09.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Apr 2025 09:33:11 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 13 Apr 2025 19:33:01 +0300 Subject: [PATCH 7/7] drm/msm: enable separate binding of GPU and display devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250413-msm-gpu-split-v1-7-1132f4b616c7@oss.qualcomm.com> References: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> In-Reply-To: <20250413-msm-gpu-split-v1-0-1132f4b616c7@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5275; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=UxZvo7l110r3KAnUQgRno9j/OlNY5H8wua2pwV5trbs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn++c6xk595/qU6lqR7+MBkfXinWGfnTdtvf7QO 3tAT79FMAOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/vnOgAKCRCLPIo+Aiko 1aq3B/4gWDn1BXiVN2x3dkE3F5IM9H0YEoSpl84TFh02x2sgfiV8VNcKO29VxJMloosHzJbbvP/ WWoZozD7+u9t0wAiqHodnse1EjYNEWoBEikmgL8yL9GBw/YQtPNEvPQwWWC7HXx2LNanoz6AIiY YbgaYJd/SE/8zAoMUZHNpvnU+WwG/U70ervTpqTO60q6ak+P+KYwRO0BVR+tZUpYLlKQlpqYfBv bvyCueCeCPIO7vr500Jytr6lpeqkusGM2+1uk4rTn+eqEV0RtWPne4a/8ldct0y3dbT4YX+W6yi sAATZrCx4ZAPtf8WExh7bR26I08rfRjfUK3cxQ2xHPLPJS4F X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=ZIrXmW7b c=1 sm=1 tr=0 ts=67fbe74a cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=d3EbUlffPpwbv2rupc8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 1fxOnyEd790Vgm_LUQeGYRr-f62Bq25G X-Proofpoint-ORIG-GUID: 1fxOnyEd790Vgm_LUQeGYRr-f62Bq25G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-13_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504130127 There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_drm, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +- drivers/gpu/drm/msm/msm_drv.c | 49 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 325cb710ea08ac8e5c3d9c80c8d8e18e1946e994..2322a3301a5226c4e2590344e47= 44934addeea33 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -243,7 +243,8 @@ static const struct component_ops a3xx_ops =3D { =20 static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) + if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || + msm_gpu_no_components()) return msm_gpu_probe(pdev, &a3xx_ops); =20 return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index e5c1124d45fa146c91caaad39a39fb9d21e5f5f3..4502425d0a62e1efaca5b987fa5= b657dc0a4e927 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -59,9 +59,18 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +static bool separate_gpu_drm; +MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); +module_param(separate_gpu_drm, bool, 0400); + DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 +bool msm_gpu_no_components(void) +{ + return separate_gpu_drm; +} + static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); @@ -898,6 +907,32 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_kms_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_ATOMIC | + DRIVER_MODESET | + DRIVER_SYNCOBJ_TIMELINE | + DRIVER_SYNCOBJ, + .open =3D msm_open, + .postclose =3D msm_postclose, + .dumb_create =3D msm_gem_dumb_create, + .dumb_map_offset =3D msm_gem_dumb_map_offset, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + MSM_FBDEV_DRIVER_OPS, + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm-kms", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + static const struct drm_driver msm_gpu_driver =3D { .driver_features =3D DRIVER_GEM | DRIVER_RENDER | @@ -1044,7 +1079,11 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver, NULL); + return msm_drm_init(dev, + msm_gpu_no_components() ? + &msm_kms_driver : + &msm_driver, + NULL); } =20 static void msm_drm_unbind(struct device *dev) @@ -1080,9 +1119,11 @@ int msm_drv_probe(struct device *master_dev, return ret; } =20 - ret =3D add_gpu_components(master_dev, &match); - if (ret) - return ret; + if (!msm_gpu_no_components()) { + ret =3D add_gpu_components(master_dev, &match); + if (ret) + return ret; + } =20 /* on all devices that I am aware of, iommu's which can map * any address the cpu can see are used: diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 78c4f0ca689cc93b8dba3fae061a92923e3115a5..73dd90cf4f17ae1b9e29d4309ee= d74393a99d6db 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -569,4 +569,6 @@ void msm_kms_shutdown(struct platform_device *pdev); =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); =20 +bool msm_gpu_no_components(void); + #endif /* __MSM_DRV_H__ */ --=20 2.39.5