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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f505e2ea1esm1420787173.123.2025.04.11.13.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Apr 2025 13:38:35 -0700 (PDT) From: Alex Elder To: gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andy.shevchenko@gmail.com, dlan@gentoo.org, benjamin.larsson@genexis.eu, bastien.curutchet@bootlin.com, andriy.shevchenko@linux.intel.com, u.kleine-koenig@baylibre.com, lkundrak@v3.sk, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] serial: 8250_of: add support for an optional bus clock Date: Fri, 11 Apr 2025 15:38:26 -0500 Message-ID: <20250411203828.1491595-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250411203828.1491595-1-elder@riscstar.com> References: <20250411203828.1491595-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT UART requires a bus clock to be enabled, in addition to it's "normal" core clock. Look up the optional bus clock by name, and if that's found, look up the core clock using the name "core". Supplying a bus clock is optional. If no bus clock is needed, the the first/only clock is used for the core clock. Signed-off-by: Alex Elder --- drivers/tty/serial/8250/8250_of.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/82= 50_of.c index 11c860ea80f60..a90a5462aa72a 100644 --- a/drivers/tty/serial/8250/8250_of.c +++ b/drivers/tty/serial/8250/8250_of.c @@ -123,7 +123,16 @@ static int of_platform_serial_setup(struct platform_de= vice *ofdev, =20 /* Get clk rate through clk driver if present */ if (!port->uartclk) { - info->clk =3D devm_clk_get_enabled(dev, NULL); + struct clk *bus_clk; + + bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(bus_clk)) { + ret =3D dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n= "); + goto err_pmruntime; + } + + /* If the bus clock is required, core clock must be named */ + info->clk =3D devm_clk_get_enabled(dev, bus_clk ? "core" : NULL); if (IS_ERR(info->clk)) { ret =3D dev_err_probe(dev, PTR_ERR(info->clk), "failed to get clock\n"); goto err_pmruntime; --=20 2.45.2