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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 15:12:09.1715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5741199b-6f84-4cc5-02f4-08dd790b3aad X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C70C.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8932 Content-Type: text/plain; charset="utf-8" This patch adds 64-bit register accessors to simplify register access in Panthor. It also adds 32-bit and 64-bit variants for read_poll_timeout. This patch also updates Panthor to use the new 64-bit accessors and poll functions. Signed-off-by: Karunika Choo Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panthor/panthor_device.h | 71 ++++++++++++ drivers/gpu/drm/panthor/panthor_fw.c | 9 +- drivers/gpu/drm/panthor/panthor_gpu.c | 142 ++++++----------------- drivers/gpu/drm/panthor/panthor_mmu.c | 34 ++---- drivers/gpu/drm/panthor/panthor_regs.h | 6 - 5 files changed, 124 insertions(+), 138 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index da6574021664..40b935fcc1f4 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -428,4 +428,75 @@ static int panthor_request_ ## __name ## _irq(struct p= anthor_device *ptdev, \ =20 extern struct workqueue_struct *panthor_cleanup_wq; =20 +static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 da= ta) +{ + writel(data, ptdev->iomem + reg); +} + +static inline u32 gpu_read(struct panthor_device *ptdev, u32 reg) +{ + return readl(ptdev->iomem + reg); +} + +static inline u32 gpu_read_relaxed(struct panthor_device *ptdev, u32 reg) +{ + return readl_relaxed(ptdev->iomem + reg); +} + +static inline void gpu_write64(struct panthor_device *ptdev, u32 reg, u64 = data) +{ + gpu_write(ptdev, reg, lower_32_bits(data)); + gpu_write(ptdev, reg + 4, upper_32_bits(data)); +} + +static inline u64 gpu_read64(struct panthor_device *ptdev, u32 reg) +{ + return (gpu_read(ptdev, reg) | ((u64)gpu_read(ptdev, reg + 4) << 32)); +} + +static inline u64 gpu_read64_relaxed(struct panthor_device *ptdev, u32 reg) +{ + return (gpu_read_relaxed(ptdev, reg) | + ((u64)gpu_read_relaxed(ptdev, reg + 4) << 32)); +} + +static inline u64 gpu_read64_counter(struct panthor_device *ptdev, u32 reg) +{ + u32 lo, hi1, hi2; + do { + hi1 =3D gpu_read(ptdev, reg + 4); + lo =3D gpu_read(ptdev, reg); + hi2 =3D gpu_read(ptdev, reg + 4); + } while (hi1 !=3D hi2); + return lo | ((u64)hi2 << 32); +} + +#define gpu_read_poll_timeout(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ + dev, reg) + +#define gpu_read_poll_timeout_atomic(dev, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ + false, dev, reg) + +#define gpu_read64_poll_timeout(dev, reg, val, cond, delay_us, timeout_us)= \ + read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ + dev, reg) + +#define gpu_read64_poll_timeout_atomic(dev, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ + false, dev, reg) + +#define gpu_read_relaxed_poll_timeout_atomic(dev, reg, val, cond, delay_us= , \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ + timeout_us, false, dev, reg) + +#define gpu_read64_relaxed_poll_timeout(dev, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ + false, dev, reg) + #endif diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 0f52766a3120..ecfbe0456f89 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -1059,8 +1059,8 @@ static void panthor_fw_stop(struct panthor_device *pt= dev) u32 status; =20 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); - if (readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, - status =3D=3D MCU_STATUS_DISABLED, 10, 100000)) + if (gpu_read_poll_timeout(ptdev, MCU_STATUS, status, + status =3D=3D MCU_STATUS_DISABLED, 10, 100000)) drm_err(&ptdev->base, "Failed to stop MCU"); } =20 @@ -1085,8 +1085,9 @@ void panthor_fw_pre_reset(struct panthor_device *ptde= v, bool on_hang) =20 panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); - if (!readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, - status =3D=3D MCU_STATUS_HALT, 10, 100000)) { + if (!gpu_read_poll_timeout(ptdev, MCU_STATUS, status, + status =3D=3D MCU_STATUS_HALT, 10, + 100000)) { ptdev->reset.fast =3D true; } else { drm_warn(&ptdev->base, "Failed to cleanly suspend MCU"); diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index 671049020afa..fd09f0928019 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -108,14 +108,9 @@ static void panthor_gpu_init_info(struct panthor_devic= e *ptdev) =20 ptdev->gpu_info.as_present =3D gpu_read(ptdev, GPU_AS_PRESENT); =20 - ptdev->gpu_info.shader_present =3D gpu_read(ptdev, GPU_SHADER_PRESENT_LO); - ptdev->gpu_info.shader_present |=3D (u64)gpu_read(ptdev, GPU_SHADER_PRESE= NT_HI) << 32; - - ptdev->gpu_info.tiler_present =3D gpu_read(ptdev, GPU_TILER_PRESENT_LO); - ptdev->gpu_info.tiler_present |=3D (u64)gpu_read(ptdev, GPU_TILER_PRESENT= _HI) << 32; - - ptdev->gpu_info.l2_present =3D gpu_read(ptdev, GPU_L2_PRESENT_LO); - ptdev->gpu_info.l2_present |=3D (u64)gpu_read(ptdev, GPU_L2_PRESENT_HI) <= < 32; + ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT_L= O); + ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT_LO); + ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT_LO); =20 arch_major =3D GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id); product_major =3D GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id); @@ -152,8 +147,7 @@ static void panthor_gpu_irq_handler(struct panthor_devi= ce *ptdev, u32 status) { if (status & GPU_IRQ_FAULT) { u32 fault_status =3D gpu_read(ptdev, GPU_FAULT_STATUS); - u64 address =3D ((u64)gpu_read(ptdev, GPU_FAULT_ADDR_HI) << 32) | - gpu_read(ptdev, GPU_FAULT_ADDR_LO); + u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR_LO); =20 drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n", fault_status, panthor_exception_name(ptdev, fault_status & 0xFF), @@ -244,45 +238,27 @@ int panthor_gpu_block_power_off(struct panthor_device= *ptdev, u32 pwroff_reg, u32 pwrtrans_reg, u64 mask, u32 timeout_us) { - u32 val, i; + u32 val; int ret; =20 - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); - - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 - if (mask & GENMASK(31, 0)) - gpu_write(ptdev, pwroff_reg, mask); - - if (mask >> 32) - gpu_write(ptdev, pwroff_reg + 4, mask >> 32); - - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); + gpu_write64(ptdev, pwroff_reg, mask); =20 - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 return 0; @@ -305,45 +281,26 @@ int panthor_gpu_block_power_on(struct panthor_device = *ptdev, u32 pwron_reg, u32 pwrtrans_reg, u32 rdy_reg, u64 mask, u32 timeout_us) { - u32 val, i; + u32 val; int ret; =20 - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); - - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 - if (mask & GENMASK(31, 0)) - gpu_write(ptdev, pwron_reg, mask); - - if (mask >> 32) - gpu_write(ptdev, pwron_reg + 4, mask >> 32); - - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); + gpu_write64(ptdev, pwron_reg, mask); =20 - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + rdy_reg + (i * 4), - val, (mask32 & val) =3D=3D mask32, - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx readiness", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, "timeout waiting on %s:%llx readiness", + blk_name, mask); + return ret; } =20 return 0; @@ -492,26 +449,6 @@ void panthor_gpu_resume(struct panthor_device *ptdev) panthor_gpu_l2_power_on(ptdev); } =20 -/** - * panthor_gpu_read_64bit_counter() - Read a 64-bit counter at a given off= set. - * @ptdev: Device. - * @reg: The offset of the register to read. - * - * Return: The counter value. - */ -static u64 -panthor_gpu_read_64bit_counter(struct panthor_device *ptdev, u32 reg) -{ - u32 hi, lo; - - do { - hi =3D gpu_read(ptdev, reg + 0x4); - lo =3D gpu_read(ptdev, reg); - } while (hi !=3D gpu_read(ptdev, reg + 0x4)); - - return ((u64)hi << 32) | lo; -} - /** * panthor_gpu_read_timestamp() - Read the timestamp register. * @ptdev: Device. @@ -520,7 +457,7 @@ panthor_gpu_read_64bit_counter(struct panthor_device *p= tdev, u32 reg) */ u64 panthor_gpu_read_timestamp(struct panthor_device *ptdev) { - return panthor_gpu_read_64bit_counter(ptdev, GPU_TIMESTAMP_LO); + return gpu_read64_counter(ptdev, GPU_TIMESTAMP_LO); } =20 /** @@ -531,10 +468,5 @@ u64 panthor_gpu_read_timestamp(struct panthor_device *= ptdev) */ u64 panthor_gpu_read_timestamp_offset(struct panthor_device *ptdev) { - u32 hi, lo; - - hi =3D gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_HI); - lo =3D gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_LO); - - return ((u64)hi << 32) | lo; + return gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET_LO); } diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/pantho= r/panthor_mmu.c index 12a02e28f50f..a0a79f19bdea 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -510,9 +510,9 @@ static int wait_ready(struct panthor_device *ptdev, u32= as_nr) /* Wait for the MMU status to indicate there is no active command, in * case one is pending. */ - ret =3D readl_relaxed_poll_timeout_atomic(ptdev->iomem + AS_STATUS(as_nr), - val, !(val & AS_STATUS_AS_ACTIVE), - 10, 100000); + ret =3D gpu_read_relaxed_poll_timeout_atomic(ptdev, AS_STATUS(as_nr), val, + !(val & AS_STATUS_AS_ACTIVE), + 10, 100000); =20 if (ret) { panthor_device_schedule_reset(ptdev); @@ -564,8 +564,7 @@ static void lock_region(struct panthor_device *ptdev, u= 32 as_nr, region =3D region_width | region_start; =20 /* Lock the region that needs to be updated */ - gpu_write(ptdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); - gpu_write(ptdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); + gpu_write64(ptdev, AS_LOCKADDR_LO(as_nr), region); write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); } =20 @@ -615,14 +614,9 @@ static int panthor_mmu_as_enable(struct panthor_device= *ptdev, u32 as_nr, if (ret) return ret; =20 - gpu_write(ptdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab)); - gpu_write(ptdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab)); - - gpu_write(ptdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); - gpu_write(ptdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); - - gpu_write(ptdev, AS_TRANSCFG_LO(as_nr), lower_32_bits(transcfg)); - gpu_write(ptdev, AS_TRANSCFG_HI(as_nr), upper_32_bits(transcfg)); + gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), transtab); + gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), memattr); + gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), transcfg); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -635,14 +629,9 @@ static int panthor_mmu_as_disable(struct panthor_devic= e *ptdev, u32 as_nr) if (ret) return ret; =20 - gpu_write(ptdev, AS_TRANSTAB_LO(as_nr), 0); - gpu_write(ptdev, AS_TRANSTAB_HI(as_nr), 0); - - gpu_write(ptdev, AS_MEMATTR_LO(as_nr), 0); - gpu_write(ptdev, AS_MEMATTR_HI(as_nr), 0); - - gpu_write(ptdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); - gpu_write(ptdev, AS_TRANSCFG_HI(as_nr), 0); + gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), 0); + gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), 0); + gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -1680,8 +1669,7 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) u32 source_id; =20 fault_status =3D gpu_read(ptdev, AS_FAULTSTATUS(as)); - addr =3D gpu_read(ptdev, AS_FAULTADDRESS_LO(as)); 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 15:12:13.6254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddbf6086-451b-45a0-3cad-08dd790b3d52 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A797.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9391 Content-Type: text/plain; charset="utf-8" With the introduction of 64-bit register accessors, the separate *_HI definitions are no longer necessary. This change removes them and renames the corresponding *_LO entries for cleaner and more consistent register definitions. Suggested-by: Boris Brezillon Signed-off-by: Karunika Choo Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panthor/panthor_gpu.c | 12 ++-- drivers/gpu/drm/panthor/panthor_gpu.h | 10 +-- drivers/gpu/drm/panthor/panthor_mmu.c | 16 ++--- drivers/gpu/drm/panthor/panthor_regs.h | 94 +++++++++----------------- 4 files changed, 52 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index fd09f0928019..5fc45284c712 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -108,9 +108,9 @@ static void panthor_gpu_init_info(struct panthor_device= *ptdev) =20 ptdev->gpu_info.as_present =3D gpu_read(ptdev, GPU_AS_PRESENT); =20 - ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT_L= O); - ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT_LO); - ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT_LO); + ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT); + ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT); + ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT); =20 arch_major =3D GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id); product_major =3D GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id); @@ -147,7 +147,7 @@ static void panthor_gpu_irq_handler(struct panthor_devi= ce *ptdev, u32 status) { if (status & GPU_IRQ_FAULT) { u32 fault_status =3D gpu_read(ptdev, GPU_FAULT_STATUS); - u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR_LO); + u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR); =20 drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n", fault_status, panthor_exception_name(ptdev, fault_status & 0xFF), @@ -457,7 +457,7 @@ void panthor_gpu_resume(struct panthor_device *ptdev) */ u64 panthor_gpu_read_timestamp(struct panthor_device *ptdev) { - return gpu_read64_counter(ptdev, GPU_TIMESTAMP_LO); + return gpu_read64_counter(ptdev, GPU_TIMESTAMP); } =20 /** @@ -468,5 +468,5 @@ u64 panthor_gpu_read_timestamp(struct panthor_device *p= tdev) */ u64 panthor_gpu_read_timestamp_offset(struct panthor_device *ptdev) { - return gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET_LO); + return gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET); } diff --git a/drivers/gpu/drm/panthor/panthor_gpu.h b/drivers/gpu/drm/pantho= r/panthor_gpu.h index 7f6133a66127..89a0bdb2fbc5 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.h +++ b/drivers/gpu/drm/panthor/panthor_gpu.h @@ -30,9 +30,9 @@ int panthor_gpu_block_power_off(struct panthor_device *pt= dev, */ #define panthor_gpu_power_on(ptdev, type, mask, timeout_us) \ panthor_gpu_block_power_on(ptdev, #type, \ - type ## _PWRON_LO, \ - type ## _PWRTRANS_LO, \ - type ## _READY_LO, \ + type ## _PWRON, \ + type ## _PWRTRANS, \ + type ## _READY, \ mask, timeout_us) =20 /** @@ -42,8 +42,8 @@ int panthor_gpu_block_power_off(struct panthor_device *pt= dev, */ #define panthor_gpu_power_off(ptdev, type, mask, timeout_us) \ panthor_gpu_block_power_off(ptdev, #type, \ - type ## _PWROFF_LO, \ - type ## _PWRTRANS_LO, \ + type ## _PWROFF, \ + type ## _PWRTRANS, \ mask, timeout_us) =20 int panthor_gpu_l2_power_on(struct panthor_device *ptdev); diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/pantho= r/panthor_mmu.c index a0a79f19bdea..1db4a46ddf98 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -564,7 +564,7 @@ static void lock_region(struct panthor_device *ptdev, u= 32 as_nr, region =3D region_width | region_start; =20 /* Lock the region that needs to be updated */ - gpu_write64(ptdev, AS_LOCKADDR_LO(as_nr), region); + gpu_write64(ptdev, AS_LOCKADDR(as_nr), region); write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); } =20 @@ -614,9 +614,9 @@ static int panthor_mmu_as_enable(struct panthor_device = *ptdev, u32 as_nr, if (ret) return ret; =20 - gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), transtab); - gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), memattr); - gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), transcfg); + gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab); + gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr); + gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -629,9 +629,9 @@ static int panthor_mmu_as_disable(struct panthor_device= *ptdev, u32 as_nr) if (ret) return ret; =20 - gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), 0); - gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), 0); - gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); + gpu_write64(ptdev, AS_TRANSTAB(as_nr), 0); + gpu_write64(ptdev, AS_MEMATTR(as_nr), 0); + gpu_write64(ptdev, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -1669,7 +1669,7 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) u32 source_id; =20 fault_status =3D gpu_read(ptdev, AS_FAULTSTATUS(as)); - addr =3D gpu_read64(ptdev, AS_FAULTADDRESS_LO(as)); + addr =3D gpu_read64(ptdev, AS_FAULTADDRESS(as)); =20 /* decode the fault status */ exception_type =3D fault_status & 0xFF; diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panth= or/panthor_regs.h index 6fd39a52f887..7e21d6a25dc4 100644 --- a/drivers/gpu/drm/panthor/panthor_regs.h +++ b/drivers/gpu/drm/panthor/panthor_regs.h @@ -65,20 +65,16 @@ #define GPU_STATUS_DBG_ENABLED BIT(8) =20 #define GPU_FAULT_STATUS 0x3C -#define GPU_FAULT_ADDR_LO 0x40 -#define GPU_FAULT_ADDR_HI 0x44 +#define GPU_FAULT_ADDR 0x40 =20 #define GPU_PWR_KEY 0x50 #define GPU_PWR_KEY_UNLOCK 0x2968A819 #define GPU_PWR_OVERRIDE0 0x54 #define GPU_PWR_OVERRIDE1 0x58 =20 -#define GPU_TIMESTAMP_OFFSET_LO 0x88 -#define GPU_TIMESTAMP_OFFSET_HI 0x8C -#define GPU_CYCLE_COUNT_LO 0x90 -#define GPU_CYCLE_COUNT_HI 0x94 -#define GPU_TIMESTAMP_LO 0x98 -#define GPU_TIMESTAMP_HI 0x9C +#define GPU_TIMESTAMP_OFFSET 0x88 +#define GPU_CYCLE_COUNT 0x90 +#define GPU_TIMESTAMP 0x98 =20 #define GPU_THREAD_MAX_THREADS 0xA0 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4 @@ -87,47 +83,29 @@ =20 #define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4)) =20 -#define GPU_SHADER_PRESENT_LO 0x100 -#define GPU_SHADER_PRESENT_HI 0x104 -#define GPU_TILER_PRESENT_LO 0x110 -#define GPU_TILER_PRESENT_HI 0x114 -#define GPU_L2_PRESENT_LO 0x120 -#define GPU_L2_PRESENT_HI 0x124 - -#define SHADER_READY_LO 0x140 -#define SHADER_READY_HI 0x144 -#define TILER_READY_LO 0x150 -#define TILER_READY_HI 0x154 -#define L2_READY_LO 0x160 -#define L2_READY_HI 0x164 - -#define SHADER_PWRON_LO 0x180 -#define SHADER_PWRON_HI 0x184 -#define TILER_PWRON_LO 0x190 -#define TILER_PWRON_HI 0x194 -#define L2_PWRON_LO 0x1A0 -#define L2_PWRON_HI 0x1A4 - -#define SHADER_PWROFF_LO 0x1C0 -#define SHADER_PWROFF_HI 0x1C4 -#define TILER_PWROFF_LO 0x1D0 -#define TILER_PWROFF_HI 0x1D4 -#define L2_PWROFF_LO 0x1E0 -#define L2_PWROFF_HI 0x1E4 - -#define SHADER_PWRTRANS_LO 0x200 -#define SHADER_PWRTRANS_HI 0x204 -#define TILER_PWRTRANS_LO 0x210 -#define TILER_PWRTRANS_HI 0x214 -#define L2_PWRTRANS_LO 0x220 -#define L2_PWRTRANS_HI 0x224 - -#define SHADER_PWRACTIVE_LO 0x240 -#define SHADER_PWRACTIVE_HI 0x244 -#define TILER_PWRACTIVE_LO 0x250 -#define TILER_PWRACTIVE_HI 0x254 -#define L2_PWRACTIVE_LO 0x260 -#define L2_PWRACTIVE_HI 0x264 +#define GPU_SHADER_PRESENT 0x100 +#define GPU_TILER_PRESENT 0x110 +#define GPU_L2_PRESENT 0x120 + +#define SHADER_READY 0x140 +#define TILER_READY 0x150 +#define L2_READY 0x160 + +#define SHADER_PWRON 0x180 +#define TILER_PWRON 0x190 +#define L2_PWRON 0x1A0 + +#define SHADER_PWROFF 0x1C0 +#define TILER_PWROFF 0x1D0 +#define L2_PWROFF 0x1E0 + +#define SHADER_PWRTRANS 0x200 +#define TILER_PWRTRANS 0x210 +#define L2_PWRTRANS 0x220 + +#define SHADER_PWRACTIVE 0x240 +#define TILER_PWRACTIVE 0x250 +#define L2_PWRACTIVE 0x260 =20 #define GPU_REVID 0x280 =20 @@ -170,10 +148,8 @@ #define MMU_AS_SHIFT 6 #define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT)) =20 -#define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x0) -#define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x4) -#define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x8) -#define AS_MEMATTR_HI(as) (MMU_AS(as) + 0xC) +#define AS_TRANSTAB(as) (MMU_AS(as) + 0x0) +#define AS_MEMATTR(as) (MMU_AS(as) + 0x8) #define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2) #define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \ ((w) ? BIT(0) : 0) | \ @@ -185,8 +161,7 @@ #define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6) #define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6) #define AS_MEMATTR_AARCH64_FAULT (3 << 6) -#define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) -#define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) +#define AS_LOCKADDR(as) (MMU_AS(as) + 0x10) #define AS_COMMAND(as) (MMU_AS(as) + 0x18) #define AS_COMMAND_NOP 0 #define AS_COMMAND_UPDATE 1 @@ -201,12 +176,10 @@ #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8) #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8) #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8) -#define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) -#define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) +#define AS_FAULTADDRESS(as) (MMU_AS(as) + 0x20) #define AS_STATUS(as) (MMU_AS(as) + 0x28) #define AS_STATUS_AS_ACTIVE BIT(0) -#define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) -#define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) +#define AS_TRANSCFG(as) (MMU_AS(as) + 0x30) #define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0) #define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0) #define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0) @@ -224,8 +197,7 @@ #define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34) #define AS_TRANSCFG_WXN BIT(35) #define AS_TRANSCFG_XREADABLE BIT(36) -#define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) -#define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) +#define AS_FAULTEXTRA(as) (MMU_AS(as) + 0x38) =20 #define CSF_GPU_LATEST_FLUSH_ID 0x10000 =20 --=20 2.47.1