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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 13:32:15.6488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f7e9f3b-099d-4861-f223-08dd78fd464d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7452 Content-Type: text/plain; charset="utf-8" - Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a synchronization method. By defining, a register access path, we use APML modules and library for all APML transactions. Without having to use external tools such as i2c-tools, which may cause race conditions. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta --- Changes since v7: - Address Arnd comment: - New IOCTL and structure defined to separate ioctl for each protocol Changes since v6: - Rebased patch, previously patch 10 Changes since v5: - Patch rebased Changes since v4: - Previously patch 8 - Address review comment for documentation warning Changes since v3: - Add ioctl description comment Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 29 +++++++++++++++++++++++++++++ include/uapi/misc/amd-apml.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-cor= e.c index 171d6e871373..b653a21a909e 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -350,6 +350,33 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, return ret; } =20 +static int apml_rmi_reg_xfer(struct sbrmi_data *data, + struct apml_reg_xfer_msg __user *arg) +{ + struct apml_reg_xfer_msg msg =3D { 0 }; + unsigned int data_read; + int ret; + + /* Copy the structure from user */ + if (copy_from_user(&msg, arg, sizeof(struct apml_reg_xfer_msg))) + return -EFAULT; + + mutex_lock(&data->lock); + if (msg.rflag) { + ret =3D regmap_read(data->regmap, msg.reg_addr, &data_read); + if (!ret) + msg.data_in_out =3D data_read; + } else { + ret =3D regmap_write(data->regmap, msg.reg_addr, msg.data_in_out); + } + + mutex_unlock(&data->lock); + + if (msg.rflag && !ret) + return copy_to_user(arg, &msg, sizeof(struct apml_reg_xfer_msg)); + return ret; +} + static int apml_mailbox_xfer(struct sbrmi_data *data, struct apml_mbox_msg= __user *arg) { struct apml_mbox_msg msg =3D { 0 }; @@ -414,6 +441,8 @@ static long sbrmi_ioctl(struct file *fp, unsigned int c= md, unsigned long arg) return apml_cpuid_xfer(data, argp); case SBRMI_IOCTL_MCAMSR_CMD: return apml_mcamsr_xfer(data, argp); + case SBRMI_IOCTL_REG_XFER_CMD: + return apml_rmi_reg_xfer(data, argp); default: return -ENOTTY; } diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index f718675d3966..3b5f5af61a1e 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -58,6 +58,21 @@ struct apml_mcamsr_msg { __u32 pad; }; =20 +struct apml_reg_xfer_msg { + /* + * RMI register address offset + */ + u16 reg_addr; + /* + * Register data for read/write + */ + u8 data_in_out; + /* + * Register read or write + */ + u8 rflag; +}; + /* * AMD sideband interface base IOCTL */ @@ -118,4 +133,20 @@ struct apml_mcamsr_msg { */ #define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mca= msr_msg) =20 +/** + * DOC: SBRMI_IOCTL_REG_XFER_CMD + * + * @Parameters + * + * @struct apml_reg_xfer_msg + * Pointer to the &struct apml_reg_xfer_msg that will contain the protocol + * information + * + * @Description + * IOCTL command for APML messages using generic _IOWR + * The IOCTL provides userspace access to AMD sideband register xfer proto= col + * - Register xfer protocol to get/set hardware register for given offset + */ +#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_re= g_xfer_msg) + #endif /*_AMD_APML_H_*/ --=20 2.25.1