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charset="utf-8" Add support for setting the number of lanes enabled. Signed-off-by: Antoniu Miclaus --- no changes in v2. drivers/iio/adc/adi-axi-adc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 0d12c0121bbc..8576c0c1d024 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -44,6 +44,7 @@ #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) =20 #define ADI_AXI_ADC_REG_CTRL 0x0044 +#define AXI_AD408X_CTRL_NUM_LANES_MSK GENMASK(12, 8) #define AXI_AD408X_CTRL_BITSLIP_EN_MSK BIT(3) #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 @@ -471,6 +472,19 @@ static int axi_adc_sync_status_get(struct iio_backend = *back, bool *sync_en) return 0; } =20 +static int axi_adc_ad408x_num_lanes_set(struct iio_backend *back, + unsigned int num_lanes) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + if (!num_lanes) + return -EINVAL; + + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, + AXI_AD408X_CTRL_NUM_LANES_MSK, + FIELD_PREP(AXI_AD408X_CTRL_NUM_LANES_MSK, num_lanes)); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -667,6 +681,7 @@ static const struct iio_backend_ops adi_ad408x_ops =3D { .self_sync_enable =3D axi_adc_ad408x_self_sync_enable, .self_sync_disable =3D axi_adc_ad408x_self_sync_disable, .sync_status_get =3D axi_adc_sync_status_get, + .num_lanes_set =3D axi_adc_ad408x_num_lanes_set, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), }; --=20 2.49.0